Algorithms for Simultaneous
Satisfaction of Multiple Constraints
and
Objective Optimization
in a Placement Flow
with Application to Congestion Control
Ke Zhong and Shantanu Dutt
June 10, 2002
Department of Electrical and Computer Engineering,
University of Illinois at Chicago
Overview
 Motivation
 Constraint-driven optimization with intermediate
relaxation
 Constraint modeling and classification
 Tackling multiple constraints: efficient violation
correction and minimum objective deterioration
 Application to congestion-driven placement
 Experimental results
 Conclusions and future work
Motivation
 Placement for Deep Sub-Micron (DSM) circuits
 Primary
objectives: wire length, timing and power
 Other design requirements



Routability of large circuits
Cross-talk bounding
Uniform thermal distribution
 Modeling as a set of constraints: multiple objectives
and secondary design requirements
 Addressing
several constraints simultaneously
 Lack of a general multi-constraint approach
 Design
req.’s handled during post-placement phases:
smaller solution space available
 Primary objective deterioration: no general method to
control it while satisfying multiple constraints
Rationale for a PDP-based Approach
 Partitioning-driven placement (PDP)
A
divide-and-conquer approach: time-efficient
(e.g., [Wang et al, ICCAD ‘00, Huang et al, ICCAD ‘97,
Zhong et al, ICCAD ‘00])
 Balanced
placement decision with a global view
 Flexible in tackling multiple constraints
 Flexible in tackling most primary objectives
(e.g., [Dutt, TAU ‘97, Marek-Sadowska et al, ICCAD ’89])
 An example of recursive 2-way PDP hierarchy
2’
1
1
2
2
2’
Constraint Satisfaction
-- Indirect Approaches
 Post-processing approach
 Ignores
constraints in optimization phase (path 1(a))
 Legalization of solutions follows (path 1(b))
 In-processing approach w/ mixed objective
 No
strict control over either aspect (path 1(c) or 1(c’))
 Final solutions typically neither global optima nor
(good) local optima
T’2
1(a)
S
1(c' )
1(c )
T2
T1
1(b)
Constraint Satisfaction
-- Direct Approaches
 In-processing approach w/o constraint violation
 Traditional: no visit of any illegal solution (path 1(d))

Leading to local optima
 In-processing w/ intermediate relaxation (new approach)
 Allows temporary visit to illegal solutions (path 1(e))


Must reach a legal solution at the end of search
Potentially leading to (near) global optima
T
1(e)
S
1(d)
T3
4
Constraint Satisfaction -- Our Approach:
Intermediate Relaxation
 Correctability of illegal moves
 Need
a short sequence of moves for legalization
 Gain estimation for intermediate relaxation
 Obtain
better solution than without relaxation:
over a set of illegal/correcting moves
 Proceed with intermediate relaxation only if both
issues are positively resolved
Constraint Modeling and Classification
 Context of discussion: recursive 2-way PDP for
standard-cell circuits (also applicable to other styles)
 Fixed-height
cells placed into rows
 Row sets divided into sub-row-sets by horizontal cuts
 SPADE placement algorithm [Zhong et al, ICCAD ‘00]
 Produced
promising wire length results
 Local-size and row-size constraints: balanced cell-area
distribution into sub-regions and sub-row-sets
Sub-row-set 1
Row set
Sub-row-set 0
Constraint Modeling and Classification
(contd.)
E.g., local-size &
row-size constr.
E.g., local-size &
row-size constr.
B-constr. metric:
function of constraintrelated metrics over all
cells/nets in a subset
M-constr: cell moves
always increase metric
value in target subset
Balance constr.
Constraints
Non-balance constr.
Monotonic constr.
Non-monotonic constr.
Non-B-constr:
limiting per-component
metrics to be within
their respective ranges
Non-M-constr: cell moves
may increase or decrease
metric in target subset
E.g., cross-talk bounding
(individual pairs of wires)
E.g., pin-density constr,
p-dst. = (pin #)/(cell area)
Constraint Modeling and Classification
(contd.)
 Formal definition of balance constraint
Bi: constraint metric of subset i; B: sum of B0 and B1
 r : desired balance ratio B0 : B1  r : (1  r ), which means
B0  B  (r  δ),
B1  B  (1  r  δ)

 Normalized
form (for uniform constraint handling):
b0  (B0 / B)  r  δ,
b1  (B1 / B)  1  r  δ
 Normalized cell constraint weight (c-weight)
A
vector assigned to cell u, each element w i (u) of which
equals change in b0 (b1) of constraint c i due to u’s move

C-weights can be +ve or -ve (can be -ve for non-mono. only)
 To
correct a violation: move cells with positive
(negative) c-weights out of (into) the violating subset
-
+
Amount of
Violation
Recall: Solution Space View
?
Single-Constraint Intermediate Relaxation
 The concept of single-constraint intermediate
relaxation first introduced in [Dutt et al, ICCAD ‘97]
 Non-backtracking branch-and-bound (B&B) search
correctability: rev(u)  R  Φ
 For gain estimation: gain(u)  gain(R  rev(u) | u)  gain(R)
 For
current best move,
adding to violation
u
violating moves
not yet corrected
R
rev(u)
best correcting
moves for u
T
correcting moves
reserved for T
Multi-Constraint Intermediate Relaxation
 Violation correction: significantly increased
complexity
 Conflicting
constraints: a cell move reducing one
constraint violation might increase another
 Critically violated constraint: with largest normalized
deviation from its metric limit
 Convergence: reduce the maximum of all violations

Decreasing violation rule: every correcting move
produces progressively smaller maximum violation
 Controlling primary objective degradation
 Balanced
consideration of violation correction and
primary optimization
 Accurate gain estimation for violating moves
Multi-Constraint Intermediate Relaxation
(contd.)
 Need a mixed measure of a cell’s gain and its ability
to correct constraint violation
A
vector of gain-c-weights (gcw) for cell u, each
element GW (u, ci ) of which corresponds to constraint c i




F and G: two monotonically increasing functions
g(u): the gain of cell u
‘max’ operator: a move to correct violation of c i should
have limited impact on other constraints
For each constraint cells are sorted into BST’s in
decreasing order of corresponding gcw values
w i (u)
GW (u, c i )  F(g(u))  G(
)
max j w j (u)
Subset 1
move u
max viol.
Subset 0
Constraint violations
cell u
max c-wt.
new violations
c-weights of u
Multi-Constraint Intermediate Relaxation
(contd.)
 Feasibility estimation: ‘short’ correcting sequence
 Move
of u will newly produce or increase violation
 Need a possible set of correcting moves: rev(u)



Search gcw trees of current critically violated constraint
for cells not belonging to R
Jump from tree to tree when crit. viol. constr. changes
rev(u) exists if violations can be resolved within
a certain number of correcting moves
 If
rev(u) found, gain estimation then performed
same as in single-constraint case:
gain(u)  gain(R  rev(u) | u)  gain(R)
maximum
violation 14
amount
10
9
u
rev(u)
Violations resolved
Cell move
Multi-Constraint Intermediate Relaxation
(contd.)
 Learning-based backtracking
 Actual
correcting move sequences may not be ‘short’
 Learning: new moves get low enough violation to be
resolved based on previous reduction gradient
11
Init. viol. move
Most Crit.
Constr. 3
Viol:
10(8)
5
1
3
6
Red:
original
moves
Yellow:
alternative
moves
Constr. 4
Constr. 1
Constraint-Based Congestion Reduction
-- Introduction
 Congestion-driven placement problem
 Reduce
routing congestion with better placement
u
move u
u
Constraint-Based Congestion Reduction
-- Previous Work
 In-processing with mixed objective

[Wang et al, TCAD ‘00] concluded congestion-inclusive
objectives didn’t work very well
 Post-processing approaches to congestion reduction
 In
[Wang et al, TCAD ‘00], greedy net-centric congestion
reduction performed
 In [Yang et al, ICCAD ‘01], region expansion limits set by
global ILP, followed by greedy random cell swaps
 In [Parakh et al, DAC ‘98], congestion estimated after
each level of partitioning and quadratic placement

Regions expanded/compressed based on congestion est.
 These previous methods generally do not have
control over wire length deterioration (though postprocessing methods yield small WL increase)
Constraint-Based Congestion Reduction
-- In-Processing Constraint Satisfaction
 Two constraints for congestion control
 Pin


density constraint
Pin density Pd=(total pin # P)/(total cell area A) in a subset
Evenly distributed connection density in all regions
 External




net balancing constraint
Proportionate distribution of external net counts (parallel
to current cutlines) with the same ratio as local-size
Using connectors to keep track of external net crossings
Enables an even net distribution across routing channels
An approximate global route planning
r
V0
1-r
V1
External nets
parallel to
cutline
Connectors
Constraint-Based Congestion Reduction
(contd.)
 Algorithm for connector determination
New connector generation (at end of move process):
for any net segment that is finally cut (fig. (a))
 Existing connector propagation (during move process):
depends on cut status of its connected net segments
 Find a geometrically closest pair of sub-segments, one
from either of Ns0 and Ns1 (for connector x)
 Direct route between the two yields new location (fig. (b))
 May be up to two possible locations for x: both accepted
with a weight of 0.5 (fig. (c))
 More new connectors generated for complete routes

 Need
Ns0
refinements for MST routing -- on-going work
x
Ns1
(a) new connector x
new
conn.
y
0.5
x move weight
u
conn.
cell u y & y’
(b) propagation of x
x
x’
(c) two possible locations
Experimental Results
 PDP engine: SPADE [Zhong et al, ICCAD ‘00] based on
SHRINK-PROP [Dutt et al, TCAD ‘00] partitioner
 Benchmarks: MCNC suite (up to 100k cells) and the first
five IBM-PLACE circuits (up to 30k cells)
 Overall congestion measured as overflow, which is wiring
demand minus supply
 Wiring demand: final connector counts in each
sub-channel within any region
 Wiring supply proportional to Demandbase * log(P)
 Hard to make apples-to-apples comp. w/ prev. works
 Lack of a generally agreed model for defining wiring
supply and congestion
Experimental Results (contd.)
160.0%
3.0%
No constr.
140.0%
2.5%
120.0%
2.0%
100.0%
Alg.
Alg.
Alg.
Alg.
1.5%
80.0%
60.0%
1.0%
40.0%
0.5%
20.0%
I
II
III
IV
+ 2 congst. constr.
1-step viol.
+ Feasiblt. Est. &
Learn-based btr.
+ Mult-step viol.
0.0%
0.0%
Overflow
diff(WL)
Time
 One-step vs. multi-step violation: start correction as soon as
violations appear vs. not until violation reaches some limit
 Consistent improvement in congestion (avg. 6.5% for alg. II,
14.3% in III, and 13.7% for IV)
 Very little WL increase (avg. 2.4% for alg. II; 1.6% for III,
reduced to 0.7% with multi-step violation for IV)
Experimental Results (contd.)
160.0%
140.0%
120.0%
100.0%
Alg. I
Alg. IV
80.0%
60.0%
40.0%
20.0%
0.0%
Overflow
WL
Time
 More results on alg. IV w/ an improved PDP engine
4-way partitioning, multi-level SHRINK-PROP
 Original WL within +/- 1-2% of Dragon [Wang et al, ICCAD ‘00]
 Tested on ibm01-15 of IBM-PLACE suite (up to 150k cells)
 Overflow reduced by 15.2% with WL increase of only 0.9%
 Our methodology scales well with circuit size

Conclusions and Future Work
 Two major contributions
 For
the first time, a general methodology for tackling
multiple constraints during a PDP process


Intermediate relaxation and efficient violation correction
Balanced consideration of constraint satisfaction and
primary optimization
 Constraint-based



congestion modeling and reduction
Two constraints: pin-density and external-net balancing
Approximate global route planning: connector generation
Effectiveness: reduced overflow by 14.3 -- 15.2% and
chip area by 8.9%, w/ only 0.9 -- 1.6% increase in wire
length
 Future work
 Apply
the general algorithms to other constraints and
objectives (timing, power, etc.)
 Construct a ‘shell’ containing all our algorithms, that
can handle user-specified constraints