Analog Integr Circ Sig Process (2010) 65:273–282
DOI 10.1007/s10470-010-9469-5
Design of output buffer with low switching noise and load
adaptability
Yingyan Lin • Jing Zhang • Xuecheng Zou
Dongsheng Liu • Shuang-yang Wang
•
Received: 7 March 2009 / Revised: 30 October 2009 / Accepted: 8 March 2010 / Published online: 8 April 2010
Ó Springer Science+Business Media, LLC 2010
Abstract A new CMOS output buffer with low switching
noise and load adaptability is presented in this paper. By
designing an innovative combination structure of two
driving stages, the buffer can reduce switching noise and
output ringing with no penalty on signal transmission
speed. Furthermore, the buffer can automatically adjust the
total driving capability in response to variation of loading
condition, the load adaptive method is simple and effective
without the necessity for a feedback circuit. The proposed
buffer has been designed in a TSMC 90 nm CMOS process. Simulation results demonstrate that the proposed
buffer achieves 4.1–53.5% improvements in ground
bounce and 2.9–15.2% reductions in output ringing compared with those of the AC/DC buffer. Meanwhile, it
reduces ground bounce by 6.5–17.6% and output ringing
by 3.8–10.9% relative to the CSR buffer.
Keywords Ground bounce Load adaptability Output buffer Output ringing Switching noise
1 Introduction
At present the semiconductor device market demands the
manufacture of storage devices with increasingly higher
operating frequencies, and this triggers another surge in the
need to have available output buffers with increasingly
Y. Lin (&) J. Zhang X. Zou D. Liu (&) S. Wang
Department of Electronic Science & Technology, Huazhong
University of Science & Technology, Wuhan 430074,
People’s Republic of China
e-mail: [email protected]; [email protected]
D. Liu
e-mail: [email protected]
higher switching speed. Consequently, the output buffer
should have enough current to meet the requirement of
transmission speed. This means a considerable current
change during a short time (di/dt), which will cause
switching noises on the power supply lines. In the case of
large capacitive loads, non-negligible voltage bumps are
observed on the power supply lines. These are due mainly
to the inductive bond wires, package and board traces,
which will result in power supply and ground bounces (also
called switching noise or Ldi/dt noise). This noise can lead
to data transition delay, oscillations at the end of signal
transitions and cross-talk between adjacent signal lines
[1–3]. Moreover, it can even cause malfunctions of the
circuits that are connected to the same supply lines.
Over the years, numerous low-noise designs have been
proposed. One of the commonly practiced techniques is
current controlled buffer [4, 5], which adjusts the driving
capability of the pre-driver so as to keep the driving current
nearly constant. The drawback of this technique is the
increase of the rise time as well as propagation delay of the
buffer. Using CSR (controlled slew rate) buffer [6–8] is
another frequently accepted scheme. Fundamental idea of
the CSR design is to limit switching current at the early
stage of output transitions, and then gradually increase the
driving capability to provide sufficient speed. Since the
driving capability is reduced at the beginning of transitions,
it can decrease the maximum value of switching noise.
Nevertheless, under-damped cases, which will cause output
ringing, may occur due to the large driving capability at the
end of transitions.
In addition to speed and switching noise, many other
issues should be taken into account in the design of output
buffer, e.g., short-circuit current and load insensitivity.
Since the variability of load transmission line characteristics, i.e., the capacitance of the load, renders it very
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Analog Integr Circ Sig Process (2010) 65:273–282
difficult to optimize buffer driving capability, an output
buffer with load adaptability is highly desired. The
adjustable output driver [9] can switch between fast and
slow modes, which enable the users to select operating
mode that best suits their application. Its drawback is that
switching of the fast and slow modes is not real time but
only in the assembly processing. Besides, several feedback
monitoring methods [3, 10, 11] to implement load adaptability have been published. However, to adapt a wide
range of output loads, the feedback circuit may introduce
significant complexity to the buffer design.
A new circuit solution for output buffer is proposed in
this paper. The limited driving capability at the beginning
of output transition together with adaptive adjustment of
the total driving capability enables the switching noise to
be kept at a reduced value. Moreover, the buffer reduces
output ringing by automatically cutting off one driving
stage near the end of transition response. Besides, the
combined driving capability is adaptive to loading condition by a simple, non-feedback mechanism. The paper is
organized as follows. In Sect. 2, specific design considerations on output ringing, load adaptability and switching
noise are discussed and analyzed. The circuit diagram and
operation of the proposed buffer are described in detail in
Sect. 3. Section 4 compares performance of the proposed
buffer with those of the previous buffers. Finally, conclusion is drawn in Sect. 5.
2 Design considerations
Figure 1 is the equivalent electrical model of a conventional output buffer driving a receiver through bond wires
and signal traces [3]. Rsub, Lsub and Csub represent the
package, whereas RGND, LGND, RVCC and LVCC model the
inductance and resistance of the ground and power-supply
lines, respectively. Since the lumped approximation holds
when interconnects are short compared to wavelength or
rise time, a lumped inductance is enough for reasonable
values of line length and capacitive load [12], the PCB
track can be neglected (Td = 0/s). Furthermore, the substrate capacitance is negligible compared with the loading
capacitor CLOAD while the resistance of the signal track can
be disregarded relative to resistance of the output buffer in
practical cases. Therefore, the ground loop circuit in Fig. 1
can be modeled fairly well by the series RLC circuit in
Fig. 2(a), the transfer function of which is a second order
ordinary differential equation as follow:
Vout
1
¼ 2
s LC þ sRC þ 1
Vin
ð1Þ
In a given system, the values of the capacitance and
inductance in Eq. 1 will remain relatively constant and the
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Fig. 1 Conventional output buffer driving a receiver through a
transmission line
resistance is thus the primary component determining
whether an oscillating behavior will appear at the power
supply or ground lines of a chip:
pffiffiffiffiffiffiffiffiffi
R\2 L=C under-damped
ð2Þ
pffiffiffiffiffiffiffiffiffi
R 2 L=C critically damped or over-damped
ð3Þ
Aiming to deal with the contradiction among transition
speed, output ringing, and switching noise, the buffer is
proposed based mainly upon the following idea: the initial
transition is characterized by increased output resistance so
that the maximum value of switching noise is limited.
During the middle stage of transition, the buffer should
have smaller output resistance to provide sufficient driving
capability and guarantee fast transition response. Finally,
the output equivalent resistance is enhanced at the end of
transition so that oscillation as well as large output ringing
is avoided.
2.1 Minimizing output ringing
An embryo structure of the proposed driving stage in Fig. 3
is firstly analyzed to illustrate the proposed trade-off design
between transition speed and output ringing. As shown in
Fig. 3, the embryo structure includes a pull-up driver and a
pull-down driver. Since the pull-up and pull-down drivers
are similar, analysis here focuses on only the pull-up driver
for brevity. Two branches including pull-up transistors P1,
P2 as well as diode-connected transistor P0 coupled
between the output node and power supply are designed in
the pull-up driver. As we know, in a conventional twobranch driving stages, the equivalent resistances of the
driving MOS devices are in parallel, thus the total resistance will be very small if all MOS devices operate in
linear region, which is usually the case at the end of output
transition for common-source drivers. Moreover, the MOS
resistance in linear region is inversely proportional to the
Analog Integr Circ Sig Process (2010) 65:273–282
275
Fig. 2 a Equivalent RLC
circuit and b its step response
with different values of
resistance (L = 3 nH,
C = 30 pF)
current is now due only to transistor P2. This behavior
results in increased output resistance when the output is
reaching its final VCC voltage, so that the output ringing
will be reduced. As a consequence, the problem of transition speed and output ringing can be solved simultaneously
quite well.
2.2 Load adaptability
Fig. 3 Embryo circuit of the proposed driving stage
aspect ratio (W/L), so the larger driving capability the
transistor has, the smaller its equivalent resistance is and
the noisier the output signal will be, where the mentioned
contradiction between transition speed and output ringing
also exists. Fortunately, the problem can be addressed by
the proposed structure, which will be illuminated by
depicting a charging transition as an example. Referring to
Fig. 4, both branches made of transistors P0–2 are switched
on and contribute together to boost transition speed at the
beginning of transition. As soon as the output voltage
increases and becomes close to the voltage level of VCC
jVTH P0 j; which means the VSG of transistor P0 is
approaching its switching threshold VTH_P0, the current
path through transistors P1 and P0 is gradually switched off
and the charging current decreases accordingly. When the
output voltage becomes higher than the value of VCC
jVTH P0 j; transistor P0 will be turned off and the output
Fig. 4 Changing of output equivalent resistance during a pull-up
transition
As can be seen in Fig. 5, the driving stage of the proposed
buffer adds delay unit based on the embryo structure shown
in Fig. 3. Due to the existence of the delay unit, stage II
will always engage in the transition later than stage I by a
certain time (Dt). Since the transition speed is determined
by the loading condition under a fixed driving capability,
the heavier the load is, the lower level the output voltage
reaches at the end of Dt, and thus the earlier stage II will
contribute to the transition response.
In order to explain this in a more intuitive way, a concrete situation is illustrated in Fig. 6. Consider a charging
process and assuming that the charging current of stage I
and stage II are I1 and I2, respectively, while the turning on
interval of the two stages is Dt as shown at the left side of
Fig. 6. Corresponding output waveforms when the capacitor is 10 and 30 pF, respectively, are shown at the right
side. As shown in Fig. 6, with a relative small load (e.g.,
10 pF) the output voltage rises rapidly, and has reached
quite a large value (e.g., 1.5 V of 1.8 V) when stage II
starts working (t2), thereby the charging transition is
mainly due to stage I (VCC - DV1) and the provided
Fig. 5 Block diagram of the proposed driving stage
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Analog Integr Circ Sig Process (2010) 65:273–282
Fig. 6 Illustration of load
adaptability
driving capability is comparatively small. On the other
hand, since the charging process is also due only to stage I
before stage II conducts when the loading capacitor shifts
to a heavier one (e.g., 30 pF), the transition speed will slow
down. Therefore, the output voltage is still at a low level
(e.g., 0.7 V) as stage II is switched on (t2), and the
transition is thus mainly due to both stages I and II
(VCC - DV2), which means that the total provided driving
capability is larger. That is to say, the proposed driving
stages can dynamically control the proportion of time
during the whole transition when both stage I and II work
together, i.e., the total provided driving capability, in
response to variation of the loading conditions, thus reduces unnecessary switching noise and output ringing.
Therefore, the load adaptability is achieved by a simple and
non-feedback mechanism.
2.3 Reducing switching noise
In this section, we analyze quantitatively the switching
noise, and illuminate the reason that why the proposed
buffer can achieve smaller switching noise compared with
the CSR (controlled slew rate) buffer [8] and the AC/DC
buffer [11] when their transition speeds are comparable.
As we know, the switching noise, also known as power
supply and ground bounces or di/dt noise, is a voltage
glitch induced at power/ground distribution connections
within a chip due to switching currents passing through
either wire/substrate inductance or package lead inductance associated with power or ground rails, and is
expressed as
dIðtÞ
Vn ¼ L
dt
ð4Þ
where I(t) = IT(t) ? IC(t), notice that both the through
current IT(t) and the charging/discharging current IC(t) may
induce switching noise [1, 13]. However, since all the CSR,
AC/DC and the proposed buffers adopt two branches for
123
the pull-up and pull-down switching, respectively, here the
switching noise due to the through current is negligible,
and is ignored in the following analysis. Besides, as
charging and discharging processes are similar, here we
only focus on the discharging process.
To analyze switching noise, the discharging circuit of
the conventional buffer in Fig. 1 can be reduced to a simple
circuit shown in Fig. 7. In Fig. 7, considering the input
rising ramp depicted as Vin = (VCC/tir) 9 t in Fig. 8(a),
where tir is the rising time of Vin from 0 to VCC. It is
usually the case that the last stage in the buffer drives a
higher capacitance load (CL is larger than several pF) than
the predriver in the output buffer. Therefore, it is true that
the discharging transistor N1 stays in its saturation region
throughout most of the low-to-high transition time tir of the
input signal Vin [1]. Furthermore, it can be well assumed
that when Vin reaches VCC, the discharging current IC
reaches its maximum value. This is because both VGS and
VDS are at their maximum value. Meanwhile, it can be
reasonably assumed that the current of the discharging
transistor N1 increases linearly from 0 to tir. Figure 8(b)
shows a sketch of the discharge current through N1. In
Fig. 8(b), after IC achieves its maximum value at the time
of tir, it begins to decrease because its drain-source voltage
Fig. 7 Simplified circuit of discharging process in the conventional
buffer
Analog Integr Circ Sig Process (2010) 65:273–282
277
R¼
kn
W L
1
ðVCC VTH Þ
n
ð7Þ
Meanwhile, the output voltage Vout in Fig. 9 is equal to
Vout ¼ Voutð0Þ et=RC
Fig. 8 a Sketch of input signal and b related discharging current
where Vout(0) = VCC. Assuming VOL = 0.1VCC, then the
output falling time is calculated by
tof 2RC ¼
VDS drops along with the discharging process, and thus N1
will enter its linear region soon.
The maximum discharging current which occurs at tir is
1
W
IMAX ¼ kn
ðVCC VTH Þ2 ð1 þ kVDS Þ
ð5Þ
2
L n
where k is the channel-length modulation coefficient, kn is
the device constant, W/L is the width to length ratio, and
VTH is threshold voltage. Since the derivative of IC with
respect to time, i.e., the switching noise, at tir is almost zero
as shown in Fig. 8(b), the maximum current in Eq. 5 does
not consider the switching noise at the source of N1.
Combining Eqs. 4 and 5, the maximum switching noise
can be approximately obtained by
dI
IMAX
L
dt tir
kn W ðVCC VTH Þ2 ð1 þ kVDS Þ
¼L L n
2tir
VnMAX ¼ L
ð6Þ
The other concern is the driving capability. As tir is usually
much smaller than the total output falling time, and the
switching noise is relatively small after N1 enters its linear
region, we can reduce the discharging circuit to that of
Fig. 9, where N1 is replaced by a linear resistor R. In
Fig. 9, the equivalent resistor during discharging can be
approximately calculated by
Fig. 9 Simplified
estimation
discharging
circuit
for
driving
capability
ð8Þ
kn
W L
2C
ð
V
VTH Þ
n CC
ð9Þ
From Eqs. 6 and 9, it is clear that there is a tradeoff
between the maximum switching noise and the driving
capability in the conventional buffer. In particular, the
larger the driving transistor is, the stronger the driving
capability and the smaller the output falling time will be.
However, the maximum switching noise increases as well.
Based on the analysis above, we then observe the
maximum switching noise and the driving capability of a
two stage CSR buffer so that the advantage of the proposed
buffer over the CSR and AC/DC buffer will become evident. For a two stage CSR buffer whose discharging circuit
is shown in Fig. 10, the calculation of switching noise and
the driving capability can be done similarly as those of the
conventional buffer, but this time the drain-source voltage
of transistor N2 is lower when its gate voltage Vin2 reaches
VCC. Here we assume stage II operates later than stage I by
a certain delay td.
Assuming Vout(tir) = VCC and equal threshold voltages
for N1 and N2, then the maximum discharging current for
the two stages are approximately given by
1
W
I1MAX ¼ kn
ðVCC VTH Þ2 ð1 þ kVDS1 Þ
ð10Þ
2
L n1
8
W 2
1
>
>
2 kn L n2 ðVCC VTH Þ ð1 þ kVDS2 Þ
>
>
< Vout ðtd þ tir Þ [ VCC VTH
i
I2MAX ¼
W h
Vout ðtd þtir Þ
>
>
k
ð
V
V
Þ
Vout ðtd þ tir Þ
n
CC
TH
>
L n2
2
>
:
Vout ðtd þ tir Þ\VCC VTH
ð11Þ
Fig. 10 a Simplified circuit of the discharging and b input signal for
the CSR buffer
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Analog Integr Circ Sig Process (2010) 65:273–282
Vout(td ? tir) is the output voltage when the gate voltage of
N2 reaches VCC. Equation 11 considers that at td ? tir N2
may stay at its saturation or has entered linear region
depending on the value of Vout(td ? tir). It should be noted
that when transistor N2 enters its linear region, i.e.,
VDS_N2 \ VCC - VTH, its drain-source voltage is quite
small and thus the channel modulation effect is negligible.
So it is reasonable to ignore the contribution of the channel
modulation effect when N2 enters its linear region in
Eq. 11.
Applying Eq. 10 to Eq. 6, the maximum switching noise
for stage I is
kn1 WL n1 ðVCC VTH Þ2 ð1 þ kVDS1 Þ
I1MAX
Vn1MAX L
¼L
tir
2tir
ð12Þ
Similarly, the maximum switching noise of stage II is
8
kn ðWL Þn2 ðVCC VTH Þ2 ð1þkVDS2 Þ
>
>
>L
2tir
>
I2MAX < Vout ðtd þ tir Þ [ VCC VTH
¼
Vn2MAX L
V
t þt
> kn ðWL Þn2 ðVCC VTH Þ out ð 2d ir Þ Vout ðtd þtir Þ
tir
>
>
L
>
tir
:
Vout ðtd þ tir Þ\VCC VTH
ð13Þ
In Eqs. 12 and 13, equal rising time is assumed for stages I
and II for simplicity. To be better understood, Fig. 11
draws sketch current of the conventional buffer and the two
stage CSR when their total transistor sizes are equal.
According to the analysis above, it is evident that the
maximum switching noise generated by the two stage CSR
buffer depends on the delay time td of stage II. If assuming
that the maximum switching noise for stage I and stage II
are the same.
Vn1MAX ¼ Vn2MAX
ð14Þ
Then the maximum switching noise for the two stage CSR
buffer is
Vn1MAX þ Vn2MAX ¼ 2Vn1MAX ðtd \tir Þ
VnMAX ¼
ð15Þ
Vn1MAX
ðtd [ tir Þ
Fig. 11 Sketch of discharging current for the conventional buffer and
the CSR buffer when their total transistor size are the same
123
Fig. 12 Simplified circuit of the discharging process for the CSR
buffer
Similarly, to calculate the driving capability, two linear
resistors can be used to replace transistors N1 and N2 in
Fig. 10(a) approximately, and then reduce the circuit to
Fig. 12. Thus, the output falling time for the two stage CSR
buffer can be obtained similarly
tof 2RC ¼
kn
W 2C
W L n1 þ L n2
ðVCC VTH Þ
ð16Þ
From Fig. 11, we should notice that, in order to minimize
the output falling time while keeping the lowest VnMAX, td
need to be equal to or only slightly larger than tir, which is
how we set the delay time td for the three buffers. It should
also be noted that the actual output falling time should be
slightly larger than the value calculated by Eq. 16 if considering the influence of td.
From Eqs. 15 and 16, we can conclude that a two stage
CSR may generate much smaller switching noise than that
of a conventional buffer while their total transistor sizes
and thus output falling time, i.e., driving capability, are
approximately the same. This is also evident from Fig. 11
which provides an illustration of the discharging current
for these two buffers with comparable driving capability.
On the other hand, since the definition of output falling
time usually considers only the required time for the
output drops from 90% of VCC to 10% of VCC, and
the AC/DC buffer uses a feedback to cut off one of the
driving stages at the end of transition (assuming the
second stage is cut off when the output drops to around
10% of VCC during discharging), the calculation of output
falling time in Eq. 16 also holds for the AC/DC buffer.
Furthermore, as the proposed buffer automatically turns
off stage I at the end of transition due to the diode-connected transistor N0 as shown in Fig. 13, the output
falling time for the proposed buffer can be calculated by
Eq. 16 as well if the threshold voltage of N0 is set to be
about 10% of VCC. Therefore, if the same transistor sizes
are applied to the three buffers as illustrated in Eq. 17,
they achieve comparable driving capability with the
assumption that the second stage of AC/DC buffer cut
off when Vout approaches 10% of VCC and the threshold
Analog Integr Circ Sig Process (2010) 65:273–282
voltage of N0 in the proposed buffer is around 10% of
VCC.
W
W
W
¼
¼
L n1 CSR
L n1 AC=DC
L n1 Pr oposed
ð17Þ
W
W
W
¼
¼
L n2 CSR
L n2 AC=DC
L n2 Pr oposed
According to Eq. 15, the maximum switching noise for the
three buffers depends on that of stage I if the interval time
td of the two stages is reasonably set. As shown in Fig. 13,
due to the diode-connected transistor N0 in stage I, the
drain-source voltage for transistor N1 is smaller than those
of the CSR and AC/DC buffers, so the maximum current of
the proposed buffer is the smallest among the three buffers
according to Eqs. 12 and 15. Therefore, the proposed
buffer can achieve the least maximum switching noise
while the driving capabilities of the three buffers are
comparable. Moreover, since the diode-connected transistors have a unidirectional characteristic, it decouples the
buffer output from the supply lines during switching of
the buffer in such a way as to prevent the noise present on
the supply lines from being transferred onto the output
node. That is to say, the adopted transistors lead to a
damping of oscillations present on supply lines to the
buffer output. Here the conclusion is deduced when the two
stages in the three buffers have the same transistor sizes for
simplicity. Actually, we recommend that the transistor size
for stage I is set to be smaller than that of stage II so that
the maximum switching noise which depends on stage I is
further reduced while the total driving capability is unaffected. Obviously the conclusion comes into existence as
well. Furthermore, to achieve threshold voltage around
10% of VCC (e.g., 0.18 V in the selected process), large
transistor should be applied to transistors N0, P0 in the
proposed buffer, which will increase area size. In our
design, transistor model with low threshold voltage and
minimum channel length are chosen for them so that the
proposed buffer can achieve the least switching noise with
reasonable additional area.
Fig. 13 Discharging circuit of the proposed buffer
279
3 High speed, low noise and load adaptive output
buffer
The proposed output buffer is shown in Fig. 14; it is
composed of stage I, stage II, a delay unit and pre-drivers.
As large transistors are employed in both stage I and stage
II, the short-circuit current is considerable, which is
undesirable because it does not have any contribution to
gate switching but its sharp current spike generates power
noise and consumes power. To avoid short circuit path
during transition and control switching time individually,
the pull-up and pull-down networks are separated. Thanks
to the introduced delay unit along with the diode-connected
transistors P0 and N0, stage I and stage II work in parallel
only during middle period of the transition responses. In
this manner, the proposed buffer achieves low switching
noise and reduced output ringing while at the same time
maintains adequate driving capability. Stage I, which
consists of PMOS transistors P0, P1 and NMOS transistors
N0, N1, operates ahead of stage II during transition. The
diode-connected transistors P0 and N0 in stage I act as
electronic components with unidirectional characteristics,
in this way, it prevents switching noise occurring on the
supply lines from being transferred onto the output voltage.
Moreover, by introducing the diode-connected transistors,
stage I turns off automatically near the end of output
transition; this effectively increases the equivalent output
resistance and hence reduces output ringing. Inverters
INV1–INV4 act as pre-driver for stage I while INV5–INV8
act as pre-driver for stage II. Sizes of the pre-drivers should
be carefully designed such that they can provide sufficient
rising or falling time to reduce switching noise, and the
turn-off operations should be faster than the turn-on operations to avoid short-circuit current, i.e., INV3, 4 switches
faster than INV1, 2 for input (IN) 0-to-1 transition, whilst
INV1, 2 is faster than INV3, 4 for input (IN) 1-to-0 transition. The delay unit, implementing with INV0, controls
the delay time of stage II. As a result, stage II is always
switched on, after a certain delay relative to Stage I, to
enhance transition speed and guarantee full output swing.
Fig. 14 Circuit of the proposed buffer
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280
Fig. 15 State transition diagram of operation for the proposed buffer
Figure 15 illustrates corresponding state transition diagram of the operation. The circuit operates essentially as
follow. Consider a low to high transition, where the input
signal IN transits from low to high. Since INV3, 4 switches
faster than INV1,2, N1 turns off before P1 conducts, then
P1 will follow its gate voltage at V1 and charge the output
load. Meanwhile, the output of logical gate NOR0 is set to
0, and N2 is turn off before P2 turns on in stage II.
Therefore, both the pull-down branches are shut down
before the pull-up networks operate so as to avoid large
short circuit current. After a fixed delay time, output of
logical gate NAND0 is set to 0, and transistor P2 in stage II
will turn on to enhance transition. Then both stages work in
parallel until the output voltage level reaches approximately VCC jVTH P0 j where VCC is the supply voltage
and VTH_P0 is the threshold voltage of P0. After that, since
P0 is cut off automatically, the output is driven by stage II
alone until full swing is reached.
4 Simulation results
To verify performance of the proposed buffer, comparison
simulations with the previous buffers including the CSR
buffer [8] and the AC/DC buffer [11] is performed with the
TSMC 90 nm/1.8 V technology. The parasitic inductance
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Analog Integr Circ Sig Process (2010) 65:273–282
and capacitance of the chip-package are modeled as
L = 3 nH and C = 1 pF, respectively. To carry out fair
comparison, the three buffers are designed to have the
same duty cycle and slew rate when CL = 30 pF and
f = 200 MHz. All transistors in the final driving stages are
set to an identical length L = 0.38 lm, except the diodeconnected transistors in the proposed design, whose length
need to be set to the minimum value, i.e., 0.1 lm. The total
transistor sizes of the driving stages, expressed as Wp/Wn
(lm/lm), for CSR, AC/DC and the proposed buffer are
1440/621, 1448/592, and 1590/672, respectively. The sizes
of driving transistors for the three buffers are comparable,
which has been well explained in Sect. 2.3. In addition, the
proposed design needs diode-connected transistors with
large W/L ratio, while the AC/DC buffer requires feedback
components, both of which will add additional area. In our
implementation, the Wp/Wn (lm/lm) for the diode-connected transistors in the proposed design, and for feedback
components in the AC/DC design, is 355/147 and 608/384,
respectively. Thus, to achieve the same driving capability,
the proposed buffer consumes larger area than that of the
CSR buffer, but has smaller size than that of the AC/DC
buffer. Since the proposed design can achieve better
switching noise and output ringing performances without
the additional complexity of feedback circuit design, the
reasonably increase in area is worthy.
Figure 16 illustrates waveforms for output voltage and
supply lines bounces at CL = 30 pF and f = 200 MHz. It
is illustrated that the proposed buffer has less ringing,
power supply and ground bounces than those of the CSR
buffer and the AC/DC buffer while the three buffers have
the same slew rate. Figure 17 draws a comparison among
the three buffers in terms of ground bounce, output ringing
and rise time over a load which ranges from 5 to 30 pF. To
make the comparison of performances more efficiently and
clearly, normalized results are shown. It should be noted
that the normalized ground bounce in Fig. 17(a) is obtained
using the maximum ground bounce among the three buffers as a basis of normalization while the normalized output
ringing in Fig. 17(b) is calculated using the maximum
output ringing among the three buffers as normalization
basis. It is clear from Fig. 17(a), (b) and (c) that the proposed buffer has the least ground bounce and output
ringing among the three buffers as it keeps comparable rise
time regardless of loading condition. In particular, the
proposed buffer improves ground bounce and output
ringing immunity by 4.1–53.5% and 2.9–15.2%, respectively, in comparison with those of the AC/DC buffer.
Besides, regarding the CSR design, it is 6.5–17.6% smaller
in ground bounce and 3.8–10.9% lower in output ringing.
Therefore, experiments are in good agreement with the
theoretical analysis that the proposed buffer can achieve
high speed and does have better performance in noise and
Analog Integr Circ Sig Process (2010) 65:273–282
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Fig. 16 Output voltage and supply bounces of the three buffers: a Output voltage, b Ground bounce, c Power supply bounce. Solid lines
simulation result of the proposed buffer. Dashed lines simulation result of the CSR buffer. Dotted lines simulation result of the AC/DC buffer
Fig. 17 Comparison of normalized output ringing, normalized
ground bounce and rise time against CL a Normalized ground
bounce vs. CL, b Normalized output ringing vs. CL, c Rise time vs.
CL. Solid lines simulation result of the proposed buffer. Dashed lines
simulation result of the CSR buffer. Dotted lines simulation result of
the AC/DC buffer
output ringing reduction under a wide range of loading
condition. Furthermore, unlike previous designs [3, 10, 11],
the proposed buffer adopts a non-feedback mechanism to
carry out load adaptability; its method is effective and
easier to implement.
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2.
3.
5 Conclusions
4.
A new CMOS output buffer has been proposed and designed.
It minimizes the inductive bounces occurring on supply lines
due to output switching while ensuring a high operation
speed. The key aspects are the novel combined structure of
two driving stages and the introduction of diode-connected
transistors in the first stage, which ensure that both driving
stages work parallel only during middle period of output
transition. Furthermore, the proposed method of load
adaptability is effective and easier to implement. Simulation
results confirm that the proposed buffer has both less ground
bounce and output ringing than those of the AC/DC and CSR
buffers under the same condition.
5.
6.
7.
8.
9.
Acknowledgments This work was supported by Wuhan Research
Center for Integrated Circuit Design. The authors wish to thank all the
people who gave precious support for the project, and special thanks
go to professor Zheng-lin Liu.
10.
11.
References
1. Vaidyanath, A. (1994). Effect of CMOS driver loading conditions
on simultaneous switching noise. IEEE Transactions on
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548.
Yingyan Lin received the B.S.
and M.S. degrees in electronic
engineering from Huazhong
University of Science & Technology (HUST) in 2004 and
2007, respectively. Since 2007,
she has been pursuing Ph.D.
degree in Department of Electronic Science and Technology
(EST), HUST, Wuhan, China.
Currently, she is studying as a
visiting student in Department
of Electrical and Computer
Engineering, the University of
Illinois at Urbana-Champaign
(UIUC), IL, USA. Her research includes design of output buffer,
transmitter, and ADC for high speed links. Ms. Lin was the recipient
of Excellent Graduate Award from HUST in 2004, First Prize Master
Dissertation from HUST in 2006, Excellent Academic Award from
HUST in 2007, and Government-sponsored Overseas Study Scholarship from China Scholarship Council in 2009.
Jing Zhang received the B.S.
and M.S. degrees in electronic
engineering from Huazhong
University of Science & Technology (HUST) in 2004 and
2007, respectively. From Jan.
2007 to Jun. 2009, he worked as
an IC engineer in INNOSILICON CO., LTD, Wuhan,
China. Currently, he is pursuing
Ph.D. degree in Electrical
Engineering Department, the
University of Texas at Dallas,
TX, USA. His research interests
include RF transmitter design
and high-speed I/O circuit design. Mr. Zhang was the recipient of
First Prize Scholarship from HUST in 2005-2007, Excellent Personnel Award from Wuhan Reserch Center for IC Design in 2006, and
Merit Graduate Student Award from HUST in 2007.
Xuecheng Zou received the
B.S., M.S., and Ph.D. degrees,
all in electrical engineering,
from Huazhong University of
Science
and
Technology
(HUST), Wuhan, China in 1985,
1988 and 1995, respectively. In
1988, he joined the Department
of Electronic Science & Technology (EST) at HUST as an
assistant professor and then
promoted to associate professor
in 1993, and he is currently a
Professor and the Chair of the
EST Department. From 1996
through 1998, he was a Research Scientist affiliated with the
123
Analog Integr Circ Sig Process (2010) 65:273–282
Department of Electronic Engineering at City University of Hong
Kong. His research interests span microelectronics and solid state
electronics, design of integrated circuits and systems for broadband
communications including low-power/high-performance VLSI
architectures as well as digital integrated circuit design. He has
authored or coauthored over 200 technical papers in this area and
holds ten Chinese patents. He is also the coauthor of a widely used
college textbook, VLSI Design Methods and Project Implement
(China Science Press, 2007, ISBN: 703019451). Besides, he has held
several administrative posts, including Director of the VLSI Integrated Circuits and System Research Center, a Member of the University Academic Committee as well as University Academic Degree
Committee at HUST, Director of the National Research Center for
Integrated Circuit Design.Wuhan, Director of National Training Base
for Integrated Circuit Design. Wuhan, a Committee Member of
Chinese Institute of Electronics. Prof. Zou has won various awards/
honors including two Provincial Level Scientific Achievement
Awards, HUST Excellent Mentor (2002), HUST Best Teacher Award
(2006), a First Prize of Provincial Excellent Courses (2008), etc.
Dongsheng Liu was born in
Anhui, China, in 1978. He
received the Ph.D. degree from
Huazhong University of Science
and Technology, Wuhan, China,
in 2007, for his thesis on passive
HF RFID tag IC. Since 2007, he
has been an Assistant Professor
at the Department of Electronic
Science & Technology in
Huazhong University of Science
and Technology. He holds four
Chinese patents, has authored or
co-authored over 20 technical
papers. His main research
interests are VLSI design, RFID Tag IC, high reliability microprocessors and high performance microprocessor.
Shuang-yang Wang received
the B.S. and M.S. degrees in
Microelectronics and Solid
State Electronics from Huazhong University of Science and
technology in 2006 and 2008,
respectively. He is working for
Actions semiconductor CO.,
LTD as an Analog design engineer. His current interests are
mixed-signal IC design with
CDR and transceivers in High
speed interface.