Verilog: Gate Level Design
1
BASED ON THE TUTORIAL ON THE BOOK CD
7/29/2017
Verilog
2
 Each Verilog model is of a particular "level." The





level of a model depends on statements and
constructs it contains. The levels of Verilog models
are:
Behavioral
Register Transfer (RT)
Gate, and
Switch
Chapter 4 : Gate level
7/29/2017
Objectives
3
 predict the output of a gate level Verilog model given
its inputs
 describe how to correct a gate level Verilog model
given its source code, inputs and output
 write a Verilog gate-level model corresponding to a
given simple schematic
 determine the schematic for a gate level Verilog
model given its source code
7/29/2017
NetList
4
module DEC1OF8 (X0B, X1B, X2B, X3B, X4B, X5B, X6B, X7B, SL0, SL1, SL2, ENB);
output X0B, X1B, X2B, X3B, X4B, X5B, X6B, X7B;
input SL0, SL1, SL2, // select signals
ENB; // enable (low active)
//Module Description
not
// invert SL0-SL2,
N1 (sl0b, SL0), // & ENB
N2 (sl1b, SL1),
N3 (sl2b, SL2),
N4 (enbb, ENB);
nand
// select outputs
NA1 (X0B, sl2b, sl1b, sl0b, enbb), // (low active)
NA2 (X1B, sl2b, sl1b, SL0, enbb),
NA3 (X2B, sl2b, SL1, sl0b, enbb),
NA4 (X3B, sl2b, SL1, SL0, enbb),
NA5 (X4B, SL2, sl1b, sl0b, enbb),
NA6 (X5B, SL2, sl1b, SL0, enbb),
NA7 (X6B, SL2, SL1, sl0b, enbb),
NA8 (X7B, SL2, SL1, SL0, enbb);
endmodule
7/29/2017
Module embedding
5
module vabc (d, s);
input [1:0] s;
output [3:0] d;
not (s1_, s[1]), (s0_, s[0]);
and (d[3], s1_, s0_);
and (d[2], s1_, s[0]);
and (d[1], s[1], s0_);
and (d[0], s[1], s[0]);
endmodule
module abc (a, b, c, d, s1, s0);
input s1, s0;
output a, b, c,d;
not (s1_, s1), (s0_, s0);
and (a, s1_, s0_);
and (b, s1_, s0);
and (c, s1, s0_);
and (d, s1, s0);
endmodule
7/29/2017
Module abc in vabc
6
module vabc (d, s);
input [1:0] s;
output [3:0] d; abc a1 (d[3], d[2], d[1], d[0], s[1],
s[0]);
endmodule
7/29/2017
Module Definition + Gate Level Diagram
7
module abc (a, b, c, d, s1, s0);
input s1, s0;
output a, b, c,d;
not (s1_, s1), (s0_, s0);
and (a, s1_, s0_);
and (b, s1_, s0);
and (c, s1, s0_);
and (d, s1, s0);
endmodule
7/29/2017
4-bit Adder : Lets write Verilog Source
8
7/29/2017