Design of a CMOS System-on-Chip for Passive,
Near-Field Ultrasonic Energy Harvesting and BackTelemetry
Abstract:
Many packaging and structural materials are made of conductive materials such as metal or
carbon-fiber composites, which limits the use of embedded radio frequency-based telemetry
systems for sensing. In this paper, we present the design of a complete passive ultrasonic energy
harvesting and back-telemetry system that exploits near-field acoustic coupling to wirelessly
transfer energy and data across conductive barriers. The use of near-field operation makes the
telemetry robust to multipath reflections that occur at barrier discontinuities and robust to
crosstalk when multiple sensors are simultaneously interrogated. Underlying the proposed
architecture is a systemon-chip (SoC) that integrates different ultrasonic energy harvesting and
telemetry modules. The operation of the system has been verified using SoC prototypes
fabricated in a 0.5-µm CMOS process which have been integrated with a piezoelectric transducer
attached to an aerospace-grade aluminum substrate. Measured results show that the proposed
near-field ultrasonic telemetry system can effectively operate across a 2-mm-thick metallic
barrier at a frequency of 13.56 MHz with the SoC consuming 22.3 µW of power. The proposed
architecture of this paper the area and power consumption are analysis using tanner tools.
Enhancement of the project:
Chance the parameter and technology
Existing System:
An alternative to RF-based telemetry is acoustic- or ultrasonic-based telemetry, which has been
demonstrated to exhibit low attenuation inside conductive media. The use of ultrasound allows
miniaturization of the embedded telemetry system by relaxing the size requirements on the
piezoelectric transducer (PZT). In addition, unlike RF transmission, which is regulated according
to FCC requirements, ultrasonic power delivery and transmission, is only limited by the
structure’s mechanical compliance. In literature, several ultrasonic telemetry systems have been
reported for use in metallic structures and for in vivo applications. Passive ultrasonic telemetry
systems have also been reported that eliminate the need for batteries on the sensors. However, all
these systems are either bulky or power hungry, and thus are not suitable for massive deployment
in practical applications.
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Disadvantages:

Area coverage and Power consumption is high
Proposed System:
The system architecture of a ultrasonic back-telemetry system is shown in Fig. 1. The reader
comprises the digital controller, the analog front-end (AFE) and the impedance matching circuit.
The digital controller implements a state machine that sends and receives commands to and from
the tag. The AFE modulates the digital signal with ultrasonic carrier and demodulates the
backscatter signal. The impedance matching circuit is used to create a resonant network
comprising the transmit PZT, the transmission medium and the receive tag.
Fig. 1. Proposed ultrasonic communication system.
The receiver tag consists of a receive PZT and a matching circuit which forms a part of the
ultrasonic resonant network. Through this network, the tag receives electrical power and a power
management module comprising of voltage multipliers and voltage regulators generate stable
supply voltages for other on-chip modules. A demodulator extracts the raw data received over
the resonant network and a digital state-machine performs error-correction and decodes the
commands received from the reader.
Power Management Circuits
Due to the attenuation of the ultrasonic signal inside the solid medium and the transducer’s
limited energy conversion efficiency as well as the impedance mismatch at various interface, the
magnitude of the signal induced at the receive PZT is typically capacitor. For this
implementation we have used a standard Dickson type multiplier, as shown in Fig. 2. The
multiplier comprises of Schottky junction diodes (with approximate threshold voltage of Vth ≈
300 mV) and produces an output voltage VOUT ≈ N · (VIN − Vth), with N being the number of
multiplier stages.
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Fig. 2. Power management modules, which include a voltage multiplier, a voltage limiter, and a regulator
Data Recovery Circuit
The data recovery circuit is shown in Fig. 3(a) and demodulates a pulse-interval encoded (PIE)
modulation signal. In a PIE code, a long duration between two digital pulses represents logic 1,
and a short duration between two pulses represents logic 0. The envelope of the modulated
piezoelectric signal is first extracted by a voltage doubler followed by a low-pass filter. A
comparator then compares the filtered signal with V2, which is the midpoint of the supply
voltage. Since the dc component of the V1 equals V2, the comparator extracts the PIE signal.
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Fig. 3. (a) Block diagram. (b) Detailed circuit design of data recovery circuit.
Digital Baseband and Manchester Encoder
The digital baseband module includes the preamble circuit, the ADC controller, and the
Manchester encoder. The PIE data transmitted from the reader to the tag are encapsulated in a
frame consisting 4-bit preamble bits, 3-bit command bits, and a 1-bit CRC code, as shown in Fig.
4(a).
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Fig. 4. Communication protocol. (a) PIE. (b) Manchester.
Sensor Data Acquisition Circuitry
A POR detects the change in the supply voltage and generates a delayed digital pulse, which is
used to initialize all the digital logic and internal registers. The delay time td is determined by the
charging current Ich and capacitor size Cc
td = (CcVth)/ Ich
(1)
where Vth is the threshold of the inverter. In addition, the current-starved inverters have been
used to minimize the power dissipation.
Advantages:

Area and power is reduced
Software implementation:

Tanner tools
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com