Looking Under
the Hood
© 2003 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
• Understand what is happening behind the scenes and how your
decisions can impact the quality of the result
• Use good design habits to achieve the best solution
Looking Under the Hood - 5 - 3
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Quantization and Overflow
• The Costs of Hardware
of System Abstraction
• Bit Picking
• Tips for Good Designs
Using System Generator
Looking Under the Hood - 5 - 4
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Quantization and Overflow
Looking Under the Hood - 5 - 5
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Quantization
• Occurs if the number of fractional bits is insufficient to represent the
fractional portion of a value
• Users can choose to:
– Truncate - Discard bits to the right of the least significant bit
– Round - Round to the nearest representable value or to the value farthest
from zero if there are two equidistant nearest representable values
Full Precision
1
0
1
1
0
1
1
1
1
0
1
0
FIX_12_9
1
0
1
1
0
1
1
1
1
0
1
0
-Truncate -2.26171875
FIX_12_9
1
0
1
1
0
1
1
1
1
0
1
0
- Round
Looking Under the Hood - 5 - 6
© 2003 Xilinx, Inc. All Rights Reserved
1
0
0
0
0
-2.26171875
For Academic Use Only
Quantization
• A signed full precision number will have a different output depending on
whether truncation or rounding is employed
Full Precision
0
0
1
1
0
1
1
1
1
0
1
0
1
0
0
0
0
1.7392578125
FIX_12_9
0
0
1
1
0
1
1
1
1
0
1
0
-Truncate
1.73828125
FIX_12_9
0
0
1
1
0
1
1
1
1
0
1
1
- Round
1.740234375
Looking Under the Hood - 5 - 7
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Quantization
• An unsigned full precision number will have a different output depending
on whether truncation or rounding is employed
Full Precision
1
0
1
1
0
1
1
1
1
0
1
0
1
0
0
0
0
5.7392578125
UFIX_12_9
1
0
1
1
0
1
1
1
1
0
1
0
-Truncate
5.73828125
UFIX_12_9
1
0
1
1
0
1
1
1
1
0
1
1
- Round
5.740234375
Looking Under the Hood - 5 - 8
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Overflow
• Occurs if a value lies outside the representable range
• Users can choose to:
– Saturate to the largest positive (or maximum negative) value
– Wrap the value (i.e., discard any significant bits beyond the most significant
bit in the fixed point number)
– Flag an overflow as a Simulink error during simulation
1
0
1
1
0
1
1
Full Precision output
- Saturate (3.9375)
0
1
1
1
1
1
1
FIX_7_4
- Wrap (-2.3125)
1
0
1
1
0
1
1
FIX_7_4
(13.6875)
Looking Under the Hood - 5 - 9
0
1
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Quantization and Overflow
• Whatever option is selected, the generated HDL model and Simulink
model will behave identically
• This also means rounding and saturation will use FPGA resources
Looking Under the Hood - 5 - 10
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Quantization and Overflow
• The Costs of Hardware
of System Abstraction
• Bit Picking
• Tips for Good Designs
Using System Generator
Looking Under the Hood - 5 - 11
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
IP Wrappers
Every IP core has a wrapper to interface between Simulink and hardware
• Each SysGen block has an RTL
VHDL wrapper to
– Extend IP core functionality
– Simplify IP core interface
• Support fixed-point arithmetic
– Number of bits, binary point
– Overflow and quantization
– Valid bit control on some cores
xlMult.vhd
COREGen
IP Core
(xmult_x_0_core.vhd)
• Note: a Simulink parameter may not be identical
to the corresponding COREGen parameter
• Wrapper file will have xl<core-name> in its
filename without core keyword
Looking Under the Hood - 5 - 12
© 2003 Xilinx, Inc. All Rights Reserved
MultGen
v6.0
SysGen VHDL
IP Core Wrapper
(xmult_x_0.vhd)
For Academic Use Only
Implications of IP Wrappers
System level abstraction is very expressive and powerful, but
comes at some expense in hardware. Be aware!
•
•
•
Saturation arithmetic and rounding requires hardware (full adder)
Excess latency is implemented with a shift register (SRL16) on the core output
Some SysGen blocks perform implicit conversion of inputs
–
–
–
–
•
Unsigned to signed
Sign extension
Zero padding
SysGen mask parameters may not be identical to COREGen parameters
Valid bit pipeline parallels to the data path, typically implemented using SRL16
Looking Under the Hood - 5 - 13
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Lab 6
Looking Under the Hood
You are given a simple design of adder circuit:
• Make changes to a System Generator model to see what the results
would be in hardware by changing saturation arithmetic and rounding
• Use the Resource Estimator block to estimate the resources usage in
each case
• Use an RTL viewer to see the changes, and
• Use the Xilinx implementation results to determine the cost of these
system-level decisions
Looking Under the Hood - 5 - 14
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Quantization and Overflow
• The Costs of Hardware
of System Abstraction
• Bit Picking
• Tips for Good Designs Using
System Generator
Looking Under the Hood - 5 - 15
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Picking Bits: Why We Do It
• To combine two data buses together to form a new bus
• To force a conversion of data type including the number of bits and
binary bits
• To reinterpret unsigned data as signed, or the converse
• To extract certain bits of data, especially when there is bit growth
Looking Under the Hood - 5 - 16
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Xilinx Blocks
•
•
Concat
– Available in basic elements, data
types, math, and index libraries
– Available in basic elements, data
types, and index libraries
•
•
Reinterpret
– Available in basic elements, math,
and index libraries
Looking Under the Hood - 5 - 17
Convert
Slice
– Available in basic elements, control
logic, data types, and index libraries
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Concat Block
• Performs a concatenation of two bit vectors
• Both inputs must be unsigned integers
– i.e., two unsigned numbers with binary points at position zero
• Reinterpret block provides signed to unsigned conversion
capabilities that can extend the functionality of the concat block
• Does not use Xilinx LogiCORE and hardware resources
Looking Under the Hood - 5 - 18
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Convert Block
• The Xilinx convert block converts each input sample to a
number of a desired arithmetic type
– A number can be converted to a signed (twos complement)
or unsigned value
– Total number of bits and binary point are specified by the user
– Rounding and quantization options apply to the output value
– Does not use Xilinx LogiCORE but may use additional hardware depending
on the overflow and quantization options
Looking Under the Hood - 5 - 19
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Convert Block
• What is it doing?
– User specifies the total number of bits, where the binary
point is, and the arithmetic type (signed or unsigned)
– First it lines up the binary point between input and output
port types
– Next, the total number of bits and binary point the user specifies
are used, and depending if overflow and quantization options
are used the output may change, as opposed to dropping bits
Looking Under the Hood - 5 - 20
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Convert Block
• The following through the convert block would result
in the same value using a different number of bits and
binary point
FIX_10_8
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
FIX_7_4
Looking Under the Hood - 5 - 21
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Convert Block
• Saturating the overflow may change the fractional number
to get the saturated value
• Rounding the quantization may also affect the value to the
left of the binary point (the whole number)
Looking Under the Hood - 5 - 22
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Convert Block
• When we convert to a Fix_6_0, how do we get
two different values?
OVERFLOW
- Wrap
- Saturate
- Flag Error
QUANTIZATION
0
1
1
0
0
0
0
0
0
- Truncate
- Round
FIX_10_8
0 0
0
0
1
0
Round to decimal +2
Add ‘1’ to round
0
1
Truncate to decimal +1
Drop the bits
FIX_6_0
0 0
0
0
FIX_6_0
Looking Under the Hood - 5 - 23
0
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Reinterpret Block
• Forces its output to a new type without any regard for
retaining the numerical value represented by the input
• Total number of bits in = total number of bits out
• Allows for unsigned data to be reinterpreted as signed
data, and the converse
• Also allows scaling of the data through the repositioning
of the binary point
• Does not use Xilinx LogiCORE and hardware resources
Looking Under the Hood - 5 - 24
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Reinterpret Block
• Reinterpret the UFIX_10_8 number and force the
binary point to position 5
0
1
1
0
0
0
0
0
0
0
+1.5
0
0
0
0
+12
FIX_10_8
0
1
1
0
0
0
FIX_10_5
Looking Under the Hood - 5 - 25
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Slice Block
• The Xilinx slice block allows you to slice off a sequence
of bits from your input data and create a new data value
• The output data type is unsigned with its binary point
at zero
Looking Under the Hood - 5 - 26
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
The Slice Block
• Take a slice of the FIX_10_8 number by taking a 4-bit slice
and offsetting the bottom bit of the slice by 5 bits
0
1
1
0
0
0
0
0
0
0
+1.5
12
• Upper Bit Location + Width: Offset of top bit from MSB = 0 and width = 4
0
1
1
0
6
• Two Bit Locations: Offset of top bit from MSB of Input = -1 and Offset of
Bottom bit from LSB of Input = 5
12
Looking Under the Hood - 5 - 27
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
What Values Do You Expect?
Signed Data
Truncate and Wrap
Signed Data
Output Binary Point of 3
Total Number of Bits 3
Bottom Slice offset by 5
from the LSB
Looking Under the Hood - 5 - 28
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
Outline
• Quantization and Overflow
• The Costs of Hardware
of System Abstraction
• Bit Picking
• Tips for Good Designs
Using System Generator
Looking Under the Hood - 5 - 29
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only
SysGen Design Tips
• Remember that saturation arithmetic and rounding have area and
performance costs. Use only as necessary
• Register inputs and outputs, and register (rather than ignore) invalid data
when possible
Looking Under the Hood - 5 - 30
© 2003 Xilinx, Inc. All Rights Reserved
For Academic Use Only