VCs used by the CP (on Port 7)
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Port CP: 32  Switch control cells
Port CP: 40+N  N/40 (IP Data from 0 to N) (FPX also may touch)
Port CP: 61  */61 (DQ broadcast) (FPX also may touch)
– SPC0 has to have special treatment of VCI=61 so it can send a copy back to the
CP for monitoring on VC = 60
Port CP: 68+N  N/0x321 (SPC CTRL cells)
Port CP: 76+N  N/34 (FPX NID CTRL)
Port CP: 84+N  N/62 (MSR Command Protocol)
Port CP: 92+N  N/63 (IP pkts from CP)
N = {0, 1, ..., 7}
Port CP: 100+N  N/35 (FPX RAD CTRL)
Port CP: 108+N  N/36 (Second FPX NID)
Port CP: 116+N  N/37 (Second FPX RAD)
Port CP: 124+N  N/64 Debug Messages
Port CP: 132+N  N/65 (NMVC Probe SPC)?
Port CP: 150-199 Inclusive, used for signaling (UNI/PNNI)
Adding Port CP: 140 through 163 for control and downloading, see page 3
SPC/PE Control
September 20, 2000
FPX Control
MSR Design
IP Data flows
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1
VCs used by SPC ports: N = 0-7
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Port N: 33  CP/68+N (CTRL resp back to CP)
Port N: 34  CP/76+N (NID CTRL resp back to CP)
Port N: 35  CP/100+N (RAD CTRL resp back to CP)
Port N: 36  CP/108+N (Second NID CTRL resp back to CP)
Port N: 37  CP/116+N (Second RAD CTRL resp back to CP)
Port N: 40  0/40+N (IP Data to Port 0) (FPX also may touch)
…
Port N: 47  7/40+N (IP Data to Port 7) (FPX also may touch)
Port N: 50  Previous/Next Hop (SPC or FPX)
Port N: 51  Previous/Next with FPX (FPX rx/send on 50)
Port N: 52-59 Reserved for data path
Port N: 61  */61 (DQ Broadcast) (FPX also may touch)
Port N: 62  CP/84+N (MSR Command Protocol)
Port N: 63  CP/92+N (IP to CP)
Port N: 64  CP/124+N, Debug Messages
Port N: 65  CP/132+N
Adding Port N: 66 control and downloading, see page 3
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
2
Additions - Download Kernel
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Port CP: 140 + (3 * N)  N/0x321 - SPC Control Cells
Port CP: 141 + (3 * N)  N/33 - SPC (control) Reply Cells
Port CP: 142 + (3 * N)  N/66 - SPC AAL5 data transfer VC
Port N: 33  CP/141 + (3 * N)
Port N: 66  CP/142 + (3 * N)
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
3
VCs used by CP (Connected to Port 0)
60
...
68
...
83
...
84
91
92
...
CP
99
...
100
107
...
108
115
116
...
NMVC VCs not shown
75
76
September 20, 2000
}
}
}
DQ Monitoring Channel
}
IP Table Management
Channels for SPCs 0-7
}
IP Packet Channels
between CP and SPCs 0-7
}
RAD Control Channels
for FPXs 0-7
}
NID Control Channels
for Second FPX 0-7
}
RAD Control Channels
for Second FPXs 0-7
Washington
123
MSR Design
Control Channels for SPCs 0-7
NID Control Channels
for FPXs 0-7
WASHINGTON UNIVERSITY IN ST LOUIS
4
50
40
(0, 40+n)
...
SPC Data Connections
(7, 40+n)
47
to Output ports
IPPn
Next/
Previous
Hop
Router
Switch
Fabric
SPCn
50
40
From port 0
...
from Input ports OPPn
From port 7
47
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
5
(0, 40+n)
(7, 40+n)
47
140
(0, 140+n)
...
Pacing
51
FIPL
50
40
...
Pacing
IP Active
SPC/FPX Data Connections (Split IP and DQ Functions)
(7, 140+n)
147
IPPn
140
From port 0
From port 7
147
40
...
50
Switch
OPPn Fabric
FPXn
DQ &
SAR
SPCn
...
Next
Router
From port 0
From port 7
47
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
6
SPC/FPX Data Connections (FPX does all IP and DQ functions)
IPPn
51
Next
Router
Active
SPCn
47
40
...
...
40
Pacing
50
FIPL
50
(port, VCI)
(0, 40+n)
(7, 40+n)
47
51
51
Switch
Fabric
FPXn
40
From port 0
...
50
DQ &
SAR
OPPn
From port 7
47
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
7
SPC/FPX Data Connections:
FPX does all IP and DQ functions, Active Processing on Ingress SPC only.
51
IPPn
51
47
40
...
...
40
Pacing
50
FIPL
APIC
Cut-through
Active
50
(input=50, <nexthop>, A=0)
(input=51, <nexthop>, A=*)
(port, VCI)
(0, 40+n)
(7, 40+n)
47
(input=50, <nexthop>, A=1)
51
Next
Router
SPCn
Switch
Fabric
FPXn
APIC
Cut-through
40
From port 0
...
50
DQ &
SAR
OPPn
From port 7
47
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
8
SPC/FPX Data Connections:
FPX does all IP and DQ functions, Active Processing on Ingress SPC only.
50
FIPL
SAR
51
Active
SAR
X
51
SAR
<nexthop>,
input=50|51,
active=0|1
SAR
51
Shouldn’t A =
(input=50, <nexthop>, A=1)
0?
FPXn
SPCn
September 20, 2000
40
MSR Design
47
(input=50, <nexthop>, A=0)
(input=51, <nexthop>, A=*)
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9
Pacing
APIC
Cut-through
...
50
SPC/FPX Data Connections (FPX does all IP and DQ functions)
Why are these Output VCs going to both SPC and FPX?
IPPn (port, VCI)
51
Next
Router
Active
SPCn
47
40
(0, 40+n)
...
...
40
Pacing
50
FIPL
50
(7, 40+n)
47
51
51
Switch
Fabric
FPXn
OPPn
1/47
0/40
...
50
DQ &
SAR
...
1/40
From port 0
From port 7
From port 0
From port 7
0/47
September 20, 2000
MSR Design
Washington
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10
SPC DQ Connections
61
60
61
OPP0
60
IPP1
RC=7
61
SPC1
0-7,61
OPP1
61
...
0,60
61
SPCn
1,60
IPPn
RC=3 (2 copies)
OPPn
61
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
Range Copy Ports 0-7, VCI = 61
SPC0
CP
IPP0
11
CP to SPCn and FPXn Control Connections
FPX0
IPP 0
SPC0
CP
68+n
76+n
84+n
92+n
100+n
108+n
116+n
OPP 0
Left out NMVC VCs
124+n->64, 132+n->65
FPX1/2
IPP n
SPCn
IP Local
IP Control
SPC Control
#2 RAD
#2 NID
#1 RAD
#1 NID
September 20, 2000
37
36
35
63
62
34
0x321
MSR Design
OPP n
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notes
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MSR initialization
packets in/out
bytes in/out
drops
configuration params: link speed
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
13
Replace Jammer: Initial VC config
• ditch Jammer, use new GBNSC to initialize
all connections
• MSR configuration code does all of this.
• jdd: discovery and download
• jp: WUGS configuration, hardcode
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
14
Sequence of Operations
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Reset
Setup Connections
Discovery
Download Kernels
Init Kernels
September 20, 2000
MSR Design
Washington
WASHINGTON UNIVERSITY IN ST LOUIS
15