E. T. TELECOMUNICACIONS
1BM2
26/05/2008
DIGITAL ELECTRONICS
Prof. F. J. Sànchez i Robert
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Fifth minimum control: 45 min. Grades will be available on June 05th
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Questions about the examination: TH:17 h – 19 h; FR: 10 h-14h
VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results always explaining what are you
doing
Minimum 6: Canonical FSM
We pretend to design a control unit (CU) that can be able to manage the operational unit (OU) for performing 14-bit
unsigned multiplications based on the shift-and-add algorithm. Fig. 1 represents the multiplier block to be designed.
The OU or datapath architecture has been discussed in class and mainly is based on the use of shift registers and a
14-bit binary adder. A down counter will determine when the 14-bit operation is over.
Fig. 1 Synchronous sequential multiplier to be designed
Fig. 2 Block diagram for the FSM that will control the operational unit resources
a) Invent the Fig. 1 symbol for the sequential multiplier. Signals SO (start operation) and EO (end operation) will
dialogue with a microprocessor unit. Invent the CU-OU architecture in Fig. 2. Propose a state diagram and
explain all the state transitions and outputs. Make a couple of numerical examples to show that your state
diagram is capable of performing correctly the multiplication operation
b) Draw the internal architecture of the synchronous canonical FSM
c) Code states in binary
d) Design the CS2 to determine every output
e) Draw the state register if D-type FF have to be used
f)
Implement the CS1using the state transition table and the D-type FF design table
g) Verify your project using Proteus. Consequently, after 15-17 clock cycles, multiplication result must appear in
vector C[13..0].