DIGITAL 2 : EKT 221
RTL : Microoperations on a
Single Register
Today’s Outline
Multiplexer-based transfers
 Transforming Block Diagram to Detailed Logic
 Shift Registers
◦ Shift Registers with Parallel Loads
◦ Shift Registers with Parallel Loads and Hold

MULTIPLEXER-BASED
TRANSFER
Microoperations on a Single
Register

Implement one or more microoperations with a
single register as the destination of all primary
results.

The single register may also serve as a source of
an operand for binary and unary operations.

A simple technique using multiplexers for
selection is introduced to allow multiple
microoperations on a single register
Multiplexer-Based Transfers
A register receives data
transfers from more than 1
sources.
 A dedicated multiplexer
is used to select the
wanted input
 Example shows:
◦ If K1=1, R0 receives data
from R1.
◦ If K1=0, R0 receives data
from R2.

K2
K1
n=4
R2
S
0
1
n=4
2:1 MUX
R1
n=4
R0
Multiplexer-Based Transfers
How do we represent this in RTL form?
 Written in if-then-else:
K2
If (K1=1) then (R0 R1),
K1
else if (K2=1) then (R0 R2).
n=4
R2
 Written in RTL:

K1:R0
R1, K1K2:R0
S
0
1
R2
n=4
R0
2:1 MUX
R1
n=4
1. Hardware connections from two source registers, R1 and R2, to one common
destination register, R0.
2. Selection between R1 and R2 must be based on the control variables K1 and K2.
Multiplexer-Based Transfers
Analyse the diagram for input:
K2
K1:R0
R1, K1K2:R0
R2
K1
n=4
K1
K2
Load
0
0
0
1
0
1
1
1
0
1
*n.c : no change
1
1
R0
R2
S
content
n.c
R2
R1
R1
0
1
n=4
2:1 MUX
R1
n=4
R0
Transforming a Block
Diagram into Detailed
Logic
K2
K1
n=4
R2
Load
S
0
1
n=4
K2
K1
R0
2:1 MUX
R1
Load
n=4
2 to 1 MUX
S
R2
Block Diagram
D0
D1
D2
D3
Q0
Q1
Q2
Q3
CLK
A0
A1
A2
A3
B0
B1
B2
B3
Load
R0
Y0
Y1
Y2
Y3
R1
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Load
Detailed Logic
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SHIFT REGISTERS
Shift Registers
Shift Registers move data laterally within the
register toward its MSB or LSB position
 In the simplest case, the shift register is simply a
set of D flip-flops connected in a row like this:

*CP: a common clock pulse input that activates the shift
Shift Registers
Parallel Output
Serial Input
Serial Output
Data input, In, is called a serial input or the shift right
input.
 Data output, Out, is often called the serial output.
 The vector (A, B, C, Out) is called the parallel output.

Shift Registers




T0 is the register state just
before the first clock pulse
occurs
T1 is after the first pulse and
before the second.
Initially unknown states are
denoted by “?”
Complete the last three
rows of the table
CP
In
A
B
C
Out
T0
0
?
?
?
?
T1
T2
1
1
0
1
?
0
?
?
?
?
T3
1
0
1
1
0
1
?
T4
0
1
T5
1
1
0
1
T6
1
Shift Registers with Parallel Load
 The
shift register shown earlier has no
control input, thus data is always shifted
on clock pulse.
 How
to make the shift registers more
controllable?
E.g. shifts only on select positive clock edges.
Shift operation can be controlled through D
inputs of the FFs, rather than through the
clock inputs CP.
Shift Registers with Parallel Load

By adding a mux between each shift register stage,
data can be shifted or loaded
2 to 1 MUX
Serial Input
1
0
Dn
A0
IN
A1
0
1
Selector
SHIFT

If SHIFT is LOW, A and B are replaced by the data
on DA and DB lines, else data shifts right on each
clock.
Shift Registers with Parallel Loads and
Hold


But what if we want
to hold to the
current data,
meaning no shift or
no loading of new
data?
The design must
have 2 controls:
1. For the SHIFT
2. For the LOAD
Function Table for the Register of Fig 7-10
SHIFT
LOAD
OPERATION
0
0
No Change
0
1
Load Parallel
Data
1
X
Shift down from
Q0 to Q3
We use an AND gate to disabled the
Load input, so we mark with don’t care
condition
4-bit SHIFT REGISTER WITH PARALLEL LOAD AND HOLD OPERATION
In Register Transfer Language:
Control
inputs
Shift : Q
sl Q, Shift Load : Q
1
2
3
1
2
3
1
2
3
1
2
3
Figure 7-10
M. Morris Mano
LOGIC AND COMPUTER DESIGN FUNDAMENTALS
D
AND gates:
1. Enables the Shift operation
2. Enables the input data
3. Restores the contents of
reg. when no operation
Shift Registers with
Parallel Loads and
Hold

S = 0, L = 0 :
◦ AND3 in each stage is
enabled
◦ The output of each FF is
applied to its own D input.
◦ A +ve transition of CLK
restores the contents of
reg.
◦ Output Qi is unchanged
1
2
3
Shift Registers with
Parallel Loads and
Hold
Shift Load : Q

D
S = 0, L = 1 :
◦ AND2 in each stage is
enabled
◦ The input Di is applied to D
input of corresponding FF.
◦ Next +ve transition of CLK
transfers the parallel input
data into reg.
◦ Output Qi = Di
1
2
3
Shift Registers with
Parallel Loads and
Hold

Shift : Q sl Q,
S=1:
◦ AND1 in each stage is
enabled
When +ve edge occurs on
CLK:
◦ Data from serial input SI to
be transferred to FF Q0,
◦ Output Q0 to be
transferred to FF Q1,
…and so on down the line.
1
2
3
Bidirectional Shift Register
Unidirectional Register

◦
Capable of shifting in only one direction (like what we have
discussed in last lecture)
1. Shift on clock pulse
2. Shift & Load
3. Shift, Load & Hold
* shift occurs in one direction only
Bidirectional Register

◦
A register that can shift in both directions
1. Shift Left (sl)
2. Shift Right (sr)
And at the same time is capable of HOLD and LOAD
Bidirectional Shift Register

A0
A1
A2
A3
By placing a 4-input multiplexer in front of each D
flip-flop in a shift register, we can implement a
circuit with shift right, shift left, parallel load, hold.
0
1
2
3
4 to 1
mux
S0 S1

D
S1
S0
Register Operation
0
0
1
1
0
1
0
1
No change (hold)
Shift Left
Shift Right
Parallel Load
Each stage consists of a D-FF and 4:1 multiplexer
Bidirectional Shift Register
How do we represent his in RTL??
S1
S0
Register Operation
0
0
1
1
0
1
0
1
No change (Hold)
Shift Left
Shift Right
Parallel Load
S1S0 : Q
S1S0 : Q
sl Q
S1S0 : Q
S1S0 : Q
sr Q
D
Bidirectional
Shift Register
Let’s analyze the one
stage diagram of a
Bidirectional Shift
Register with parallel
load.
S1
S0
Register
Operation
0
0
No change (Hold)
0
1
Shift Left
1
0
Shift Right
1
1
Parallel Load
4 Bits Bidirectional Shift Register
with Parallel Load
Serial outputs:
(Right Shift)
(Left Shift)
Bidirectional Shift Register

Shift registers can also be designed to
shift more than a single bit position right
or left

Shift register can be designed to shift a
variable number of bit positions specified
by a variable called a shift amount.
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