EEE2135 Digital Logic Design
Chapter 5. Computer Arithmetic
and Adder/Multiplier Design
서강대학교
전자공학과
1. Number System
1)
Positional Number System
a.
A number is represented by a string of digits
b.
2)
(radix point : i = 0)
Positional Number System Conversion
a.
Base-b to decimal
b.
Decimal to base-b
Number System
3)
Representation of Negative Numbers
a.
Signed magnitude representation
- Extra bit to represent the sign
b. Radix Complement Number System
I.
-
II.
III.
More difficult than changing the sign (as in SM)
Addition/subtraction can be performed directly without
sign and magnitude check
– Adopted in most general-purpose computers
.
Number System
c.
Diminished Radix Complement Representation
I.
II.
III.
IV.
V.
D = dn-1dn-2 … d1d0
-D = (b-1-dn-1 ) (b-1-dn-2 ) … (b-1-d1) (b-1-d0 )
Symmetric
Ease of complementation
Addition of 1’s complement number is more difficult
Problem with +0, -0
.
Number System
* Examples of circuits designed carelessly (in Hayes book)
An n-bit Adder/Subtractor
A one-digit BCD adder
Correct n-bit Adder/Subtractor
yn – 1
y1
y0
Add  Sub
control
xn – 1
x1
cn
x0
c0
n-bit adder
sn – 1
s1
s0
x3 x2 x1 x0
Correct one-digit BCD adder
y3 y2 y1 y0
cin
Four-bit adder
z3
z2
z1
z0
Two-bit adder
cout
s3
s2
s1
s0
2. Binary Arithmetic
1)
Additional and Subtraction
a.
Addition
+3 0011
+4 0100
+7 0111
I.
II.
-2 1110
-5 1011
-7 11001
+6 0110
-3 1101
+3 10011
+4 0100
-7 1001
-3 1101
Ignore the carry out of the sigh position
Overflow : a result exceeding the range of a number system

Signs of addend/augend are same, but sign of sum is
different

Carry bits into and out of the sign position are different
-3 1101
+5
-6 1010
+6
-9 10111=+7 +11
0101
0110
1011=-5
Binary Arithmetic
b.
Subtraction
I.
Subtrahend is negated by taking 2’s complement then
minuend and subtrahend are added
II. Overflow : Examine the signs of the minuend and
complement of subtrahend (as in addition) using the same
rule
c.
Hardware (adder/subtractor )
I.
Full Adder
II. Serial Adder
III. CPA (Carry Propagation Adder), RCA (Ripple Carry Adder)
- Simplest (Cascaded connection of full adders)
- Large delay
IV. Carry Lookahead Adder (CLA)
V. Carry Select Adder (CSA)
Binary Arithmetic : Adders
1)
Full Adder
a.
b.
c.
2)
3)
One bit adder used as building blocks for RCA
Simplest
Inputs : xi, yi, and ci (carry input); outputs si, co (carry out)
si = XOR(xi, yi, ci)
co = xiyi + ci(xi + yi)
Serial Adder - ridiculous
Ripple Carry Adder (Carry Propagation Adder)
a.
b.
c.
Constructed by cascading full adders
Simplest, but slowest adder (carry must propagate from the
LSB to the MSB)
Delay = 2 * gate delay * #stages
Full Adder
ci
ci
0
0
0
0
1
1
1
1
xi
0
0
1
1
0
0
1
1
yi
0
1
0
1
0
1
0
1
ci + 1
0
0
0
1
0
1
1
1
si
0
1
1
0
1
0
0
1
xi yi
00 01 11 10
1
1
0
1
1 1
si = xi yi ci
ci
(a) Truth table
xi yi
00 01 11 10
1
0
1 1 1
1
ci + 1 = xi yi + xi ci + yi ci
(b) Karnaugh maps
xi
yi
ci
si
ci + 1
(c) Circuit
Full Adder
s
ci
xi
yi
s
HA
HA
c
si
ci + 1
c
(a) Block diagram
ci
si
xi
yi
ci + 1
(b) Detailed diagram
Serial Adder
X
Y
Si
FA
cout
cin
FF
reset
Carry Propagation Adder
xn –1
cn
x1
yn – 1
FA
sn – 1
MSB position
cn ”
1
c2
y1
x0
y0
c1
FA
FA
s1
s0
LSB position
c0
x1
g1
y1
x0
p1
g0
y0
p0
c1
c2
Stage 1
c0
Stage 0
s1
s0
Flags
Carry Lookahead Adder
4) CLA (Carry Lookahead Adder )
a.
b.
c.
d.
For fast calculation of carry
Used popularly until recently (~ 1980’s)
Delay = (2 ~ 4) * gate delay * #blocks
Based on the following calculation
co = ci +1 = xi yi + (xi + yi) ci = gi + cipi
where , gi = xi yi (Generate term) ;
pi = xi +yi (Propagate term)
Binary Arithmetic
Using the recursive relationship, the equation becomes
co =
=
=
=
=
=
=
c i+1 = x i y i + (x i + y i )c i = g i + p i c i
g i + p i (g i-1+p i-1c i-1)
g i + p i g i-1 + p i p i-1c i-1
g i + p i g i-1 + p i p i-1(g i-2 + p i-2c i-2)
g i + p i g i-1 + p i p i-1g i-2 + p i p i-1p i-2c i-2
g i + p i g i-1 + p i p i-1g i-2 + p i p i-1p i-2(g i-3 + p i-3c i-3)
g i + p i g i-1 + p i p i-1g i-2 + p i p i-1p i-2g i-3 + p i p i-1p i-2p i-3c i-3
i=3
co = c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
Now, c4 depends only on c0. Needs not to wait for c3, c2, c1
First 2 stages of
a CLA
g1
x1
y1
x0
x0
p1
y0
y0
g0
p0
c0
c2
c1
s1
s0
A CLA with ripple-carry between blocks
x31 – 24
c32
x15 – 8
y31 – 24
Block
3
s31 – 24
c24
c16
y15 – 8
Block
1
s15 – 8
x7 – 0
c8
y7 – 0
Block
0
s7 – 0
c0
Critical Path Delay without Fanin Constraint
a.
•
•
b.
•
c.
•
d.
•
Ripple Carry Adder
(2n + 1) gate delay
XOR gate for sum
Carry Lookahead Adder
(2~4) m gate delay (m: # CLA blocks)
Hierarchical CLA
8 gate delay
Carry Select Adder
6 ~ 7 gate delay
Fan-in Limitations
a.
Carry-out function without consideration of fan-in limitation:
3 gate delay
c8  g7  p7 g6  p7 p6 g5  p7 p6 p5 g 4  p7 p6 p5 p4 g 3
 p7 p6 p5 p4 p3 g 2  p7 p6 p5 p4 p3 p2 g1  p7 p6 p5 p4 p3 p2 p1 g 0  p7 p6 p5 p4 p3 p2 p1 p0c0
b.
With 4 fan-in limitation
11 AND + 3 OR
c8  ( g 7  p7 g 6  p7 p6 g5  p7 p6 p5 g 4 )
[( p7 p6 p5 p4 )( g3  p3 g 2  p3 p2 g1  p3 p2 p1 g 0 )]
( p7 p6 p5 p4 )( p3 p2 p1 p0 )c0
CSA
5) Carry Select Adder
a.
b.
c.
d.
Two adder structures are built to form a CSA adder block:
One with carry-in of ‘0’, the other with carry-in of ‘1’
The stage carries and the previous carry are gated to form the
carry for the succeeding stage
Structure (next page)
Each succeeding CSA adder block may be extended by one
stage to account for the delay in the carry lookahead adder
block
CSA
* Delay of Carry Select Adder
Technology 1
2 g
3 g
4 g
5 g
6 g
Technology 2
2 g
3 g
3 g
4 g
4 g
5 g
5 g
4-bit CLA
5-bit CLA
6-bit CLA
7-bit CLA
8-bit CLA
9-bit CLA
10-bit CLA
a. In Technology 1
4- 4-5-6-7-8(6) for 32-bit adder
total delay
= (2 + 1 + 1 +1 +1 + 1) g = 7 g
b. In Technology 2
4-4-6-8-10 for 32-bit adder total delay = 6 g
CSA Structure
X4 – X7 Y4 – Y7
‘1’
X0 – X3
C81
4-7
S41 – S71
Y0 – Y3
1
C0
0-3
C4
S4 – S7
MUX
0
S40 – S70
C80
S0 – S3
‘0’
4-7
X4 – X7 Y4 – Y7
/C8
32-bit CSA Overall Structure
C0
C13
C4
4-7
0-3
13 -18
C190
C191
C80
/C19
/C8
C81
19 - 25 1
/C260 /C26
8 - 12
/C130
C26
/C131
26 - 31
C320
C321
/C32
Binary Arithmetic : Multiplication
1)
Multiplication
a.
Here, we had better go back to 2’s complement NS
I.
To store a number at the register of larger size, sign must
be extended all the way to MSB (Sign Extension)
II.
To correctly represent a 2’s complement number
i=n-2
D = - dn-1 2
n-1
+ Σ di 2i
i=0
b. Signed magnitude is natural for multiplication
- For multiplying two 2’s complement numbers, negative
multiplicand/multiplier must be 2’s complemented
c. In general-purpose processors, multiplication is performed by
a library function call
d. In DSP applications, multiplication is frequent

must be faster

Hardware multiplier is required
Multiplication
2)
Algorithm Description (Multiplication Routine)
mult(X, Y) {
/* Principle : Repetitive ‘Add’ and ‘Shift’ operations */
/* X/Y: multiplicand/multiplier (N bits)
RRext: product (2N bits) (Concatenation of registers R, Rext)
*/
Store the sign of the result;
If X is negative, X <- 2’s complement of X;
If Y is negative, Y <- 2’s complement of Y;
RRext <- 0;
Repeat N times {
Shift right Y register by 1 bit to check if rightmost bit is 1 or 0;
Add X or ‘0…0’ to R depending on the value of y shifted out;
Shift right RRext by 1 bit
}
If the stored sign is negative, find the 2’s complement of RRext
}
Example
Multiplicand X = 6
Multiplier
Y=5
After initialization
Y
0101
X
0110
4
R
0000
4
0000
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
1st iteration
Shift Y to the right;
Add to R;
After addition
Y
0010
X
0110
1
4
R
0110
4
0000
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
1st iteration
Shift RRext to the right
After shifting RRext
Y
0010
X
0110
1
4
R
0011
4
0000
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
2nd iteration
Shift Y to the right;
Add to R;
After addition
Y
0001
X
0110
0
4
R
0011
4
0000
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
2nd iteration
Shift RRext to the right
After shifting RRext
Y
0001
X
0110
0
4
R
0001
4
1000
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
3rd iteration
Shift Y to the right;
Add to R;
After addition
Y
0000
X
0110
1
4
R
0111
4
1000
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
3rd iteration
Shift RRext to the right
After shifting RRext
Y
0000
X
0110
1
4
R
0011
4
1100
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
4th iteration
Shift Y to the right;
Add to R;
After addition
Y
0000
X
0110
0
4
R
0011
4
1100
Rext
Example
Multiplicand X = 6
Multiplier
Y=5
4th iteration
Shift RRext to the right
After shifting RRext
Y
0000
X
0110
0
4
R
0001
4
1110
Rext
Multiplication
3) Hardware Multiplier
a.
Serial multiplier : ridiculous
reset
Serial-to-parallel register
X
Y
FA
Cout
N-1 stages
N bits are out
* A = const, D = O(N2)
- X and Y are presented serially to the circuit (at different rate)
- Partial product is evaluated for every bit of the multiplier and
a serial addition is preformed with the partial sum at reg.
38
Multiplication
b. Parallel multiplier (Braun’s multiplier)
- Good only for multiplication of positive numbers
Carry Save Structure
A
B
C
Ai Bi Ci
+
Ci
+
+
Si
C
S
Multiplier carry-save array
Booth’s Algorithm & Hardware Multiplier
2) (Modified) Booth’s Algorithm
a.
b.
Goal : to reduce # partial products
Idea : find strings of consecutive one’s
11….1 = 100….0 - 1
n
n
c.
d.
#pps reduced depends on the pattern of the multiplier
to make if uniform – Modified Booth’s Algorithm
I.
3-bit encoding (partition into 3-bit overlapping fields )
II. For each field , find pp and shift
III. Reduce #pps to  N /2 
e.
Applicable to both positive and negative numbers.
Booth’s Algorithm
f. Encoding
yi+1 yi yi-1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Operation
Add zero
Add multiplicand
Add multiplicand
Add 2*multiplicand
Sub 2*multiplicand
Sub multiplicand
Sub multiplicand
Sub zero
+0
+X
+X
+2X
-2X
-X
-X
-0
Booth’s Algorithm
g. Example
Multiplicand
X
* 2’s Complement Number

A 2’s complement number Y can be represented by
i = n-2
Y = -yn-12n-1 + Σ
i=0


yi2i
To store a 2’s complement number in a register wider than the
number : Sign extension required
Example : store a 8-bit number at a 16-bit register
numbers
Stored values
00110011
10110011
00000000 00110011
11111111 10110011
Booth’s Algorithm
*
The multiplier Y of 2’s complement number
Yi +1 Yi
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Yi-1
0
1
0
1
0
1
0
1
Di
0
1
1
2
-2
-1
-1
-0
Binary Arithmetic
* Residue Arithmetic (Modular Arithmetic)
a.
Based on more than 1 modulus (must be mutually prime)
Ex) (7, 9) – residue system
N1 = 8 = (1, 8)
N2 = 6 = (6, 6)
b.
c.
N1 = (1, 8)
N1 = (1, 8)
+ N2 = (6, 6)
X N2 = (6, 6)
---------------------(0, 5) = 1410
(6, 3) = 4810
No carry propagation delay effects
Limited range : Largest number m1*m2……-1
Ex. m1 = 15, m2 = 16  fit in well with 8-bit representation
Largest number = 15*16 - 1 = 239
3. Fixed-point and
Floating-point Number Systems
1)
a.
b.
c.
2)
a.
b.
c.
Fixed-point Representation
The binary point in fixed
I.
to the right of LSB : integer representation
II. to the left of MSB : implicit scale factor
Requires programmer to keep track of implicit scale factor
Dynamic range is limited
Floating-point Representation
Binary point is not implicit (explicit)
Scale factor is encoded in each number (exponent field)
Mantissa and exponent M*2E
Dynamic range and precision
* IEEE standard Floating-point Representation
mantissa sign
31
MS
ex.
30
•
23
Exponent (E)
hidden bit
22
0
Mantissa (M)
MS
E
HB M
+1 =
0 01111111 (1).0..……0
( =
0 10000000
0.1…….0 )
* Binary point is just at right of HB
Normalized representation
- leftmost bit of the mantissa is nonzero
(all nonzero floating-point numbers are assumed that HB is 1)
ex.
MS
E
(HB)
M
3.0 = 0
1000 0000 (1) . 100…… 0
(+1)
(1.5)
3)
Floating-point Operations
a.
Fixed-to-float conversion
I.
Convert the number to the system used to represent the
mantissa (e.g. signed magnitude )
II. Starting with an exponent of 0, shift the mantissa’s binary
point to the left (right), adjusting the exponent
III. Convert the resulting exponent into appropriate representation
IV. Pack the mantissa sign, normalized mantissa, and the
exponent into the floating-point format
b. Floating-to-fixed conversion
I.
Expand if using the formula M*2E
II. Overflow detection, truncation may be required
c. Floating-point addition/subtraction
I.
Two numbers are aligned so that both have the same
exponent (by unnormalizing the smaller operand )
II. Mantissa’s are added (subtracted)
III. The result is normalized
d, Floating-point multiplication/division
I.
Exponent are added (subtracted), possible adjustment after
calculation (ex. excess-127 code)
II. Mantissa is multiplied (divided)
III. The result is normalized