I. OBJECTIVES:
1. To analyze a real world problem in terms of how system inputs and the present state
determine the next output state using a state diagram
2. To implement a solution using state diagrams, VHDL, and an FPGA.
II.
PARTS LIST
Equipment:
IBM PC or Compatible with Windows 2000 or Higher
Quartus II Design Software—Version 9.1 or 13.1
Parts:
eSOC III Board
III. INTRODUCTION
A state diagram for a simple two-floor elevator is shown in Figure 5.1.
S0
Arrived 2
S5
Doors: Open
Direction: Down
Motion: Stopped
S1
Doors: Closed
Direction: Up
Motion: Moving
Doors: Closed
Direction: Down
Motion: Stopped
S2
S4
Doors: Closed
Direction: Up
Motion: Stopped
Doors: Closed
Direction: Down
Motion: Moving
S3
Doors: Open
Direction: Up
Motion: Stopped
Arrived 1
Figure 5.1: State Diagram for a Two-Floor Elevator1
1
Thomas Floyd, Digital Fudamentals, 7th ed
Course Number: ECET-230
Laboratory Number: 5
Page 1 of 6
Finite state machines are systems that output a sequence of pre-defined states. The order
of states within that sequence may change as system inputs vary. State diagrams help us
analyze the various ways a system can progress through its output states. Each state can
contain one or more unrelated variables, such as voltage, pressure, speed, and so forth.
The elevator shown in Figure 5.1 has three variables (direction, doors, and motion) and
six output states, represented as bubbles. Arrows between bubbles represent state
transitions. S0 represents the elevator at rest on the upper floor and S3 is the elevator at
rest on the lower floor. Here information from sensors, Arrived 1 and Arrived 2, is used
to detect elevator arrival on either floor.
This state diagram can be translated into a VHDL text file utilizing state variables. A
portion of the text file ARCHITECTURE is shown in Figure 5.2.
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
CASE state IS
WHEN S0 => state <= S1;
WHEN S1 => state <= S2;
WHEN S2 =>
IF ARRIVE1 = 1 THEN
state <=S3;
ELSE state <= S2;
END IF;
WHEN S3 => state <= S4;
WHEN S4 => state <= S5;
WHEN S5 =>
IF ARRIVE2 = 1 THEN
state <=S0;
ELSE state <= S5;
END IF;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
Q <= "000" WHEN S0,
"100" WHEN S1,
"101" WHEN S2,
"010" WHEN S3,
"110" WHEN S4,
"111” WHEN S5;
Figure 5.2: VHDL Description of Two-Floor Elevator
Course Number: ECET-230
Laboratory Number: 5
Page 2 of 6
In this description, the variables are represented by the values for Q, such that Doors is
Q(2) with Open = 0 and Closed = 1; Direction is Q(1) with Down = 0 and Up = 1; and
Motion is Q(0) with Stopped = 0 and Moving = 1.
This example is obviously not an accurate representation of the behavior of an elevator,
because the system is operating without external inputs. In this system, the elevation
would continuously move between floors, without regard to if anyone was waiting.
In order to give a more accurate model, user inputs are required to determine which one
of the two or more possible transitions take place next. In Figure 5.3, inputs have been
added to enhance system functionality. Button activations inside and outside the elevator,
(Floor 1, Floor 2, Call 1, and Call 2), cause a transition from one state to the next and are
indicated next to the arrows between those states. In addition, sensors are added to
indicate the current position of the elevator, (Floor 1, Floor 2), and if the elevator door is
open, DOpen.
S0
Arrived 2
S5
Doors: Open
Direction: Down
Motion: Stopped
Doors: Closed
Direction: Up
Motion: Moving
Floor 1 + Call 1
DOpen + Call 2
S1
Doors: Closed
Direction: Down
Motion: Stopped
Floor 1 + Call 1
Floor 2 + Call 2
S2
S4
Doors: Closed
Direction: Up
Motion: Stopped
Doors: Closed
Direction: Down
Motion: Moving
DOpen + Call 1
S3
Floor 2 + Call 2
Doors: Open
Direction: Up
Motion: Stopped
Arrived 1
Figure 5.3: A Two-floor Elevator With Floor and Call Buttons
This elevator control can be described using the same general format by adding in the
various control buttons. This description is shown in Figure 5.4.
Course Number: ECET-230
Laboratory Number: 5
Page 3 of 6
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
CASE state IS
WHEN S0 =>
IF FLOOR1 = 1 OR CALL1 = 1 THEN
state <= S1;
ELSE state <= S0;
END IF;
WHEN S1 =>
IF DOPEN = 1 AND CALL2 = 1 THEN
state <= S0;
ELSE state <= S2;
END IF;
WHEN S2 =>
IF ARRIVE2 = 1 THEN
state <=S3;
ELSE state <= S2;
END IF;
WHEN S3 =>
IF FLOOR2 = 1 OR CALL2 = 1 THEN
state <= S4;
ELSE state <= S3;
END IF;
WHEN S4 =>
IF DOPEN = 1 AND CALL1 = 1 THEN
state <= S4;
ELSE state <= S5;
END IF;
WHEN S5 =>
IF ARRIVE1 = 1 THEN
state <=S0;
ELSE state <= S5;
END IF;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
Q <= "000" WHEN S0,
"100" WHEN S1,
"101" WHEN S2,
"010" WHEN S3,
"110" WHEN S4,
"111” WHEN S5;
Figure 5.4: VHDL Description of Enhanced Two-Floor Elevator
Course Number: ECET-230
Laboratory Number: 5
Page 4 of 6
In this Lab, we will design a three-color traffic light controller capable of stopping traffic
on one or the other of two cross streets by repeatedly sequencing through a finite number
of pre-determined LED output states.
IV. PROCEDURE
1. Design a controller to operate two separate sets of three traffic light signals, one for
each direction. The configuration is shown in Figure 5.5. Use eight LEDs as shown in
Table 5.1 to represent the outputs. The Time in This State can be met in several ways.
One method is to use a debounced switch as input, another to input a 1 Hz clock,
another to use the internal 24 MHz clock, and a frequency division circuit to create a
1 Hz output.
North-South Road Signal
RYG
R
Y
G
East-West Road Signal
Figure 5.5: Plan for Traffic Light Controller Operation
State
N-S Green
Colored LEDs
G
N-S
Y
N-S Yellow
E-W Green
E-W Yellow
R
E-W
R
5 sec.
1 sec.
R
R
Time in This State
G
Y
5 sec.
1 sec.
Table 5.1 Traffic Light States
Course Number: ECET-230
Laboratory Number: 5
Page 5 of 6
2. Draw the state diagram for the traffic light controller above in the space below.
3. Write, simulate, and demonstrate this program using VHDL and the eSOC III board.
Print out a copy of the text file and simulation diagram to attach to your report.
4. For online students, photograph your final circuit showing the four states shown in
Table 5.1. For onsite students, demonstrate you circuit to your instructor.
Instructor Sign Off____________________
Course Number: ECET-230
Laboratory Number: 5
Page 6 of 6