Enabling Technologies for
Reconfigurable Computing
July 8, 2002, ENST, Paris, France
Reiner Hartenstein
University of
Kaiserslautern
Enabling Technologies for
Reconfigurable Computing and
Software / Configware Co-Design
Part 4:
Recent developments
-.
Schedule
Xputer Lab
University of Kaiserslautern
time
slot
10.00 – 11.00
Reconfigurable Computing (RC)
11.00 – 11.30
coffee break
11.30 – 12.30
Data-Stream-based Computing
12.30 – 14.00
lunch break
14.00 – 15.00
15.00 – 15.30
Resources for RC and
Data-Stream-based Computing
Recent developments
15.30 – 16.00
Discussion
© 2002, [email protected]
2
http://kressarray.de
>> Configware Market
Xputer Lab
University of Kaiserslautern
•
Configware Market (also see appendix)
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
3
http://kressarray.de
bleeding edge designs
Xputer Lab
University of Kaiserslautern
• Infinite amount of gates not yet available on a chip
• 3 mio gates (10 mio in 2003 ?) far away from "infinite"
• Bleeding edge designs only with sophisticated EDA tools
• Excessive optimization needed
• Hardware epertise is inevitable for the designer.
• improve and simplify the design flow the user
• provide rich configware libraries of soft IP cores,
• control appl., networking, wireless telecommunication, data
communication, embedded and consumer markets.
© 2002, [email protected]
4
http://kressarray.de
Xputer Lab
EDA as the Key Enabler (major EDA vendors)
University of Kaiserslautern
• Select EDA quality / productivity, not FPGA architectures
• EDA often has massive software quality problems
• Customer: highest priority EDA center of excellence
–
–
–
–
–
collecting EDA expertise and EDA user experience
to assemble best possible tool environments
for optimum support design teams
to cope with interoperability problems
to keep track with the EDA scene as a rapidly moving target
• being fabless, FPGA vendors spend most qualified manpower
in development of EDA, IP cores, applications , support
• Xilinx and Altera are morphing into EDA companies.
5
http://kressarray.de
© 2002, [email protected]
>> FPGA Market
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
6
http://kressarray.de
Xputer Lab
Top 4 PLD Manufacturers 2000
University of Kaiserslautern
Lattice
15%
Altera
37%
© 2002, [email protected]
Actel
6%
Xilinx
42%
$3.7 Bio
Top 4 PLD Manufacturers 2000
7
http://kressarray.de
FPGA market 1998 / 1999
Xputer Lab
University of Kaiserslautern
Source:
IC Insights Inc.
1999 rank
1
2
3
4
5
6
7
8
Xilinx
Altera
Lattice
Actel
Lucent
Cypress
Quicklogic
Atmel
© 2002, [email protected]
8
Meanwhile,
Xilinx acquired
Philips' MOS PLD
business,
Lattice
purchased Vantis.
.
global sales
1998
629
654
206
154
100
41
30
32
(mio $)
1999
899
837
410
172
120
43
40
38
http://kressarray.de
.... going into every type of application
Xputer Lab
University of Kaiserslautern
• [Dataquest] PLD market
> $7 billion by 2003.
[Gordon Bell]
• „fastest growing segment
of semiconductor market.“
• IP reuse: "pre-fabricated"
components for the
efficiency of design and
use for PLDs
• FPGAs are going into
every type of application.
© 2002, [email protected]
9
http://kressarray.de
>> Embedded Systems (Co-Design)
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
10
http://kressarray.de
Triscend CSoC
Xputer Lab
University of Kaiserslautern
[Kean]
Configurable system logic
ARM
Digital Filter
Display Interface
Viterbi
A/D Interface
CSI Socket
Configurable System Interconnect (CSI) Bus
Memory
© 2002, [email protected]
Other System Resources
11
http://kressarray.de
Goal: away from complex design flow
Xputer Lab
University of Kaiserslautern
[à la S. Guccione]
Schematics/
HDL
Netlister
Netlist
Place
and
Route
Bitstream
HLL
Compiler
© 2002, [email protected]
12
http://kressarray.de
Xputer Lab
Overcome traditional separate design flow
University of Kaiserslautern
[à la S. Guccione]
HLL
Schematics/
HDL
Netlister
Netlist
Compiler
Place
and
Route
.
.
Bitstream
User
Code
Compiler
Executable
© 2002, [email protected]
13
http://kressarray.de
Overcome traditional co-processing design
Xputer Lab
separate flow -> JBits Design Flow
University of Kaiserslautern
[à la S. Guccione]
Schematics/
HDL
JBits
API
Netlister
Netlist
Place
and
Route
User
Java
Code
Java
Compiler
Executable
.
.
Bitstream
User
Code
Compiler
Executable
© 2002, [email protected]
14
http://kressarray.de
>> hardwired IP cores on board
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
15
http://kressarray.de
Xputer Lab
University of Kaiserslautern
HLL
Embedded hardw. CPU & memory cores
on chip.
Compiler
FPGA core
HLL
Compiler
CPU Memory
core
core
[à la S. Guccione]
© 2002, [email protected]
16
http://kressarray.de
Xputer Lab
new directions in application development
University of Kaiserslautern
• new directions in application development.
• aut. partitioning compilers: designer productivity
• like CoDe-X (Jürgen Becker, Univ. of Karlsruhe),
• supports Run-Time Reconfiguration (RTR), a key
enabler of error handling and fault correction by
partial re-routing the FPGA at run time, as well as
remote patching for upgrading, remote debugging,
and remote repair by reconfiguration - even over
the internet.
© 2002, [email protected]
17
http://kressarray.de
Xputer Lab
>> Run-Time Reconfiguration (RTR)
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
18
http://kressarray.de
Xputer Lab
CPU use for configuration management
University of Kaiserslautern
• on-board microprocessor CPU is available
anyhow - even along with a little RTOS
• use this CPU for configuration management
RTR System Design
HLL
© 2002, [email protected]
19
Compiler
http://kressarray.de
hard CPU & memory core on same chip
Xputer Lab
University of Kaiserslautern
HLL
Compiler
FPGA core
RTR System Design
HLL
© 2002, [email protected]
Compiler
20
CPU Memory
core
core
http://kressarray.de
Xputer Lab
Converging factors for RTR
University of Kaiserslautern
• Converging factors make RTR based system design viable
• 1) million gate FPGA devices and co-processing with
standard microprocessors are commonplace
• direct implementation of complex algorithms in FPGAs.
• This alone has already
revolutionized FPGA design.
JBits
• 2) new tools like Xilinx Jbits
API
software tool suite directly
support coprocessing and RTR.
User
Java
Code
© 2002, [email protected]
21
Java
Compiler
Executable
http://kressarray.de
RTR
Xputer Lab
University of Kaiserslautern
• divides application into a series of sequentially executed
stages, each mapped as a separate execution module.
• Excellent example :Xtrem platform by PACT AG, Munich
• Without RTR, all configurable platforms just ASIC
emulators.
• directly support development and debugging of RTR
applications
• will also heavily influence the future system organization
© 2002, [email protected]
22
http://kressarray.de
>> Rapid Prototyping & ASIC Emulation
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
23
http://kressarray.de
Xputer Lab
ASIC emulation: a new business model ?
University of Kaiserslautern
• ASIC emulation / Rapid Prototyping: to replace simulation
• Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)
• from rack to board to chip (from other vendors, e. g.
Virtex and VirtexE family (emulate up to 3 million gates)
• Easy configuration using SmartMedia FLASH cards
• ASIC emulators will become obsolete within years
• By RTR: in-circuit execution debugging instead of emulation
© 2002, [email protected]
24
http://kressarray.de
>> Evolvable Hardware (EH)
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
25
http://kressarray.de
Xputer Lab
EH, EM, ...
University of Kaiserslautern
• "Evolvable Hardware" (EH), "Evolutionary Methods" (EM),
„digital DNA“, "Darwinistic Methods", and biologically
inspired electronic systems
• new research area, also a new application area of FPGAs
• revival of cybernetics or bionics: stimulated by technology
• „evolutionary“ and „DNA“ metaphor create awareness
• EM sucks, also thru mushrooming funds in the EU, in
Japan, Korea, and the USA
• EM-related international conference series are in their
stormy visionary phase, like EH, ICES, EuroGP, GP, CEC,
GECCO, EvoWorkshops, MAPLD, ICGA
26
http://kressarray.de
© 2002, [email protected]
EH, EM, ...
Xputer Lab
University of Kaiserslautern
• Shake-out phenomena expected, like in the past with
„Artificial Intelligence“
• should be considered as a specialized EDA scene,
focusing on theoretical issues.
• Genetic algorithms suck - often replacable by more
efficient ones from EDA
• It is recommendable to set-up an interwoven competence
in both scenes, EM scene and the highly commercialized
EDA scene
• EH should be done by EDA people, rather than EM freaks.
© 2002, [email protected]
27
http://kressarray.de
>> Academic Expertise
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise (see appendix)
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
28
http://kressarray.de
>> ASICs dead ?
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead ?
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
29
http://kressarray.de
Xputer Lab
(When) Will FPGAs Kill ASICs?
[Jonathan Rose]
University of Kaiserslautern
ASICs Are Already Dead
My Position
[Jonathan Rose]
They Just Don’t Know It Yet!
© 2002, [email protected]
30
http://kressarray.de
Xputer Lab
What’s Wrong with This Picture?
University of Kaiserslautern
What About PLD
Cores on ASICs ?
Embedded
FPGA Fabric
[Jonathan Rose]
1. Still Have to Make the Chip
2. Need Two Sets of Software to Build It
– The ASIC Flow
– The PLD Flow
3. Have No Idea What to Connect the PLD Pins to
– Chances Are, You Are Going to Get It Wrong!
31
http://kressarray.de
© 2002, [email protected]
Xputer Lab
What’s Right with This Picture!
University of Kaiserslautern
Embedded
CPU Serial Link,
Analog, “etc.”
[Jonathan Rose]
1. Pre-Fabricated
2. One CAD Tool Flow!
3. Can Connect Anything to Anything
 PLDs are built for general connectivity
© 2002, [email protected]
32
http://kressarray.de
>> Soft CPU
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
33
http://kressarray.de
Xputer Lab
Free 32 bit processor core
University of Kaiserslautern
© 2002, [email protected]
34
http://kressarray.de
Soft CPU: new job for compilers
Xputer Lab
University of Kaiserslautern
Memory
FPGA
core
HLL
© 2002, [email protected]
soft
CPU
Compiler
35
FPGA
http://kressarray.de
Some soft CPU core examples
Xputer Lab
University of Kaiserslautern
core
architecture
platform
MicroBlaze
125 MHz 70
D-MIPS
32 bit
standard RISC
32 reg. by 32
LUT RAMbased reg.
Xilinx up to
100 on one
FPGA
Nios
16-bit
instr. set
Nios
50 MHz
Nios
core
architecture
platform
Leon
25 Mhz
SPARC
ARM7 clone
ARM
uP1232 8-bit
CISC, 32 reg.
Altera
Mercury
200 XC4000E
CLBs
REGIS
32-bit
instr. set
Altera
22 D-MIPS
8 bits Instr. +
ext. ROM
2 XILINX
3020 LCA
Reliance-1
12 bit DSP
8 bit
Altera –
Mercury
Lattice
4 isp30256,
4 isp1016
1Popcorn-1
8 bit CISC
Altera, Lattice,
Xilinx
gr1040
16-bit
gr1050
32-bit
My80
i8080A
FLEX10K30
or EPF6016
YARD-1A
16-bit RISC,
2 opd. Instr.
old Xilinx FPGA
Board
DSPuva16
16 bit DSP
Spartan-II
xr16
RISC integer C
SpartanXL
© 2002, [email protected]
Acorn-1
36
1 Flex 10K20
http://kressarray.de
Xputer Lab
free DSP or Processor Cores
University of Kaiserslautern
CPU core
Description
Language
Implementation
Reliance 1
12bit DSP and peripherals
Schematic
Viewlogic 7 Lattice CPLDs
PopCorn 1
small 8 bit CISC
Verilog
1 Lattice CPLD isp3256-90
Acorn 1
small 8 bit CISC
VHDL
Max2PlusII+ 1 Altera 10k20
16-bit DSP
A 16-bit Harvard DSP with
5 pipeline stages.
VHDL
Xilinx XC4000
Free-6502
6502 compatible core
VHDL
DLX
Generic 32-bit RISC CPU
VHDL
DLX2
Generic 32-bit RISC CPU
VHDL
GL85
i8085 clone
VHDL
AMD 2901
AMD 2901 4-bit slice
VHDL
AMD 2910
AMD 2910 bit slice
VHDL
i8051
8-bit micro-controller
VHDL
Synopsys
i8051
another i8051 clone
VHDL
Mentor Graphics
© 2002, [email protected]
37
Synopsys
http://kressarray.de
Xputer Lab
University of Kaiserslautern
FPGA CPUs in teaching and
academic research
• Michigan State
• Universidad de
Valladolid, Spain
• Virginia Tech
• Washington
University, St. Louis
• New Mexico Tech
• UC Riverside
• Tokai University,
Japan
• UCSC: 1990!
• Märaldalen University,
Eskilstuna, Sweden
• Chalmers University,
Göteborg, Sweden
• Cornell University
• Gray Research
• Georgia Tech
• Hiroshima City
University, Japan
© 2002, [email protected]
38
http://kressarray.de
Xputer Lab
Xilinx 10Mg, 500Mt, .12 mic
University of Kaiserslautern
© 2002, [email protected]
39
http://kressarray.de
Soft rDPA feasible ?
Xputer Lab
University of Kaiserslautern
[à la S. Guccione]
© 2002, [email protected]
40
http://kressarray.de
Array I/O examples
Xputer Lab
University of Kaiserslautern
data streams, or, from / to
embedded memory banks
Performance
1000
100
µProc
60%/yr..
10
1
1980
Processor-Memory
Performance Gap:
(grows 50% / year)
CPU
DRAM
1990
[à la S. Guccione]
2000
DRAM
7%/yr..
data
streams,
or,
from / to
embedded
memory
banks
© 2002, [email protected]
41
http://kressarray.de
HLL 2 Soft Array
Xputer Lab
University of Kaiserslautern
miscellanous
HLL
Compiler
soft CPU
Memory
[à la S. Guccione]
© 2002, [email protected]
42
http://kressarray.de
HLL 2 „flex“ rDPA
Xputer Lab
University of Kaiserslautern
miscellanous
HLL
Compiler
CPU
Memory
[à la S. Guccione]
© 2002, [email protected]
43
http://kressarray.de
>> HLLs
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
44
http://kressarray.de
HLLs for Hardware Design vs.
System Design vs. RTR System
Design
Xputer Lab
University of Kaiserslautern
HLL
Compiler
System Design
HLL
[à la S. Guccione]
© 2002, [email protected]
Compiler
RTR System Design
45
http://kressarray.de
HLLs for Hardware Design vs.
System Design vs. RTR System
Design
Xputer Lab
University of Kaiserslautern
HLL
Compiler
HLL
Compiler
System Design
[à la S. Guccione]
© 2002, [email protected]
46
http://kressarray.de
Embedded System Design
Xputer Lab
University of Kaiserslautern
FPGA core
HLL
Compiler
CPU Memory
core
core
HLL
Memory
core
soft
CPU
FPGA
Compiler
[à la S. Guccione]
© 2002, [email protected]
FPGA
47
http://kressarray.de
>> Problems to be solved
Xputer Lab
University of Kaiserslautern
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
© 2002, [email protected]
48
http://kressarray.de
Xputer Lab
Why Can’t Reconfig. Software Survive?
University of Kaiserslautern
• Resource constraints/sizes are exposed:
– to programmer
– in low-level representation (netlist)
• Design revolves around device size
– Algorithmic structure
– Exploited parallelism
© 2002, [email protected]
49
http://kressarray.de
The future GIGA FPGA
Xputer Lab
University of Kaiserslautern
• Map DPA plus environment onto FPGA
–
–
–
–
no domain-specific silicon needed
turbo turn-around
upgrades via internet on customer’s site
data-stream-based: no v.N bottleneck
• Configware to repeat Software success story ?
• Problems to be solved
– Current FPGA architectures are not scalable
– Configuration Code is not relocatable
– no real Compilers available commercially
• wrong educational background is dominant
© 2002, [email protected]
50
http://kressarray.de
Retargetting
Xputer Lab
University of Kaiserslautern
• FPGA vendors are working at
Retargetting Tools
© 2002, [email protected]
51
http://kressarray.de
Annihilation
Xputer Lab
University of Kaiserslautern
-
+
© 2002, [email protected]
52
+
http://kressarray.de
Xputer Lab
University of Kaiserslautern
structural
CS education .....
Configware / Software Co-Design?
Hardware / Software Co-Design?
procedural
hardware person
© 2002, [email protected]
53
software person
http://kressarray.de
Xputer
Xputer
LabLab
University
Kaiserslautern
University
of of
Kaiserslautern
CS Education
….
…However,
is basedcurrent
on the Submarine
Model
This model disables ...
Algorithm
procedural high level
Programming Language
Brain usage:
procedural-only
Assembly Language
Hardware invisible:
under the surface
Hardware
© 2002, [email protected]
© 2001, [email protected]
54
http://kressarray.de
http://www.fpl.uni-kl.de
Hardware and Software as Alternatives
Xputer
Xputer
LabLab
University
Kaiserslautern
University
of of
Kaiserslautern
procedural
structural
Algorithm
partitioning
Brain Usage:
both Hemispheres
Hardware,
Configware
Software
Software only
& Hardw/Configw
Software only
Hardw/Configw
© 2002, [email protected]
© 2001, [email protected]
55
http://kressarray.de
http://KressArray.de
Dominance of the Submarine Model ...
Xputer
Xputer
LabLab
University
Kaiserslautern
University
of of
Kaiserslautern
(procedural)
structurally
disabled
Hardware
... indicates, that our CS education
system produces zillions of mentally
disabled Persons
It‘s time to attack the software
faculty dictatorship. Get involved!
© 2002, [email protected]
© 2001, [email protected]
… completely disabled to cope with
solutions other than software only
56
http://kressarray.de
http://KressArray.de
>>> thank you
Xputer
Xputer
LabLab
University
Kaiserslautern
University
of of
Kaiserslautern
thank you for your patience
© 2002, [email protected]
© 2001, [email protected]
57
http://kressarray.de
http://KressArray.de
>>> Coarse Grain
Xputer Lab
University of Kaiserslautern
- END © 2002, [email protected]
58
http://kressarray.de
Notes – July 8, 2002
Xputer Lab
University of Kaiserslautern
•
•
•
•
Area efficieny: add ASIC figures (Edelin)
Area efficieny: figures on new FPGAs (9 metal layers)
Survey on algorithms from parallel computing (Edelin)
Power efficieny on reconfigurable platforms: R&D needed
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Academic Expertise
Xputer Lab
University of Kaiserslautern
EDA &
Configware
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Xputer Lab
Configware heading for mainstream
University of Kaiserslautern
• Configware market taking off for mainstream
• FPGA-based designs more complex, even SoC
• No design productivity and quality without good
configware libraries (soft IP cores) from various
application areas.
• Growing no. of independent configware houses
(soft IP core vendors) and design services
• AllianceCORE & Reference Design Alliance
• Currently the top FPGA vendors are the key
innovators and meet most configware demand.
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Xputer Lab
Configware (soft IP Products)
University of Kaiserslautern
• For libraries, creation and reuse of configware
• To search for IPs see: List of all available IP
• The AllianceCORE program is a cooperation
between Xilinx and third-party core developers
• The Xilinx Reference Design Alliance Program
• The Xilinx University Program
• LogiCORE soft IP with LogiCORE PCI Interface.
• Consultants
© 2002, [email protected]
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OS for FPGAs
Xputer Lab
University of Kaiserslautern
• separate EDA software market, comparable to
the compiler / OS market in computers,
• Cadence, Mentor, Synopsys just jumped in.
• < 5% Xilinx / Altera income from EDA SW
• Changing EDA Tools Market
• Major configware
EDA vendors
–
–
–
–
–
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Altera
Cadence
Mentor Graphics
Synopsys
Xilinx
http://kressarray.de
Xputer Lab
EDA Software for Xilinx
University of Kaiserslautern
•Full design flow from Cadence, Mentor, & Synopsys
•Xilinx Software AllianceEDA Program:
–Alliance Series Development System.
–Foundation Series Development Systems.
–Xilinx Foundation Series ISE (Integrated Synthesis Environment)
–free WebPOWERED SW w. WebFitter & WebPACK-ISE
–StateCAD XE and HDL Bencher
–Foundation Base Express
–Foundation ISE Base Express
© 2002, [email protected]
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Xputer Lab
Foundation ISE Base Express
University of Kaiserslautern
• ModelSim Xilinx Edition
(ModelSim XE)
• Forge Compiler
• Modular Design
• Chipscope ILA
• The Xilinx System
Generator
• XPower
© 2002, [email protected]
• JBits SDK
• The Xilinx XtremeDSP
Initiative
• MathWorks / Xilinx
Alliance
• System Generator
• Wind River / Xilinx
alliance
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Altera EDA
Xputer Lab
University of Kaiserslautern
• Altera was founded in June 1983
• EDA: synthesis, place & route, and, verification
• Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families
• MAX+PLUS II: FLEX, ACEX & MAX families
• Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity
deliver a design design software to support Altera SOPC solutions.
• Mentor: only EDA vendor w. complete design environment f. APEX
II incl. IP, design capture, simulation, synthesis, and h/s coverification
• Configware: Altera offers over a hundred IP cores
• Third party IP core design services and consultants
© 2002, [email protected]
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Cadence
Xputer Lab
University of Kaiserslautern
• FPGA Designer: top-down FPGA design system,
• high-level mapping, architecture-specific optimization,
• Verilog,VHDL, schematic-level design entry.
• Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer
• FPGAs simulated by themselves using Cadence's VerilogXL or Leapfrog VHDL simulators and
• simulated w. rest of the system design w. Logic
Workbench board/system verification env‘ment.
• Libraries for the leading FPGA manufacturers.
© 2002, [email protected]
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Mentor Graphics
Xputer Lab
University of Kaiserslautern
• System Design and Verification.
• PCB design and analysis:
• IC Design and Verification
• shifts ASIC design flow to FPGAs (Altera, Xilinx)
–
–
–
–
by FPGA Advantage with IP support
by ModuleWare,
Xilinx CORE Generator
Altera MegaWizard integration,
© 2002, [email protected]
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Synopsys
Xputer Lab
University of Kaiserslautern
• FPGA Compiler II
• Version of ASIC Design Compiler Ultra
• Block Level Incremental Synthesis (BLIS)
• ASIC <-> FPGA migration
• Actel, Altera, Atmel, Cypress, Lattice,
Lucent, Quicklogic, Triscend, Xilinx
© 2002, [email protected]
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Xilinx
Xputer Lab
University of Kaiserslautern
• fabless FPGA semi vendor, San Jose, Ca, founded 1984
• key patents on FPGAs (expiring in a few years)
• Fortune 2001: No. 14 Best Company to work for in (intel:
no. 42, hp no. 64, TI no. 65).
• DARPA grant (Nov‘99) to develop Jbits API tools for
internet reconfigurable / upgradable logic (w. VT)
• Less brilliant early/mid 90ies (president Curt Wozniak):
1995 market share from 84% down to 62% [Dataquest]
• As designs get larger, Xilinx losed its advantage (bugfixes
did not require to burn new chips)
• meanwhile, weeks of expensive debug time needed
© 2002, [email protected]
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Xilinx Flexware
Xputer Lab
University of Kaiserslautern
• Virtex, Virtex-II, first w. 1 mio system gates.
– Virtex-E series > 3 mio system gates.
• Virtex-EM on a copper process & addit. on chip memory f. network switch appl.
• The Virtex XCV3200E > 3 million gates, 0.15-micron technology,
• Spartan, Spartan-XL, Spartan-II
– for low-cost, high volume applications as ASIC replacements
– Multiple I/O standards, on-chip block RAM, digital delay lock loops
– eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers
• XC4000XV, XC4000XL/XLA, CPLD: low-cost families
– rapid development, longer system life, robust field upgradability
– support In-System Programming (ISP), in-board debugging,
– test during manufacturing, field upgrades, full JTAG compliant interface
• CoolRunner: low power, high speed/density, standby mode.
• Military & Aerospace: QPRO high-reliability QML certified
• Configuration Storage Devices
© 2002, [email protected]
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Altera Flexware
Xputer Lab
University of Kaiserslautern
• Newer families: APEX 20KE, APEX 20KC, APEX II, MAX
7000B, ACEX 1K, Excalibur, Mercury families.
– Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates,
– APEX II (all-copper 0.13-µ) f. data path applications, supports
many I/O standards. 1-Gbps True-LVDS performance
– wQ2001, an ARM-based Excalibur device
• Altera mainstream: MAX 7000A, 3000A; FLEX 6000,
10KA, 10KE; APEX 20K families.
• Mature and other : Classic, MAX 7000, 7000S, 9000;
FLEX 8000, 10K families.
© 2002, [email protected]
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Academic Expertise
Xputer Lab
University of Kaiserslautern
Academic
Expertise
© 2002, [email protected]
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Xputer Lab
BRASS (1)
University of Kaiserslautern
• UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek
• The Pleiades Project, Prof. Jan Rabaey, ultra-low power highperformance multimedia computing through reconfiguration
of heterogeneous system modules, reducing energy by
overhead elimination, programmability at just right
granularity, parallellism, pipelining, dynamic voltage scaling.
• Garp integrates processor and FPGA; dev. in parallel w.
compiler - software compile techniques (VLIW SW
pipelining): simple pipelining schema f. broad class of loops.
• SCORE, a stream-based computation model - a unifying
computational model. Fast Mapping for Datapaths: by a treeparsing compiler tool for datapath module mapping
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© 2002, [email protected]
BRASS (2)
Xputer Lab
University of Kaiserslautern
• HSRA. new FPGA (& related tools) supports pipelining, w.
retiming capable CLB architecture, implemented in a 0.4um
DRAM process supporting 250MHz operation
• OOCG. Object Oriented Circuit-Generators in Java
• MESCAL (GSRC), the goal is: to provide a programmer's
model and software development environment for efficient
implementation of an interesting set of applications onto a
family of fully-programmable architectures /
microarchitectures.
© 2002, [email protected]
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Berkeley claiming (1)
Xputer Lab
University of Kaiserslautern
• SCORE, a stream-based computation model: the BRASS group claims
having solved the problem of primary impediment to wide-spread
reconfigurable computing, by a unifying computational model.
• Remark: clean stream-based model introduced ~1980: Systolic Array
• 1995: Rainer Kress. Introduces reconfigurable stream-based model
• Fast Mapping for Datapaths (SCORE): BRASS claims having
introduced 1998 the first tree-parsing compiler tool for datapath
module mapping ." Further, it is the first work to integrate
simultaneous placement with module mapping in a way that preserves
linear time complexity."
© 2002, [email protected]
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Berkeley claiming (2)
Xputer Lab
University of Kaiserslautern
• Remark: The DPSS (Data Path Synthesis System) using
tree covering simultanous datapath placement and routing
has been published in 1995 by Rainer Kress
• „Chip-in-a-Day Bee Project. Prof. Dr. Bob Broderson‘s
„radical rethink of the ASIC design flow aimed at
shortening design time, relying on stream-based DPU
arrays.“ [published in 2000]
• Remark: the KressArray, a scalable rDPU array [1995] is
data-stream-based
© 2002, [email protected]
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Xputer Lab
.... Stream Processors - MSP-3
University of Kaiserslautern
• 3rd Workshop on Media and Stream Processors (MSP-3)
• http://www.pdcl.eng.wayne.edu/msp01
• in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO-34)
• http://www.microarch.org/micro34
• Austin, Texas, December 1-2, 2001
• Topics of interest include, but are not limited to:
– Hardware/Compiler techniques for improving memory
performance of media and stream-based processing
– Application-specific hardware architectures for graphics, video,
audio, communications, and other media and streaming
applications
– System-on-a-chip architectures for media & stream processors
– Hardware/Software Co-Design of media and stream processors
– and others ....
© 2002, [email protected]
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Xputer Lab
Berkeley: „Chip-in-a-Day“ Bee Project
University of Kaiserslautern
• Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting
a radical rethink of the ASIC design flow aimed at shortening
design time. Relying on stream-based DPU arrays (not rDPU and
related EDA tools. Davis: „ „... 50x decrease in power requ. over
typical TI C64X design.“
• New design flow to break up the highly iterative EDA process,
allowing designers to spend more time defining the device and
far less time implementing it in silicon. „... developers to start by
creating data flow graphs rather than C code,„
• It is stream-based computing by DPU array (hardwired DPA)
• For hardwired and reconfigurable DPU array and rDPU array
© 2002, [email protected]
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Xputer Lab
Stanford thru BYU
University of Kaiserslautern
• Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs
• no activities seen other than YAFA (yet another FPGA application)
• UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P
algorithms. 9 projects, mult. sponsors under California MICRO Program
• Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new
routing architecture, architecture-aware CAD, IP-aware SPS compiler
• USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable
computing: MAARC project, DRIVE project and Efficient SelfReconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation o
scalable multiprocessors.
• DEFACTO proj.: compilation - architecture-independent at all levels
• MIT. MATRIX web pages removed `99. „RAW project“: a conglomerate
• VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w
Prof. Brad Hutchings, BYU on programming approaches for RTR System
• BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware
80 of JHDL sources
http://kressarray.de
© Description
2002, [email protected]
Language) and compilation
into FPGAs.
Toronto thru Karlsruhe
Xputer Lab
University of Kaiserslautern
• U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg.
• The group has dev. Transmogrifier C, a C compiler creating netlist for
Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs.
• Founder of Right Track CAD Corporation acquired by Altera in 1999
• Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff
Arnold) – Project Streams-C: programming FPGAs from C sources.
• Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins,
methods for MPEG-4 like multimedia applications on dynamically
reconfigurable platforms, & on reconf. instruction set processors.
• University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker:
hardware/software co-design, reconfigurable architectures & rel.
synthesis for future mobile communication systems & synthesis w.
• distributed internet-based CAD methods, partitioning co-compilers
© 2002, [email protected]
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Academic Expertise
Xputer Lab
University of Kaiserslautern
© 2002, [email protected]
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Academic Expertise
Xputer Lab
ASICs
dead?
University of Kaiserslautern
© 2002, [email protected]
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Xputer Lab
(When) Will FPGAs Kill ASICs?
[Jonathan Rose]
University of Kaiserslautern
ASICs Are Already Dead
My Position
[Jonathan Rose]
They Just Don’t Know It Yet!
© 2002, [email protected]
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Xputer Lab
Why? [Jonathan Rose]
University of Kaiserslautern
1. You have to fabricate an ASIC
 Very hard, getting harder
2. An FPGA is pre-fabricated
 A standard part
 immense economic advantages
© 2002, [email protected]
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Xputer Lab
University of Kaiserslautern
•
•
•
•
•
•
•
Making ASICs is Damn Difficult
[Jonathan Rose]
Testing
Yield
Cross Talk
Noise
Leakage
Clock Tree Design
Horrible very deep submicron effects we
don’t even know about yet
© 2002, [email protected]
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Xputer Lab
Did I Mention Inventory? [Jonathan Rose]
University of Kaiserslautern
• ASIC users must predict # parts
– 2 or 3 months in advance!
• Never guess the Right Amount
– Make Too Many – You Pay holding costs
– Make Too Few – Competitor gets the Sale
© 2002, [email protected]
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[Jonathan Rose]
http://kressarray.de
[Jonathan Rose] FPGAs Give You
Xputer Lab
University of Kaiserslautern
• Instant Fabrication
– Get to Market Fast
– Fix ‘em quick
• Zero NRE Charges
– Low Risk
– Low Cost at good volume
© 2002, [email protected]
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Xputer Lab
FPGAs: “Too Pricey & Too Slow ?”
University of Kaiserslautern
[Jonathan Rose]
• 9 Times Out of 10
– You make can the thing fast by breaking it
into multiple parallel slower pieces
• Custom IC Designer Can Make Logic
– 20x Faster,
– 20x Smaller than Programmable
© 2002, [email protected]
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Xputer Lab
What’s Wrong with This Picture?
University of Kaiserslautern
What About PLD
Cores on ASICs ?
Embedded
FPGA Fabric
[Jonathan Rose]
1. Still Have to Make the Chip
2. Need Two Sets of Software to Build It
– The ASIC Flow
– The PLD Flow
3. Have No Idea What to Connect the PLD Pins to
– Chances Are, You Are Going to Get It Wrong!
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© 2002, [email protected]
Xputer Lab
What’s Right with This Picture!
University of Kaiserslautern
Embedded
CPU Serial Link,
Analog, “etc.”
[Jonathan Rose]
1. Pre-Fabricated
2. One CAD Tool Flow!
3. Can Connect Anything to Anything
 PLDs are built for general connectivity
© 2002, [email protected]
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>> HLLs
Xputer Lab
University of Kaiserslautern
© 2002, [email protected]
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HLLs for Hardware Design vs.
System Design vs. RTR System
Design
Xputer Lab
University of Kaiserslautern
HLL
Compiler
System Design
HLL
[à la S. Guccione]
© 2002, [email protected]
Compiler
RTR System Design
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HLLs for Hardware Design vs.
System Design vs. RTR System
Design
Xputer Lab
University of Kaiserslautern
HLL
Compiler
HLL
Compiler
System Design
HLL
[à la S. Guccione]
© 2002, [email protected]
Compiler
RTR System Design
94
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CPU and memory on Chip
Xputer Lab
University of Kaiserslautern
HLL
Compiler
FPGA core
RTR System Design
HLL
Compiler
CPU Memory
core
core
[à la S. Guccione]
© 2002, [email protected]
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Jbit Environment
Xputer Lab
University of Kaiserslautern
RTP Core
Library
[à la S. Guccione]
JRoute
API
JBits
API
User
Code
BoardScope
Debugger
XHWIF
TCP/IP
Device
Simulator
© 2002, [email protected]
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HLLs for Hardware Design vs.
System Design vs. RTR System
Design
Xputer Lab
University of Kaiserslautern
HLL
Compiler
HLL
Compiler
System Design
[à la S. Guccione]
© 2002, [email protected]
97
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Embedded System Design
Xputer Lab
University of Kaiserslautern
FPGA core
HLL
Compiler
CPU Memory
core
core
HLL
Memory
core
soft
CPU
FPGA
Compiler
[à la S. Guccione]
© 2002, [email protected]
FPGA
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>> RTR
Xputer Lab
University of Kaiserslautern
© 2002, [email protected]
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RTR
Xputer Lab
University of Kaiserslautern
• divides application into a series of sequentially executed stages, each
implemented as a separate execution module.
• Partial RTR partitions these stages into finer-grain sub-modules to be
swapped in as needed.
• Without RTR, all configurable platforms just ASIC emulators.
• needs a new kind of application development environments.
• directly support development and debugging of RTR applications
• essential for the advancement of reconfigurable computing
• will also heavily influence the future system organization
• Xilinx, VT, BYU work on run-time kernels, run-time support, RTR
debugging tools and other associated tools.
• smaller, faster circuits, simplified hardware interfacing, fewer IOBs;
smaller, cheaper packages, simplified software interfaces.
© 2002, [email protected]
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Run-time Mapping
Xputer Lab
University of Kaiserslautern
• run-time reconfigurable are: Xilinx VIRTEX FPGA family
• RAs being part of Chameleon CS2000 series systems
• Using such devices changes many of the basic assumptions
in the HW/SW co-design process:
• host/RL interaction is dynamic, needs a tiny OS like eBIOS,
also to organize RL reconfiguration under host control
• typical goal is minimization of reconfiguration latency
(especially important in communication processors), to hide
configuration loading latency, and,
• Scheduling to find ’best’ schedule for eBIOS calls (C~side).
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Xputer Lab
Processors in PLDs: Excalibur
University of Kaiserslautern
Dual-Port
RAM
Single-Port
RAM
ARM 922T
Core
•High-Speed
Processors
Integrated
with PLDs
General Purpose
PLD
[Jonathan Rose]
© 2002, [email protected]
102 Today!
Available
http://kressarray.de
Xputer Lab
Nios Architecture (Altera)
University of Kaiserslautern
© 2002, [email protected]
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