Timing Analysis
Section 2.4.2
Delay Time
Def: Time required for output signal Y
to change due to change in input signal
X
X
t=0
F(x)
Y
t=0
Up to now, we have assumed this delay
time has been 0 seconds.
Delay Time
In a “real” circuit, it will take tp
seconds for Y to change due to X
X
t=0
F(x)
Y
t=tp
tp is known as the propagation delay time
Timing Diagram
We use a timing diagram to graphically
represent this delay
1
X
0
t=0
time,s
1
Y
0
t=tp
time,s
Horizontal axis = time axis
Vertical axis = Logical level axis (Logic One or Logic Zero)
Timing Diagram
We see a change in X at t=0 causes a
change in Y at t=tp
1
X
0
t=0
t=T
time,s
1
Y
0
t=tp
t=T+tp
time,s
Horizontal axis = time axis
Vertical axis = Logical level axis (Logic One or Logic Zero)
Timing Diagram
We also see a change in X at t=T
causes another change in Y at t=T+tp
1
X
0
t=0
t=T
time,s
1
Y
0
t=tp
t=T+tp
time,s
We see that logic circuit F causes a delay of tp seconds in
the signal
Simple Example – Not Gate
Let tp=2 ns
Where ns = nanosecond = 1x10-9 seconds
X
Y
X
0
2ns
time,ns
Y
2
time,ns
Simple Example – 2 Not Gates
Let tp=2 ns
X
Z
Y
4ns
X
2ns
2ns
Z
Y
0
2
4
Total Delay = 2ns + 2ns = 4ns
6
8
t,ns
Simple Example – 2 Not Gates
Notes:
Time axis is shared among signals
Logic levels (1 or 0) are implied, not shown
X
Z
Y
0
2
4
6
8
t,ns
Simple Example – 2 Not Gates
Sometimes dashed vertical lines are added to aid reading
diagram
2ns
2ns
2ns
2ns
2ns
X
Z
Y
0
2
4
6
8
t,ns
Where does this delay come
from?
Circuit Delay
Circuit Delay
All electrical circuits have intrinsic
resistance (R) and capacitance (C).
C
R
Let’s analyze a simple RC circuit
Circuit Delay – SimpleVinRC Circuit
1
R
Vout(t)
0.9
0.8
0.7
C
Vin(t)
0.6
0.5
0.4
Vout
0.3
0.2
0.1
0
0

 t
Vout  t   Vdd 1  exp  
 

  RC



  RC  time constant
1
2
3
4
5
6
7
Note:
t x  0.69 Vout  t x   0.5Vdd
t x  2.3
Vout  t x   0.9Vdd
t x  4.6
Vout  t x   0.99Vdd
Circuit Delay – Example
Vin
1
R
Vout(t)
0.9
0.8
0.7
Vin(t)
C
0.6
0.5
0.4
Vout
0.3
0.2
0.1
0
0
1
2
3
Let R=1ohm, C=1F, so that RC=1 second
Time Delay is 0.7s or 700 ms for 0.5Vdd
Time Delay is 2.3s for 0.9Vdd
Time Delay is 4.6s for 0.99 Vdd
4
5
6
7
How do we relate this to logic
diagrams?
Def: tplh
tplh = low-to-high propagation delay time
This is the time required for the output to rise from 0V to ½ VDD
1
0.9
0.8
0.7
tplh
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
Def: tphl
Tphl = high-to-low propagation delay time
This is the time required for the output to fall from Vdd to ½ VDD
1
0.9
0.8
0.7
tphl
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
Def: tp
(propagation delay time)
Let’s define tp = propagation delay time as
1
 p   t plh  t phl 
2
This will be the “average” delay through the circuit
Gate Delay – Simple RC Model
Ideal gate with tp=0 delay
RC network
R
Vout(t)
Vin(t)
Ideal gate with RC network
C
Vin(t)
Vout(t)
Tp=tp_not
Equivalent model with
Gate delay of tp_not
Gate Delay - Example
X
X
Y
0
5ns
tp_not
We indicate tp on the gate
25ns
Y
0
5ns
30ns
Combinational Logic Delay
Longest delay


F  a, b, c, d   D  AB  B  C
A
5ns
B
5ns
5ns
5ns
C
This circuit has multiple delay paths
A-Y = 5ns+5ns+5ns=15ns
B-Y = 5ns+5ns+5ns+5ns=20ns
C-Y = 5ns+5ns+5ns=15ns
D-Y = 5ns
Longest delay = 20ns
Shortest delay = 5ns
5ns
D
Shortest delay
Y

Combinational Logic Delay
Longest delay


F  a, b, c, d   D  AB  B  C
A
5ns
B
5ns
5ns
5ns
C
5ns
D
We’ll use the longest delay to represent
the logic function F.
Let’s call it Tcl for time, combinational logic
Longest delay = 20ns
Shortest delay
Y

Combinational Logic (CL)
Cloud Model
A
5ns
5ns
B
X
5ns
C
5ns
D
5ns
F
Y
tcl
E
Tcl=20ns
Tcl=20ns


F  a, b, c, d   D  AB  B  C

Y
Logic Simulators
Used to simulate the output
response of a logic circuit.
Logic Simulations
Three primary types

Circuit simulator (e.g. PSPICE)
 “Exact” delay for each gate
 Most accurate timing analysis
 Very slow compared to other types

Functional Simulation (e.g. Quartus )
 Assumes one unit delay for each gate
 Very fast compared to other types
 Most inaccurate timing analysis

Timing Simulation (e.g. Quartus)
 Assumes “average” tp delay for each gate
 Not the fastest or slowest timing analysis
 Provides “pretty good” timing analysis
TPS Quizzes
Timing Quiz 1
Calculate all delay paths through
the circuit shown below
A
5ns
B
2ns
5ns
8ns
C
10ns
D
What is the shortest and longest delay?
Y
Solution: Calculate all delay paths
through the circuit shown below
A
5ns
B
2ns
5ns
8ns
C
10ns
Y
D
This circuit has multiple delay paths
A-Y = 5ns+5ns+10ns=20ns
B-Y = 2ns+5ns+5ns+10ns=22ns
Shortest path=10ns
B-Y = 8ns+5ns+10ns=23ns
Longest path=23ns
C-Y = 8ns+5ns+10ns=23ns
D-Y = 10ns
Timing Quiz 2
Given the circuit below, find
(a) Expression for the logic function
(b) Longest delay in original circuit
A
5ns
7ns
7ns
B
C
2ns
Y
Solution: Given the circuit below, find
(a) Original logic function
(b) Longest delay in original circuit
A
5ns
7ns
7ns
B
C
2ns


Y   AC   B  C  C
Longest Delay = 7ns+7ns = 14ns
Y
Timing Quiz 3
Given the circuit below,
(a) Using Boolean Algebra, minimize the logic function
(b) Longest delay in minimized circuit
Delay times are
NOT gates= 2ns; AND,OR gates= 5ns
NAND, NOR gates= 7ns; XOR gates: 10ns
XNOR gates: 12ns
A
5ns
7ns
7ns
B
C
2ns
Y
Solution: Given the circuit below, find
(a) Minimized logic function
(b) Longest delay in minimized circuit
Delay times are
NOT gates= 2ns; AND,OR gates= 5ns
NAND, NOR gates= 7ns; XOR gates: 10ns
XNOR gates: 12ns
You can show
A
5ns
7ns
7ns
B
C
2ns
Y
Y  AC
Solution: Given the circuit below, find
(a) Minimized logic function
(b) Longest delay in minimized circuit
Delay times are
NOT gates= 2ns; AND,OR gates= 5ns
NAND, NOR gates= 7ns; XOR gates: 10ns
XNOR gates: 12ns
Y  AC
C
5ns
A
2ns
Longest delay is 7ns
Y
Solution Expanded


Y   AC   B  C  C


Y  AC B  C C  AC  B  C  C
 
 AC C  ( A  C )C  AC
Y  AC
Given the circuit below,
(a) Using a Truth Table and a K-map, minimize the logic
function
A
5ns
7ns
7ns
B
C
2ns
Y
Solution
Do yourself!
D-FF Timing
Section 6.3.3
Def: Clock Period and Switching
Frequency
ClK
Tc
0
Tc = cycle period, seconds
Switching frequency,
1
f 
Tc
D-FF Timing Parameters
Pre
Timing Diagram
time
Clk
D
D
SET
Q
Qn+1
Clk
CLR
Q
D
tsu
thd
Rst
q
tq
Tsu= setup time
0
D must be stable (unchanging) tsu seconds before the clock edge
Thd = hold time
D must be stable thd seconds after the clock edge.
Tq = register delay time
Q becomes valid tq seconds after the clock edge.
If Tsu or Thd are violated, data are NOT stored in D-FF
Maximum Switching Frequency
How fast can our circuits operate
Maximum Switching Frequency Model
No feedback and thd=0ns
IN
CL
F
tin
tcl
Input Buffer
X
No delay on this net
W
R
E
G
tq
thd
tsu
CLK
Reset
We need to find the minimum time, Tc,min, needed
to propagate a signal from input X to node W.
Output Buffer
OUT
tout
Y
Maximum Switching Frequency Model
No feedback and thd=0ns
IN
CL
F
tin
tcl
Input Buffer
X
W
No delay on this net
Output Buffer
R
E
G
OUT
tq
thd
tsu
tout
CLK
Reset
From the model, we see that the minimum cycle time is
Tc ,min  tin  tcl  tsu
Register Setup time
Y
Timing Diagram
Maximum Switching Frequency
This model assumes tq+tout < tin+tcl+tsu
Tc,min
ClK
X
W
Y
Tc.min
tin+tcl
Tc.min
tsu
tq+tout
Tc ,min  tin  tcl  tsu
tin+tcl
tsu
tq+tout
f max 
1
Tc ,min
Setup Time Violation
Clock
Tc
0
tin+tld
Ideal Case
tsu
tsu
tin+tcl
tin+tcl
tin+tld
Clock too
Fast
tsu
tin+tcl
Clock is too fast!!!
We have a setup time violation because the clock is too fast!!!
Correcting a Setup Time Violation
1. Slow down the clock so that
Tc  tin  tcl  tsu
However, in most cases, Tc is a system parameter which cannot
be changed. Plus, most users want their designs to go faster not
slower.
2. Use a pipeline design. Let’s examine this option more closely.
Original Design
IN
CL
F
tin
tcl
Input Buffer
X
No delay on this net
W
R
E
G
tq
thd
tsu
Output Buffer
OUT
tout
CLK
Reset
f max,original
1
1


for tcl  tin , tsu
tin  tcl  tsu tcl
Y
Pipeline Design
X
CL
F1
CL
F2
tcl1
tcl2
F Logic
Let’s break the F Logic into two components, so that
F = F1 + F2 and tcl = tcl1 + tcl2
Y
Pipeline Design
Input Buffer
X
IN
tin
CL
F1
R
E
G
CL
F2
R
E
G
tcl1
tq
thd
tsu
tcl2
tq
thd
tsu
No delay on this net
CLK
Reset
Now, let’s add two register blocks. One between F1 and F2 and
another one at the output.
Output Buffer
OUT
tout
Y
Pipeline Design
Minimum Cycle Time for Each Stage
Stage 1
Input Buffer
X
IN
tin
Stage 2
CL
F1
R
E
G
CL
F2
R
E
G
tcl1
tq
thd
tsu
tcl2
tq
thd
tsu
Output Buffer
OUT
tout
No delay on this net
CLK
Reset
Stage 1
Tc ,1  tin  tcl ,1  tsu
For simplicity,
Stage 2
Tc ,2  tq  tcl ,2  tsu
Let tin  tq
Y
Pipeline Design
Maximum Switching Frequency Calculation
Stage 1
Input Buffer
X
IN
tin
Stage 2
CL
F1
R
E
G
CL
F2
R
E
G
tcl1
tq
thd
tsu
tcl2
tq
thd
tsu
No delay on this net
CLK
Reset
Tc ,min  max Tc ,1 , Tc ,2 
f max 
1
Tc ,min
Output Buffer
OUT
tout
Y
Pipeline Design
Maximum Switching Frequency Calculation
We have,
where
Tc ,min  max Tc ,1 , Tc ,2 
Tc ,1  tq  tcl ,1  tsu ; Tc ,2  tq  tcl ,2  tsu
Let tcl ,1  tcl ,2
Tc ,min
or,
tcl

2
so,
tcl
tcl
 tq   tsu 
2
2
f max, PL 
1
Tc,min
tcl
for
 tsu , tq
2
2
  2 f max,original
tcl
Pipeline Design
Maximum Switching Frequency Calculation
Stage 1
Input Buffer
X
IN
tin
Stage 2
CL
F1
R
E
G
CL
F2
R
E
G
tcl1
tq
thd
tsu
tcl2
tq
thd
tsu
No delay on this net
CLK
Reset
In other words, the pipeline design can run 2x as fast as the
original design. Let’s look at a timing diagram to see why.
Output Buffer
OUT
tout
Y
Pipeline Design Timing Diagram
Clock
0
Stage1
Tc
tsu
tq+tcl1
2Tc
tq+tcl1
tsu
Stages 1
and 2 run
Stage2
Original
Design
tq+tcl2
tsu
tq+tcl
tq+tcl2
tsu
in parallel
tsu
Too Slow
End of Lecture
N-stage Pipeline Design
Pipeline Design
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tld,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tld,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tld,n-1
tsu,t
hd,tq
Reg
CL
Tld,n
No delay on this net
Let’s extend this concept to an N stage pipe
What is the maximum switching frequency?
Let the total logic delay Tcl = Tcl1+Tcl2+ …. + Tcl,N
tsu,t
hd,tq
Out
Outputs
tout
Pipeline Design
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
tsu,t
hd,tq
Out
Outputs
tout
No delay on this net
Tcl
Let tq  tin and tcl ,n 
i.e. all stages have equal delays.
N
Tcl
 tsu
We have for each stage: Tc , n  t q 
N
Pipeline Design
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
Now, assume
So
Tc ,min
Or,
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Tcl
No delay on this net
 tsu  tq
N
Tcl
Tcl
 Tc ,n  tq   t su 
N
N
f max 
1
Tc ,min
N

 Nf original
Tcl
Reg
CL
Tcl,n
tsu,t
hd,tq
Out
Outputs
tout
Pipeline Design
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
tsu,t
hd,tq
No delay on this net
In other words, the pipelined design will operate N times faster than
the original design.
f pipe  Nf original
Out
Outputs
tout
Pipeline Design
PIPE
Stage 1
Stage 2
0
Reg
INPUTS
Inp
tin
CL
Tcl,1
Now, let’s set
So
Tc ,min
Stage n-1
0
tsu,t
hd,tq
Reg
CL
Tcl,2
Stage n
0
tsu,t
hd,tq
.....
0
Reg
CL
Tcl,n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
N 
0
Tcl
 Tc ,n  tq 
 tsu  tq  tsu
N
No delay on this net
Or,
Tc ,min  tq  tsu
constant
tsu,t
hd,tq
Out
Outputs
tout
Pipeline Design
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
No delay on this net
So,
f max 
1
Tc,min
1

tq  tsu
constant
tsu,t
hd,tq
Out
Outputs
tout
Pipeline Design
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
tsu,t
hd,tq
Out
Outputs
tout
No delay on this net
In other words, the absolute maximum frequency of any design is fixed at
f max 
1
Tc,min
1

tq  tsu
We can use this formula to perform a “back of the envelope” calculation to
determine if a desired switching frequency is “feasible”
Pipeline Design- Tradeoffs
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
tsu,t
hd,tq
Out
Outputs
tout
No delay on this net
The pipeline approach is a very powerful design technique.
However, we have two major trade-offs using a
pipelined design. They are
1. Data Load Time and 2. Data Latency Time
DATA Load Time
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
tsu,t
hd,tq
Out
Outputs
tout
No delay on this net
At power-up, we must first “load” the pipeline. This will require a time of
Tload
Note as,
 Tcl

 NTc,min  N  tq   tsu   N  tq  tsu   Tcl
N


N 
we find,
Tload  
unacceptable
DATA Latency Time
PIPE
Stage 1
Stage 2
Reg
INPUTS
Inp
tin
CL
Tcl,1
tsu,t
hd,tq
Stage n-1
Reg
CL
Tcl,2
tsu,t
hd,tq
.....
Stage n
Reg
CL
Tcl,n-1
tsu,t
hd,tq
Reg
CL
Tcl,n
tsu,t
hd,tq
Out
Outputs
tout
No delay on this net
Data will require a finite time to progress through the pipe, this is
equivalent to the Data load time.
 Tcl

Tlatency  NTc ,min  N  tq   tsu   N  tq  tsu   Tcl
N


unacceptable
Note as,
N   we find, Tlatency  