10Gb/s EPON FEC - Coding
gain vs power budget
Contributors names
Sept 2006
Introduction
• From July meeting FEC seems to be a mandatory
part of the budget.
• The purpose of this presentation is to initiate
discussion of using FEC to help 10G EPON power
budgets.
• This first set of slides address following FEC issue
other than framing:
– FEC rates
– Algorithms
– Code gain
– Latency issue
Downstream 29dB link budget
SOA based Tx
SOA based Rx
FEC-IC based Rx
Max: +15dBm
Tx
Max: +5dBm
Max: +4dBm
Min: +13dBm
Min: +1dBm
Min: 0dBm
Loss 28dB
Loss 28dB
Rx
PP: 1dB
Rx Sens:
-16dBm
PP: 1dB
Rx Sens:
-28dBm(??)
(Challenging due to NF)
Loss 28dB
PP: 1dB
Rx Sens:
-29dBm
(Easy/margin with
GFEC/EDC)
RS(255, 239) code: an example
Measured results
Simulated results
Vitesse FEC Performance Curves
1.0E+00
1.0E -01
1.0E -02
B2B GFEC
B2B EFEC
B2B No FEC
1.0E -03
BER
1.0E -04
1.0E -05
1.0E -06
1.0E -07
1.0E -08
1.0E -09
1.0E -10
1.0E -11
1.0E -12
-34
-33
-32
-31
-30
-29
-28
Average Power (dBm)
-27
-26
-25
RS(255, 239) code: an explanation
• The performance of a given code is uniquely
represented by input BER vs. output BER, or
net coding gain (after adjusting noise BW
penalty).
• Optical gain (in dBm) normally donot match
directly to half of the coding gain (in dB).
• Optical gain depends on channel/Rx response
– RS code: 6dB coding gain typically show 4dB
optical gain
• RS codes is implemented in generic CMOS
process
Common codes with std rates
• Coding gain obviously implementation
dependant (slightly).
• 64B/66B code: No rate change as 10.3125Gb/s;
~2.5dB coding gain, input BER=1E-7.
• RS(255, 239): 6-7% overhead, 6dB coding gain;
input BER=1E-4.
• Enhanced FEC: 6-7% overhead same as RS(255,
239) (vendor proprietary); 8.5dB coding gain; input
BER<1E-3.
Other codes in consideration
FEC lowers BER at the expense of overhead
• Other RS codes:
– RS(255, 247): 4% overhead
– RS(255, 223): 12% overhead
• BCH codes (weaker):
– BCH(8191, 8178): 0.15% overhead
– BCH(8191, 8165): 0.32% overhead
– BCH(8191, 8152): 0.48% overhead
• RS+BCH codes
– RS(255, 239)+BCH(127,120): ~13% overhead
Latency issues
• Latency obviously depends on framing and
implementation.
• RS codes potentially has total latency ~1us
– Note: propagation in 300m fiber: ~1us
• In ethernet, preferable small block sizes to
minimize buffer size.
• Some existing FEC IC with long blocks may
has well over ~10um total latency.
Trade-off of rate vs. performance
The group need to answer the following:
• What rate is acceptable?
– Non-std rates may require re-qualify the optics for the
performance in the new rate.
• How much coding gain is enough?
– Need to run through various power budget scenarios
• What is the clear trade-off between FEC perf. and
its implementation (overhead, complexity, latency)?
– Good news: most codes doable in CMOS.
10 Gb/s PON
FEC - Framing
Contributors names
Sept 2006
Introduction
• Presentations in July seemed to
demonstrate general consensus on:
– FEC is definitely needed for 10G
– FEC should be at the lowest layer
• There are two parts to the FEC puzzle
– ‘Framing,’ or how to arrange the bits
– ‘Algorithm,’ or the actual math of FEC
• This set of slides concentrates on framing
FEC framing
• FEC will be applied at the lowest layer
– Below the 64b66b sub-layer
– Right before the PMA
• FEC sub-layer will be responsible for obtaining
codeword lock, because without it, FEC is
impossible
– Frame lock must work with extensive errors
– In the upstream, lock must work very fast
• 64b66b sub-layer will be handed aligned data,
so there is no need for its own framing system
FEC framing structure issues
• There are several differently sized data objects
in the 10G EPON technology that we should
consider:
– 64b66b blocks, 6.4 ns long
– MPCP time quanta, 16 ns long
– FEC codeword, (yet to be determined)
• The simplest and most efficient system will
– Arrange objects so sizes are related by ratios of small
integers
– Result in a final line-rate that is a small integer ratio of
the input MAC rate
64b66b and time quanta
• The least common denominator of time
quanta and 64b66b blocks is 32 ns
– 5 blocks
– 2 time quanta
• Regardless of FEC code choice, if we
want to keep things neat, then time-quanta
should always be specified in even
numbers
RS code as an example
• For this presentation, we will consider the tried
and true RS(239,255) code (and shortened
variants) as a example code
– This gives us a concrete set of code constraints to
work out the method of solution
– This is not meant to favor RS over other codes
• As the PMD analysis moves forward, the choice
of FEC algorithm will get clearer
• However, the basic ideas presented here will
remain the same
Form of FEC codeword
• A FEC codeword will contain three important items
– Framing pattern
– User data
– FEC parity
• In continuous mode systems, framing pattern is typically
short, and state machine with long memory is used to
lock onto codewords
• In burst-mode systems, framing pattern is longer, to
provide instant lock-on
– This can occur once at the beginning of the frame, with no
further framing structure required
Good codeword arrangements
for 66b blocks
• Maximum number of 66b blocks that fit is 28
–
–
–
–
1848 bits payload
40 bits synchronization
128 bits parity
252 total bytes: 9/8 line rate
• With an even number of quanta, 25 blocks fit
–
–
–
–
1650 bits payload
22 bits synchronization
128 bits parity
225 total bytes: 9/8 line rate
Choice of 64b66b encoding
• The 2 bit header in 64b66b is redundant, since
FEC sub-layer will be aligning the data
– Can reduce to 1 bit (the T-bit) to increase effciency
• Sounds good, but redundant bits in the payload
could be used for auxilliary alignment purpose,
so sending 66b blocks is not useless
Good codeword arrangements
for 65b blocks
• Maximum number of 66b blocks that fit is 29
–
–
–
–
1885 bits payload
17 bits synchronization
128 bits parity
2030 total bits: 35/32 line rate
• With an even number of quanta, 25 blocks fit
–
–
–
–
1625 bits payload
22 bits synchronization
128 bits parity
1775 total bits: 71/64 line rate
Downstream FEC synchronization
• In the downstream, any of the above
mentioned framing lengths would work
– We would adjust the state machine
parameters to obtain whatever lock
probabilities we wanted
– For reference, 2^64 was considered a ‘good
lock’ in the 66b system
– 2~4 sync patterns will produce similar results
Upstream FEC synchronization
• Two phases of synchronization
• Initial lock requires a larger and error-resistant
sequence that can reliably produce a unique
autocorrelation signal
– For reference, merely 20 bits is recommended for GPON operating at 1e-4 raw BER
• Maintenance is nearly redundant (protects
against clock slips – how frequent are they?) but
probably will be included to retain clock
frequency harmonization