Computer Systems
4. Digital Logic (continued. . . )
Spyros Voulgaris
Vrije Universiteit
Computer Systems
4. Digital Logic (continued. . . )
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Table of Contents
1
Memory
2
Memory Organization
3
CPU chips
4
Buses
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Table of Contents
1
Memory
2
Memory Organization
3
CPU chips
4
Buses
Computer Systems
4. Digital Logic (continued. . . )
Memory
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SR Latch
Most of the time: S = 0 and R = 0
This circuit has two stable states:
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Q = 0 and Q = 1
Or: Q = 1 and Q = 0
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Memory
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SR Latch
Imagine that Q = 0, Q = 1
. . . and we set S = 1
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Memory
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SR Latch
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Memory
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SR Latch
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Memory
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SR Latch
We have switched to the other stable state: Q = 1, Q = 0
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Memory
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SR Latch
Even after we set S = 0 again
S = “Set” ⇒ it sets Q to 1
R = “Release” ⇒ it sets Q to 0
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Memory
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Clocked SR Latch
We want to control when it is possible to change state
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The clocked SR latch can change state only when clock=1
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Memory
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Clocked SR Latch
We want to control when it is possible to change state
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The clocked SR latch can change state only when clock=1
Problem: What happens if S = R = 1?
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Undeterministic behavior
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Memory
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Clocked D Latch
Let’s make sure that S = R = 1 never happens:
The output of the latch is set to D only when Clock = 1
We have an 1-bit memory!
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Memory
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Table of Contents
1
Memory
2
Memory Organization
3
CPU chips
4
Buses
Computer Systems
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Memory Organization
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An 8-bit Memory Register
Storing two bits:
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Memory Organization
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An 8-bit Memory Register
Storing eight bits:
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Let’s get rid of Q lines
Let’s group all clocks together
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Memory Organization
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An 8-bit Memory Register
To store 1 GB of memory we don’t want to use 2,147,483,652 pins!
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Memory Organization
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A 4 × 3 memory
Let’s build a memory with 4
words of 3 bits each
Don’t be afraid! It is
actually pretty simple :-)
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Memory Organization
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A 4 × 3 memory
Let’s build a memory with 4
words of 3 bits each
2-bit address input:
choose one word to
manipulate
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4. Digital Logic (continued. . . )
Memory Organization
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A 4 × 3 memory
Let’s build a memory with 4
words of 3 bits each
3-bit control:
CS: Chip Select
RD: Choose Read or Write
OE: Output Enable
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4. Digital Logic (continued. . . )
Memory Organization
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A 4 × 3 memory
Let’s build a memory with 4
words of 3 bits each
3-bit data input:
what to do want to
store?
Computer Systems
4. Digital Logic (continued. . . )
Memory Organization
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A 4 × 3 memory
Let’s build a memory with 4
words of 3 bits each
3-bit data output:
read values from memory
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4. Digital Logic (continued. . . )
Memory Organization
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Memory chip organization
With this design a 512 kB memory chip needs 30 pins:
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Note: we use the same pins for data input/output
Question: how many pins do we need for an 1 GB memory chip?
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Memory Organization
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Let’s reduce the number of pins
Large memory chips usually organize words in columns and rows
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512 KB = 4096 Kbits = 2048 × 2048 bits = 211 × 211 bits
RAS = Select raw
CAS = Select column
We now need two cycles to select a memory address
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Memory Organization
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It is better to make several small chips than one big
Split memory into 4 banks
Define a suitable output width
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Memory Organization
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Flash memory
Not available in the book
Computer memory disappears if you switch power off
EEPROM = Electrically Erasable Programmable Read-Only Memory
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Many different types of EEPROM
One common type: Flash memory
The secret behind Flash memory: floating gate transistors
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The floating gate is electrically insulated
It can keep an electric charge for several years
Its electrical field is enough to connect (or not) the source and drain
Program the gate: input the right voltage (∼ 12v) in the control gate
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Memory Organization
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Table of Contents
1
Memory
2
Memory Organization
3
CPU chips
4
Buses
Computer Systems
4. Digital Logic (continued. . . )
CPU chips
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A typical CPU chip
The usual stuff:
Power (+5v)
Ground (0v)
Clock
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4. Digital Logic (continued. . . )
CPU chips
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A typical CPU chip
Addressing:
Select which memory
address the CPU
wants to manipulate
Data:
Send word to write
Receive word to read
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CPU chips
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A typical CPU chip
Bus Control:
Tell whether the
CPU wants to read,
write, or do
something else
Interrupts:
Receive notification
that an I/O has
completed
Bus arbitration:
Make sure only one
device writes in the
bus at once
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CPU chips
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The Pentium4 chip
478 pins
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85 for power, 180 are grounded (better for reducing power usage)
Two pins are missing in one corner
Power usage: 63-82 watts (depending on frequency)
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CPU chips
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The Pentium4 logical pinout
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CPU chips
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Table of Contents
1
Memory
2
Memory Organization
3
CPU chips
4
Buses
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4. Digital Logic (continued. . . )
Buses
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Buses
Buses are used to connect multiple devices
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Buses
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What is a bus?
A bus is just a cable with many parallel electric connections
Using it is mostly a matter of timing. . .
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Buses
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Master vs. slave devices
Master: initiates transfers
Slave: waits for requests
Some devices can be both masters and slaves (e.g., I/O devices)
Memory is always a slave
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Buses
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Synchronous bus clocking
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Buses
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Synchronous bus clocking
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Synchronous bus clocking
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Buses
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Synchronous bus clocking
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Buses
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Synchronous bus clocking
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Buses
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Synchronous bus clocking
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Buses
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Synchronous bus clocking
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Buses
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Synchronous bus issues
Synchronous buses work only by time unit
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What if we design a faster memory?
The bus will slow down transfers
What if some devices are slow and some are fast?
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Everybody needs to run at the slowest speed
V Asynchronous buses!
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No more strict timing. . .
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Buses
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Asynchronous bus operation
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Buses
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Asynchronous bus operation
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Buses
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Bus arbitration
Many masters, many slaves
on the same bus
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We must have only one
signal at a time!
Otherwise: interferences,
no signal gets delivered
We need to decide who can
send data at what time
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Bus arbitration!
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Buses
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Daisy chaining
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Before using the bus, send a request to the bus arbiter
2
The arbiter sends authorization to device 1
3
If device 1 wants to use the bus, it can start now.
Otherwise, pass the authorization to device 2, etc.
The first devices in the chain get higher priority!
(there exist other kinds of buses)
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Buses
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The PCI/Pentium4 bus
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Buses
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PCI bus arbitration
Centralized arbitration
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All devices were created equal. . .
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Buses
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PCI bus signals
Mandatory 32-bit signals:
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Buses
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PCI bus signals
Optional 64-bit signals:
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Buses
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PCI bus operation
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Buses
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Reader
Read the remainder of chapter 3 (the digital logic level) of Structured
Computer Organization except for:
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The example CPU chips sections for non-x86 CPUs (3.5.2 and 3.5.3)
The example buses PCI Express (3.6.3 or 3.6.2 depending on the
edition) and USB (3.6.4 or 3.6.3 depending on the edition)
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Buses
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