FPGA Technology Mapping:
A Study of Optimality
Andrew C. Ling M.A.Sc. Candidate
University of Toronto
Deshanand P. Singh Ph.D.
Altera Corporation
Professor Stephen D. Brown
Altera Corporation Toronto
University of Toronto
Goals


Determine how “good” current FPGA LUT based
technology mappers are in terms of area-optimality
A. Farrahi and M. Sarrafzadeh (1994).
Area problem shown to be NP-Hard
Method



Take a set of benchmark circuits and technology
map them to LUTs using one of the best existing
LUT based technology mappers.
Devise a resynthesis technique that is able to
remove LUTs from these pre-existing technology
mapped circuit.
The more LUTs that can be removed, the farther the
original technology mapping was from the
area-optimal solution.
Resynthesis

Attempt to map a cone with X LUTs to another cone
with less than X LUTs
Sliding Window Approach


Resynthesize subcircuits
Does not give the globally optimal solution; however
gives an indication of the area “left on the table”
Background: The Propositional
Satisfiability (SAT) problem
Given a formula, f :
 Defined over a set of variables, V
(a,b,c)
 Comprised of a conjunction of clauses (C1,C2,C3)
 Each clause is a disjunction of literals of the variables V
SAT: Seek an assignment of to the variables, V, which
sets expression to ‘1’.
Example : (a  b  c)( a  c)( a  b  c)
C1
C2
C3
a=b=c=1
Construction of CNF


T. Larrabee, “Test pattern generation using Boolean
satisfiability," TCAD, 1992 (Plaisted's and Greenbaum's
encoding which is based on Tseitin's work)
Creates a Characteristic Function for circuits
x1x2
00
01
10
11
00
01
10
11
g
0
0
0
0
1
1
1
1
f
1
1
1
0
0
0
0
1
x1
x2
g
f=(x2+¬g) (x1+¬g) (¬x2+¬x1+g)
Construction of CNF (cont’d)
x1
x2
z1
x3
g
f AND= (x2+¬z1) (x1+¬z1) (¬x2+¬x1+ z1)
f OR= (¬x3+g) (¬z1+g) (x3+z1+ ¬g)
f total= fAND fOR
= (x2+¬z1) (x1+¬z1) (¬x2+¬x1+ z1) (¬x3+g) (¬z1+g) (x3+z1+ ¬g)
Formulating Resynthesis Problem
2-LUT
2-LUT
f
?
2-LUT
2-LUT
g
2-LUT


Can function f be implemented in circuit g ?
Does there exist a configuration to g such that for all
inputs to g, f is equivalent to g
Formulating Resynthesis Problem
2-LUT
2-LUT
f
?
2-LUT
2-LUT
2-LUT


Derive characteristic function H for circuit g
Replace all instances of g in H with f
– H[g/f]
(g ≡ f )
– f is equivalent to g
g
Formulating Resynthesis Problem
2-LUT
2-LUT
f
?
2-LUT
2-LUT
g
2-LUT

Does there exist a configuration to g such that for
all inputs to g, f is equivalent to g ?
(g ≡ f )
Formulating Resynthesis Problem
2-LUT
2-LUT
f
?
2-LUT
2-LUT
g
2-LUT
Does there exist a configuration to g such that for
all inputs to g, f is equivalent to g ?
A
E

l1…lm x1…xn(g ≡ f )
Formulating Resynthesis Problem
2-LUT
f
2-LUT
SAT
2-LUT
2-LUT
2-LUT
Express as a QBF with inputs (x1…xn) and
configuration bits (l1…lm)
l1…lm x1…xn (g ≡ f )
Remove quantifiers to form a SAT problem
(A. Biere. “Resolve and Expand”, SAT’04)
E

A

g
Resynthesis Structures Used

Given a MFFC with 7 or less
inputs and containing more
than 2 LUTs, map it to:

Given a MFFC with 10 or less
inputs and containing more
than 3 LUTs, map it to:
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
4-LUT
MCNC Circuit Name
Al
l
30
00
-
i
G
eo 10
m
ea
ns
30
00
+
al
u4
ex
5p
se
q
ex
3
m
is
pd
c
fri
sc
b1
4
b2
0
cl
m
a
b1 b1
5_ 5_
1_ 1
op
t_
C
s3
85
84
.1
s3
84
17
Ratio
Resynthesis Results, 4-LUTs
Resynthesis Results
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
Digital Logic Blocks with Tricks

How intelligent are current technology
mappers when it comes to some common
digital logic blocks?
Techmap 4:1 MUX with 4-LUTs
00
01
10
11
Techmap 4:1 MUX with 4-LUTs
00
01
10
11
Techmap 4:1 MUX with 4-LUTs
00
01
10
11
Logic Block
ge
om
ea
n
4:
it
1
B
16
ar MU
-b
re
X
6- it B l S
bi
hi
t P arr
ft
e
ri o l S er
6bi
t S iri ty hif t
er
et
F
R unc
es
et tion
A
C
he
8- dd
bi
c
C
t A om k
pa
2- dd
bi
r
C
tA
om e
dd
p
C are
om
pa
En re
co
16 der
:
8bi 1 M
tB
U
us X
M
U
X
4b
Ratio
Resuts using 4-LUTs
Area Driven Resynthesis Results
1.2
1
0.8
0.6
0.4
0.2
0
Conclusions



Current 4-LUT technology mappers still have room
for improvement
(~5% on average, up to 10% for some circuits)
For some logic blocks, current technology mappers
have a very difficult time finding the optimal
mapping to 4-LUTs (~36% geomean, up to 67%).
Still has difficultly particularly for non-disjoint
decomposition.
Future Work

Explore BDDs, QBF solvers and All Solution SAT
solvers to speed up process
– If fast enough, this technique can be used as
a valid resynthesis technique.


Use Multiple Output Resynthesis
Search for other optimal configurations of
common logic blocks, used in a caching scheme
for resynthesis
– After technology mapping, search for digital logic
blocks found in our cache, replace digital logic block
with the cached optimal configuration
Questions?