Ultimate Device Scaling: Intrinsic
Performance Comparisons of Carbonbased, InGaAs, and Si Field-effect
Transistors for 5 nm Gate Length
Mathieu Luisier1, Mark Lundstrom2,
Dimitri Antoniadis3, and Jeffrey Bokor4
1ETH
Zurich, 2Purdue University, 3MIT, and
4University of California at Berkeley
Outline
• Motivation
• Simulation Approach
Models and Validation
• General Scaling Considerations
Band-to-band Tunneling
Electrostatics and Contacts
Source-to-drain Tunneling
• Performance Comparisons
• Conclusion and Outlook
Motivation
Motivation: Future of Moore’s Law
65nm (2005)
1. 3-D Si FinFETs for ever?
2. What will be the dominant
limiting factors when Lg<10nm?
45nm (2007)
32nm (2009)
22nm (2011)
5nm (2020)
Source: Intel Corporation
??
Gate Length Reduction in planar Si MOSFETs:
=> increase of short-channel effects (SCE)
=> poor electrostatic control (single-gate)
=> SOLUTION: 3-D FinFET since 2011
Leakage Sources in Ultrascaled Devices
IBT/
S-to-D
BTBT1
HIBL
BTBT2
Band Diagram of Lg=5nm Nano-transistor
How can we minimize leakage?
Best device structure at Lg=5nm:
The least sensitive to leakage
Nanowire
P. Hashemi et al.,
EDL 30, 401 (2009)
Graphene
L. Tapasztó et al., Nat.
Nano. 3, 397 (2008)
III-V UTB
Y.Q. Wu et al., EDL
30, 700 (2009)
CNT
Supratik Guha,
IBM Research
NEEDED: Fast, cheap, and reliable platform to investigate
the performance of next-generation ultrascaled
nano-transistors beyond 3-D FinFETs
Simulation
Approach
State-of-the-art Nano-TCAD Tool
Simulation Capabilities
Physical Models
• Industrial-Strength Nano• 3D Quantum Transport Solver
electronic Device Simulator • Different Flavors of Atomistic
• Multi-Geometry Capabilities Tight-Binding Models
• Investigate Performance of • Multi-Physics Modeling: From
Ultra-Scaled Nano-Devices
Ballistic to Dissipative (e-ph)
before Fabrication
Electron/Hole Transport
More Features
OMEN
• Schrödinger-Poisson
Solver with NEGF and WF
• Finite Element Poisson
TB: sp3d5s*
• Accelerate Simulation Time
through Parallel
MassiveComputing
and MultiEfficient
Level Parallelization
Si Bandstructure
Samstag, 29. Juli 2017
Bias
Momentum
Energy
Space
8
Model Verifications
III-V HEMT
Expt: J. del Alamo @ MIT
CNT FET
Expt: A. Franklin @ IBM YH
BTBT Diode
Expt: S. Rommel @ RIT
S. Datta @ PSU
Zener
Current
NDR
Current
General Scaling
Considerations
Device Characteristics
SG-AGNR
CNT
NW
DG-AGNR
DG-UTB
Id-Vgs at Vds=0.5 V in Carbon Devices
AGNR width: 2.1 nm / CNT diameter: 1.49 nm / Band Gap Eg=0.56 eV
SiO2
EOT=0.64nm
HfO2
EOT=0.64nmHIBL/IBT
BTBT
Observations:
• same EOT gives very different electrostatic gate-channel coupling
• as long as Eg>Vds, BTBT remains weak, but still intra-band tunneling
Intra-Band Tunneling: Electrostatics
Spectral current through GAA CNT FETs with d=1.49 nm,
Eg=0.563 eV, different dielectrics, and EOT=0.64 nm
Fringing Fields:
•stronger when spacer with large εR
•effective channel length is longer
•same effect as gate underlap doping
Intra-Band Tunneling: Material (1)
OBSERVATIONS:
• Current
flows through
the (Gaussian-like barrier)
Fix electrostatic
potential
Id=4.4nA
potential barrier,
almost no
Investigate
how semiconductor
properties influence
IBT
thermionic component
Si NW d=3nm
Eg=1.404eV
• Smaller band gap (and m*)
gives higher intra-band
tunneling current
• Need to understand why
Id=91nA
CNT d=1nm
Eg=0.817eV
Intra-Band Tunneling: Material (2)
What is needed: Under-the-Barrier (UB) model
Same principle as Top-of-the-Barrier (ToB), but with
Complex Bandstructure instead of Real Bandstructure
ToB
Eg=1.408eV
Eg=1.404eV
Eg=1.378eV
Eg=0.817eV
UB
Transmission through potential barrier: T(E)=exp(-2*Κ(E)*L)
Ohmic vs Schottky Contacts
Id-Vgs transfer characteristics for
Si NW and CNT FETs with
Ohmic and Schottky Contacts
Ohmic
Schottky
Performance
Comparisons
Id-Vgs at Vds=0.5 V in CNT, NW, and UTB
Features:
VDD=0.5 V
• CNT with d=0.6nm and
Si/InGaAs NW with
d=3nm have same
band gap: Eg=1.4eV
• CNT with d=1nm has
band gap: Eg=0.82eV
• EOT=0.64nm made of
3.3nm HfO2
• No AGNR since worse
than CNT
• Intrinsic characteristics
•
•
•
•
d=1nm GAA-CNT (high IBT) and DG-UTB (bad electrostatics) scale poorly
3-D devices with same “large” band gap (Eg=1.4 eV) scale better (low IBT)
if CNT with d<1 nm and Eg>1 eV possible, then at least as good as NW
CHALLENGE: trade-off between high injection velocity (low m*) and low
SS (high m*) needed, new constraint at short gate lengths
Conclusion
Conclusion and Outlook
• Simulation Platform for
Lg=5nm Ultra-scaled Devices
Full-band and atomistic
Same approximations for All
• Understand Limiting Factors
Electrostatics and IBT
Trade-off between vinj and SS
•
Outlook
Include non-ideal effects
Try other crystal orientations
Investigate nano-contact physics