STATUS OF DHP PROTOTYPES
PXD/SVD Workshop
24 th September 2012
Tomasz Hemperek, Tetsuishi Kishishita, Hans Krüger, Mikhail Lemarenko, Manuel Koch , Leonard Germic
Overview
• DHP Overview
• DHP 0.2 + Hybrid 5.0
• DHPT 0.1
• DHPT 0.2
• LVDS RX/TX
• ADC
• DHPT 1.0 Planning
2
DHP
To SWITCHERS
768x250 pixel
DEPFET Matrix
192x1000 channels
(rows x cols)
DCD chip
256 inputs, 8-bit ADC per input
4:1 output MUX
320MHz
Per DHP chip:
Raw data memory
Switcher
sequencer
Pedestal subtraction
FIFO 1
Hit finder
FIFO 2
Link layer framing
8b/10b protocol
PLL
3
1.6GHz
Gbit TX
81.29Gbps
(320Mbps output
data x 256 lines)
6 channels per
DCD will be
left unconnected
Deserializer
Common mode
correction
10MHz read-out
frequency
Offset
memory
•
Pedestal
memory
•
Analog
blocks
JTAG
DHP
One 1.6GB output link
per chip
8x8 bit wide data
inputs
8x2 bit wide offset
correction outputs
DHP: Prototype & Tests Chips
DHP 0.1, IBM 90nm, March 2010, half size chip
DHP 0.2, IBM 90nm, July 2011, full size chip
Improved data processing & hit finder, new
data format
CML driver with programmable pre-emphasis
Bias DACs & temperature sensor (U Barcelona)]
DHPT 0.1, TSMC 65nm, November 2011, test chip
Gbit TX (PLL, CML TX)
Memories + JTAG (radiation test)
DACs (UBarcelona)
DHPT 0.2, TSMC 65nm, April 2012, test chip
LVDS TX/RX
ADC (8 bit, 10MS)
TEMP Sensor (UBarcelona)
Planned: DHPT 1.0, TSMC 65nm, Q1 2013
4
DHP 0.2 (full size IBM 90nm) Summary
Verified Blocks
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•
•
•
•
•
•
•
DHP 0.2 @1.6 Gbps,15m Infiniband
LVDS I/O
HSTL like Input
Slow control (JTAG)
Memory read/write
DCD interface
Switcher sequencer
DAC
Gbit link driver
Hybrid 5.0
Test system
See the talk of Florian Lüttike
5
DHPT 0.1 (prototype TSMC 65nm) Summary
100 mV
DHPT 0.1, 20m of Infiniband cable @1.6Gbps of random data
Memory SEU measurements conclusions
6
Memory type
Size
Mean time between
SEU per one chip
Raw data buffer
0.5 Mbit ~30 min
20 us
Pedestals
0.5 Mbit ~30 min
~15 min
Hamming code
Configuration Register
368 bit
~1day
Triple redundancy
490 day
Refresh
rate
Mitigation
DHPT 0.2 (prototype TSMC 65nm) Overview
•
•
•
•
7
LVDS TX/RX
ADC (8 bit, 10Msps)
TEMP Sensor (UBarceolona)
FE Pixels design (ATLAS)
DHPT 0.2 – LVDS RX/TX
LVDS RX
M11 M12
M13 M14
M15
M16
M10
M9
M17
M8
M14
RX
OUT
RX
M1
M2
M18
M19
M20
M3
M6 M7
M4 M5
M21
M22
LVDS TX
M. Gronevald, T. Kishishita
Vbp
5pF
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LVDS Reciver (1.8/2.5V)
LVDS Transmitter (1.8/2.5V)
Level Shifters 1.2V<->1.8/2.5V
Custom IO (ARM compatible)
D
D
CMOS
driver
M4
TX
CMFB
100k
Vcm
100k
Vofs
D
M5
5pF
8
M3
M6
TX
Vbn
LVDS TX/RX Test Setup
T. Kishishita, L. Germic
9
DHPT 0.2 – LVDS TX/RX
PRBS (27-1) @ 320MHz - VDD 1.2V/1.8V
Both receiver and transmitter works as expected.
10
ADC chip on DHPT 0.2
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T. Kishishita, T. Hemperek
11
4 x asynchronous 8bit ADC
4 x synchronous 8bit ADC
2 x TIA
Frequency divider+ serializer
LVDS TX
SAR ADC with Charge Redistribution - Overview
No distribution of fast clock needed - only sample signal!
12
Possible Layouts
Straight DAC
Folded DAC
30 um
70um
120 um
15 um
D
A
C
40 um
65um
Layout is not area optimized
13
DAC
ADC Testbench
T. Hemperek, T. Kishishita, M. Koch
14
DHPT 0.2 – ADC INL/DNL at 10MS/s
Single Ended Mode
Differential Mode
Power Consumption
Works up to 12.5MS/s
~38uW @1.2V
15
TIA
Range: 22uA
LSB: 86nA
16
DHPT 1.0 (TSMC 65nm) Planning
• Pin compatible to DHP 0.2 (still a bit smaller)
• New programmable sequencer (gated mode included)
• Improved programmable delay module for DCD signal sync.
• Error flags included in frame header
• Improved pedestal update (double buffer scheme)
• New trigger mode for gated mode operation
• ... other
Submission in Q1 2013
(new feature requests till end 2012)
17
DHPT 1.0 Planner
http://bit.ly/DHPT10Planner
Please send comments and feature requests to :
[email protected], [email protected], [email protected]
18
Questions?
19
Asynchronous SAR ADC
20
DHPT 0.2 – ADC INL/DNL at 12.5MS/s
Single Ended Mode
21
Differential Mode
Dynamic ADC measurements at 5MS/s
51 dB
Fundamental:
SINAD:
ENOB:
THD:
22
1MHz
44.05dB
7.04
-52.7 dB
We may be limited by generator or not!
Comparison DCD (180nm vs 65nm)
DCD (180nm)
DCD (65nm)
ADC bits
8
8
Pedestal Bits
2
8
Power per input (mW)
~3
~1
Others
23
single DCD+DHP chip
No AmpLow