The first prototype of the FE analog channel
for outer Layers of SVT(L4 & L5)
Bayan Nasri, Carlo Fiorini
Remind of chosen architecture
2
FE-Block Diagram
RF
Peaking
Polarity Time
CF
-A
Q×δ(t)
CD
SHAPER &
GAIN STAGE
T.O.T
PREAMP.
BLH
DETECTOR
Third order complex-pole shaping
Analog Front End Electronics
DAC
OUTPUT
ASIC Architecture (1)
3
External Test signal
Input signal
Charge-PreAmplifier
MUX
CPA-out-Buff
MUX
Gain-out-Buff
Features:
• 6 Test points for the FE
Shaper
Shaper-out-Buff
• Opportunity to apply Ex signal to test buffers
S_BLH
• 2 Test points for the Bias block
• Opportunity to operate external trimming
BLH-FS
BLH
Output of ASIC
T.O.T
DAC
Vref
Bias Block
DAC-Coarse
S
Analog Front End Electronics
ASIC Architecture (2)
4
Power Supply & Biasing:
•Analog
•Digital
Power Supply
&
Bias voltags
•Buffer
Output control Signals
•4 external bias points
Control signals:
•15 input control signals
Coupling Capacitors
•2 output control signals
Control
Signals
ASIC
Output signals:
•7 test points
•T.o.T output
Total PADs: 40
GND
Analog Front End Electronics
Output Signals
FE Channel
5
RF
Peaking
Polarity Time
CF
-A
Q×δ(t)
CD
Features:
SHAPER &
GAIN STAGE
PREAMP.
BLH
DETECTOR
• Two polarity operations
• Four Peaking times (250ns,375ns, 500ns, 750ns)
• Two Bias currents for input FET (500uA, 750uA)
• Two different gain operations for the shaper
Analog Front End Electronics
T.O.T
DAC
OUTPUT
Bias Block
6
Features:
• Produce 200mV reference voltage
• Produce 4 bias points for FE
by help of external resistors
Vref
Vbias
• Produce a reference voltage for DAC_Precise
Ref
D9
D8
D7
D6
D5
Analog Front End Electronics
Vcoarse
DAC_Coarse
Trimming the Threshold level of T.o.T
7
Ref
First Step
•Fine trimming with DAC_Coarse
• 30mV resolution
D9
D8
D7
D6
D5
DAC_Coarse
Second Step
•Precise trimming with DAC_Precise
•1mV resolution
•The bin_Precise= noise(rms)/2
Analog Front End Electronics
D4
D3
D2
D1
D0
Vth_TOT
DAC_Precise
Current generation for DACs
Features:
• Binary based cell
•The same basic cell for all codes
•Randomizing the cell placement
due to minimize the offset
16×I
D(n+4)
8×I
D(n+3)
4×I
D(n+2)
I
2×I
D(n+1)
D(n)
Iout
Analog Front End Electronics
8
Layout of ASIC (submitted on 5th of November 2012)
Analog Front End Electronics
9
Backup slides
Analog Front End Electronics
10
ENC Estimation before radiations damage
• Phi-Strip
• Layer 4
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
250
596
483
207
600
234
695
11
• Z-Strip
• Layer 4
375
491
392
251
644
282
638
500
437
343
288
646
324
586
750
376
288
345
640
388
507
ENC_Total 1237 1166 1121 1077
• Phi-Strip
• Layer 5
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
250
533
389
200
384
128
581
375
463
320
249
427
170
427
500
406
280
283
425
194
396
750
346
233
330
418
228
384
ENC_Total
988
879
836
810
• Z-Strip
• Layer 5
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
375
591
546
261
648
543
648
500
525
477
300
651
622
600
750
452
401
360
653
745
505
1000
405
351
415
655
859
471
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
375
496
377
222
429
350
472
500
441
330
256
428
398
429
750
375
273
303
420
471
389
1000
336
240
351
420
546
359
ENC_Total
1360
1328
1316
1359
ENC_Total
983
946
925
947
Analog Front End Electronics
ENC Estimation after 7.5 years
(without safety factor)
• Phi-Strip
• Layer 4
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
250
596
483
207
600
956
695
12
• Z-Strip
• Layer 4
375
491
392
251
644
1160
638
500
437
343
288
646
1330
586
750
376
288
345
640
1592
507
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
ENC_Total 1545 1620 1709 1883
250
533
389
200
384
878
581
375
463
320
249
427
1166
427
500
406
280
283
425
1326
396
750
346
233
330
418
1566
384
ENC_Total 1316 1450 1555 1749
• Phi-Strip
• Layer 5
• Z-Strip
• Layer 5
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
375
591
546
261
648
1309
648
500
525
477
300
651
1498
600
750
452
401
360
653
1797
505
1000
405
351
415
655
2071
471
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
375
496
377
222
429
1140
472
500
441
330
256
428
1295
429
750
375
273
303
420
1532
389
1000
336
240
351
420
1772
359
ENC_Total
1808
1903
2099
2324
ENC_Total
1465
1553
1727
1934
Analog Front End Electronics
ENC Estimation after 7.5 years
(Safety factor=5)
• Phi-Strip
• Layer 4
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
250
595
483
207
600
2080
704
375
491
392
253
644
2530
635
500
437
343
288
646
2898
588
13
• Z-Strip
• Layer 4
750
376
288
348
640
3470
505
ENC_Total 2411 2771 3091 3613
• Layer 5
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
250
533
389
198
385
2046
581
375
463
320
249
427
2578
427
500
406
280
283
425
2930
396
750
346
233
335
418
3462
384
ENC_Total 2269 2718 3041 3548
• Layer 5
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
375
591
546
262
648
2700
647
500
525
478
301
651
3092
596
750
452
401
360
653
3703
507
1000
405
351
415
655
4266
472
Tp(ns)
ENC_FET
ENC_Rs
ENC_RB
ENC_Rf
ENC_Leakage
ENC_others
375
496
377
225
429
2439
472
500
441
330
256
428
2772
429
750
375
273
303
420
3280
389
1000
336
240
351
420
3799
359
ENC_Total
2974
3306
3859
4395
ENC_Total
2607
2902
3376
3877
Analog Front End Electronics