Results of GET4 Tests
Known Bugs and Performance
Holger Flemming
February 11, 2013
Outline
Known Bugs
DLL Reset Phase
24 bit Serialiser Timing
Further Modifications
DLL lock indication
Sync flag
Bit error rate test
Internal Timing
Process speed
Encoder data latching
Performance
Test Setup
Finetime spectra with correlated Hits
Time resolution
Outlook
DLL Reset Phase (I)
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Left side: Phase detector operation. DLL output comes later
⇒ feedback control to faster DLL
But phase detector has to be initialised to resolve phase
ambiguity
⇒ Reset input of phase detector (rigth side)
Correct phase detector initialisation depends on phase of reset
release
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Red marked reset: Correct initialisation
Green marked reset: Phase detector sees DLL output first ⇒
feedback control to slower DLL
Wrong initialisation!
DLL Reset Phase (II)
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Internal generated DLL reset of GET4 V1.10 unfortunately
has wrong release phase
Solution for GET4 V1.20:
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Configurable phase shifter for DLL reset release
Auto DLL reset (can be disabled!)
If DLL is out of lock state:
1. Generate a 1 µs DLL reset
2. Wait for 10 µs
3. If DLL is still out of lock: increment phase shifter
configuration and go to first step
24 bit Serialiser Timing
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Internal clock divider for reduced serialiser data rates ⇒
inserting clock delays
Unfortunately generated clocks are not constrained
Data sources of serialiser are driven by 160 MHz main clock
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Latch enable register
Data multiplexer switching from event data to epoch data
Serialiser is driven with internally generated delayed clock
⇒ Data corruption by timing violation of serialiser
Will be corrected in Version 1.20
Serialiser will work completely synchronously on 160 MHz
clock
Further Modifications
DLL lock indication
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Internal DLL lock monitor is only available in 32 bit readout
mode
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In Version 1.20 an additional error event for DLL lock loss will
be implemented in 24 and 32 bit readout mode
Sync flag
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Epoch events contain a sync flag to mark external
synchronisation
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In GET4 V 1.10 sync flag is always zero
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Problem is fully understood and will be fixed in version 1.20
Bit Error Rate Test on Serial Downlink
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◮
Till now no option to test
bit errors on serial down
link
New in V 1.20: Bit error
rate test
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17 bit shift register with
xor feedback
operating as pseudo
random code generator
At receiver stage
another 17 bit shift
register is needed
Receiver output: bit
correct: 1, bit error: 0
Process Speed Observations
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Observation: DLL of most GET4 V1.10 ASICs do not lock
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Reason: The latest UMC run seems to be slower than
previous runs
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Run parameter provided by UMC are in specs
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Ring oscillator measurements are close to slow corner
simulations
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Corner simulations:
simulated corner
worst
slow
typical
best
transistor models
slow
slow
typical
fast
temperature
125◦ C
30◦ C
25◦ C
-40◦ C
voltage
1.62 V
1.80 V
1.80 V
1.98 V
Process Speed – Simulation and Mesurements
Ring Oscillator
9
Best Corner
Typical Corner
Worst Corner
Slow Corner
Measurements
8
7
Cycle Time [ns]
6
5
4
3
2
1
0
0
5
10
15
Number of Ring Oscillator Stages [1]
20
25
Process Speed
Symptoms of unlocked slow DLL
Fine time Ch2 (a.u.) 12:05:13
PulseWidth Ch2 [ns] 12:06:29
FineTimeLE2
Entries
115452
Mean
63.81
60.31
RMS
0
Underflow
0
Overflow
Integral
1.155e+05
0.000236
Skewness
60000
50000
PulsWidth2
Entries
Mean
RMS
Underflow
Overflow
Integral
Skewness
230903
1.655
1.436
1.154e+05
1
1.155e+05
-0.0007488
104
40000
103
30000
102
20000
10
10000
0
0
20
40
60
80
100
120
1
0.5
1
1.5
2
2.5
3
3.5
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DLL is to slow
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⇒ New clock edge enters delay chain befor previous edge has
passed the whole chain
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Hits close to clock edge are sampled by two clock edges
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⇒ Second pulse width peak with very short pulse width values
Process Speed
Reasons and work arounds
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Device speed depends on
1. Process variations
2. Temperature ( cold environment ⇒ faster device )
3. Core voltage ( higher voltage ⇒ faster device )
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In MPW runs no influence on process parameters
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Maybe in production run we can ask for faster process
parameters
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Current problem solved by increase of core voltage (from
1.8 V to 1.9 V)
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Reduced margin in case of warm environment in the
experiment
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Influence of radiation damage?
Timing DLL Data Latching
Clock and data path
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Common clock source
PadClk
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Start of timing path: Hit
register
Clock for start register
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Clock split and transfer
line
DLL
Bin clock tree
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Combinatorics: Hit
position encoder
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End of timing path: Data
latch
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Clock for end register
Timing DLL Data Latching
Layout exception for simulation
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Extraction of TDC core layout
Simulation model from parasitic extraction
Timing DLL Data Latching
Simulation results
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Corner effect on register input timing stronger than on
register clock
Simulated slack:
Corner Slack
Setup time tSetup
best
tSl = 1.78 ns − tSetup
≈ 220 ps
typical tSl = 1.088 ns − tSetup ≈ 276 ps
slow
tSl = 500 ps − tSetup
≈ 320 ps
worst
tSl = −356 ps − tSetup ≈ 390 ps
setup violation in worst corner
Timing DLL Data Latching
Measurement, method
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Reducing DLL speed by reducing core voltage
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Effects of slower DLL:
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DLL no longer locks
Two rising edges in delay chain
⇒ double peak in pulse width spectrum
6.4ns
Increasing of Bin size: τBin = 128−∆t
PW
Hit data of Bin 63 arrive later: δ63 = 64 · τBin − 3.2ns
⇒If slack gets negative a gap in finetime spectrum appears
Slack at normal conditions: tSL = δ63 − ∆tFT · τBin
Timing DLL Data Latching
Measurement, results
Fine time Ch0 (a.u.) 11:25:05
PulseWidth Ch0 [ns] 11:29:28
PulsWidth0
Entries
Mean
RMS
Underflow
Overflow
Integral
Skewness
104
253697
3.408
0.2196
1.637e+05
2.135e+04
4.031e+04
0.9494
FineTimeLE0
Entries
125794
Mean
62.1
35.3
RMS
0
Underflow
0
Overflow
Integral
1.258e+05
0.005367
Skewness
2500
2000
103
1500
102
1000
10
500
1
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
0
0
20
40
60
80
100
120
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∆tPW = 9.5 bins ⇒ τBin = 54 ps
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δ63 = 257 ps
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∆tFT = 4 bins ⇒ tSL = 41 ps
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Timing is at the edge and will be configurable shifted in GET4
V1.20
Test setup
Finetime spectra with correlated Hits
Fine time Ch0 (a.u.) 13:09:47
Fine time Ch0 (a.u.) 13:08:39
FineTimeLE0
Entries
104857
Mean
0.6106
0.9281
RMS
0
Underflow
0
Overflow
Integral
1.049e+05
Skewness
122
5
10
FineTimeLE0
Entries
104931
Mean
63.5
0
RMS
0
Underflow
0
Overflow
Integral
1.049e+05
nan
Skewness
5
10
104
104
103
103
102
10
102
0
20
40
60
80
100
120
0
20
Fine time Ch0 (a.u.) 13:10:30
60
80
100
120
Fine time Ch0 (a.u.) 13:11:42
FineTimeLE0
Entries
104729
Mean
64.5
0
RMS
0
Underflow
0
Overflow
Integral
1.047e+05
nan
Skewness
5
10
40
104
104
103
103
102
FineTimeLE0
Entries
104854
Mean
127.5
0
RMS
0
Underflow
0
Overflow
Integral
1.049e+05
nan
Skewness
5
10
102
0
20
40
60
80
100
120
0
20
40
60
80
100
120
Time resolution
PulseWidth Ch0 [ns] 13:14:32 2012-12-11 Analysis/Histograms/PulsWidth0
PulsWidth0
Entries
Mean
RMS
Underflow
Overflow
Integral
Skewness
255385
3.546
0.0378
1.109e+05
3.353e+04
1.109e+05
-5.098
104
3
10
102
10
1
0
2
4
6
8
10
12
Time Difference Ch0 - Ch3 [ns] 13:14:32 2012-12-11 Analysis/Histograms/TimeDiff2
TimeDiff2
Entries
Mean
RMS
Underflow
Overflow
Integral
Skewness
5
10
1015226
0.1286
0.02788
2.638e+05
1.92e+05
5.594e+05
0.2192
104
3
10
102
10
-4
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-2
0
2
4
Internal test pattern generator used to get uncorrelated hits
Pulse width: 37.8 ps RMS / 26.7 ps RMS Uncorrelated
Time Difference (Ch0 and Ch3): 27.9 ps RMS / 19.7 ps RMS
Uncorrelated
Outlook
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A second iteration of GET4 was designed: GET4 V1.20
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All known bugs are corrected
Pin and functional compatible with GET4 V1.10
Same test pcbs and setup can be used for test
Submitted on Feb. 4th