Design procedure for asynchronous circuits
(i)
(ii)
(iii)
(iv)
(v)
(vi)
Obtain a primitive table from specifications
Reduce flow table by merging rows in the primitive flow table
Assign binary state variables to each row of reduced table
Assign output values to dashes associated with unstable states to
obtain the output map
Simplify Boolean functions for excitation and output variables;
Draw the logic diagram
2 input variables x1 and x2 and one
output variable z. Output is 1 only when x1=x2=1 , while x1 being 1 first.
Ex-1: Design a asynchronous sequential circuit with
Solution:
The states are numbered as 1 t0 5 and are shown in rows, the inputs X1X2 are shown
in the colums and the states are shown in the boxes. The output and the next state is
shown in the state diagram.
From the state diagram we can draw the state table as described below.
Initially, when the input X1=X2=0, the machine is in steady state with output as zero.
Now if we change the input from 10(bcs given condition is X1 being ‘1’ first) the state
changes to 2 the transition is shown in blue arrow.
Now we move to state 2 in row 2, The state goes to stable stae with input 10 shown
by circle. From here the both input cannot change simultaneously, so inputs can
change to 00 or 11. Id input changes to 00 the state goes to 1 and if the input
changes to 11 the state move to 3.
Now we go in row-3 for the next state. Here if the input remain as 11 the state 3 will
be stable with output becoming ‘1’ (as per given condition). We cannot change both
input so entry under column 00 is don’t care (-). But can change to 10 or 01. If
changed to 10 the state will become as 2 and if input changes to 01 the state will go
to state 4.
Now we move to next row for analysing
state 4. If now inputs are 01, the state 4
will become stable state with output as
‘0’. The inputs can change to 00 or 11 (
but not 10). If input changes to 00 the
state will change to state ‘1’ and if input
changes to 11 the state will become as
state 5. Note the arrows for other
changes.
Now we move to next row for state 5.
Here if the input remain as 11 the state 5
will be stable state. The input here cannot both change to 00, so the input can
change to 10 or 01. Changing input to 01 will take us to state 4 and chnaging the
input to 10 will take uis to state 2. Note the arrows for other changes.
Implication Chart for reducing the states. The table is formed by writing the states in
1st column starting from 2nd state i.e. 2,3,4,5 and in the bottom row starting from
state 1 and leaving the last state (state 5).
Comparing state 1 and state 2 from primitive table above, we find that the entry for
row 1, and 2 matches in each column (taking
‘-‘ as don’t care) for similar output. So we
mark a right tick in row for state 2 in the
following implication chart.
For row 3(state 3) compare state 1 and state
3 from primitive table above and note that in
both rows entries at respective box in
columns match (considering don’t care as
required)
Similarly we note the entries for row 4,column 1; row 5 column 1 match so put a right tick.
Going this way row 3 and column 2 also match so put a tick. Row 4 and column 2; and row 5 column 2
will match if 3, 5 match.
Row 5 and column 3 does not match having different outputs so have a cross in the box., and finally row
5 and column 4 match put a right tick for it.
Now since row 5 and column 3 has a cross; we can put a cross at box in row 4, column 2, 3 and row 5
column 2.
This completes out reduction table.
Merger Diagram
(1,2),(1,3), (1,4), (1,5), (2, 3), (4,5)
So reduction matrix is (1,2,3), (4,5), The states are A (1,2,3);
B (4, 5)
The Reduced and Final State Table
After the Merger Graph step , we get the secondary variables which need to distinguish between
the states.
Here only two secondary states are required A(1,2,3) and B(4,5). We can use the stable state for
the don’t care terms
Simplification using K-Map
The final circuit is shown
below:
Ex-2: Design a asynchronous sequential circuit with inputs x1,x2 and one output z. Initially
x1=x2=z=0. When x1 or x2 become ‘1’, z become ‘1’. When the second input also become ‘1’,
z changes to ‘0’. The output stays at ‘0’ until the circuit goes back to initial state.
Solution:
The state diagram from the given condition
is drawn first.
The primitive flow table is constructed from
the state diagram or/from the given
condition as :
Implicate Table:
The states in the column are B to F (shown on left of the table, and in row are A to E (shown at the
bottom of table)
Compare Row A with row B, C, D, E and F box by box for similar output of stable state, if they match put
a right tick, if output of stable states do not match put a cross.
If outputs or rows match and if the states in the box do not match, write the mismatching states.
When all rows are done, check for the mismatched conditions, if the corresponding box in implicate
table contain X then write X in that box as shown in box AD, AE, AF.
Now the resuced pairs are (B,C), (D,E), (D,F) and (E,F).
Merger graph:
Ex-3 : Design an asynchronous sequential circuit with two inputs, x1 and x2 , and two
outputs, G and R, as follows.
• Initially, both input values and both output values are 0
• Whenever G = 0 and either x1 or x2 becomes 1, G becomes 1
• When the second input becomes 1, R becomes 1
• The first input value that changes from 1 to 0 turns G equal to 0
• R becomes 0 when G is 0 and either input value changes from 1 to 0
Solution: The state diagram as per the given condition is drawn :
Primitive Flow Table
Merger Graph
Since there are now only two states (ABC, and CDE they being equivalent) only one variable can be used.
Now we can solve using the K-Map the state(S) and the output equation for (G,R)
The synthesis of the above design can be done using basic gates as shown in figure.