EEN1026 Electronics II:
Experiment
Experiment EB1: FET Amplifier Frequency Response
Learning Outcome



LO1:
LO2:
LO3:
Explain the principles and operation of amplifiers and switching circuits
Analyze high and low frequency response of amplifiers
Analyze the operation of power amplifiers and switching circuits.
1.0 Apparatus
Equipment required
Power Supply
Oscilloscope
Digital Multimeter
Breadboard
Function Generator
–1
–1
–1
–1
–1
Components required
N-channel JFET 2N5457
Resistor 10k (1/4W)
Resistor 3.3k (1/4W)
Resistor 3.9k (1/4W)
Resistor 22k (1/4W)
Mylar Capacitor 0.47F
Mylar Capacitor 0.1F
Mylar Capacitor 0.01F
50 k potentiometer
–1
–2
–1
–1
–1
–2
–1
–1
-- 1
Objectives:
1.
2.
3.
4.
Construct and test a voltage amplifier using N-channel JFET device in a common source
configuration
Apply the voltage divider biasing method to set the DC operating point (VGSq , IDSq) .
Verify the estimated DC operating point with the measured data.
Investigate the effect of frequency changes on the voltage gain of the amplifier, measure
its frequency response and obtain its operating bandwidth.
Investigate the capacitance effect on the frequency response of the common source JFET
amplifier
Important Notes
All related calculation questions that does not require experimental data must be
answered before coming to the lab. You are required to show all the calculation steps when
requested by the lab instructor. During the evaluation session, your lab instructor may request
you to demonstrate how the measurement data is obtained and explain your experimental
results.
Report Submission
Submit your report on the same day immediately after the experiment.
EEN1026 Electronics II:
Experiment
2.0 Background Theory
An amplifier is a circuit that increases/decrease the input signal value and in this experiment
the signal to be amplified is the voltage. In this experiment you are going to investigate
frequency response characteristic of a voltage amplifier circuit using the N-channel JFET
device
Most amplifiers have relatively constant gain over a certain range of frequencies. This range
of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier
depends on the circuit component values, the type of active components and the dc operating
point of the active component. When an amplifier is operated within its bandwidth, the
current gain  Ai  , voltage gain  Av  , and power gain A p values are referred to as midband
gain values. A simplified frequency-response curve that represents the relationship between
amplifier gain and operating frequency is shown in Figure 1.
 
Power Gain
Ap drops at lower
frequencies
Mid-band
Ap drops at higher
frequencies
Ap(mid)
Bandwidth
0.5Ap(mid)
fc1
Frequency
fc2
Figure 1: A simplified frequency response curve
As the frequency-response curve shows, the power gain of an amplifier remains
relatively constant across a band of frequencies. When the operating frequency starts to go
outside this frequency range, the gain begins to drop. Two frequencies of interest, f c1 and
f c 2 , are the frequencies at which power gain decreases to approximately 50% of A p (mid ) .
The frequencies labeled f c1 and f c 2 are called the lower and upper cutoff frequencies of an
amplifier, respectively. These frequencies are considered to be the bandwidth limits for the
amplifier and thus bandwidth BW is given by
BW  f c 2  f c1 .
The geometric average of f c1 and f c 2 is called the geometric center frequency fo of an
amplifier, given by
f 0  f c1 f c 2 .
When the operating frequency is equal to f 0 , the power gain of the amplifier is at its
maximum value.
Frequency response curves and specification sheets often list gain values that are
measured in decibels (dB). The dB power gain of an amplifier is given by
EEN1026 Electronics II:
Experiment
A p ( dB )  10 log A p  10 log
Pout
Pin
.
Positive and negative decibels of equal magnitude represent reciprocal gains and losses. A
+3dB gain caused power to double while a –3dB gain caused power to be cut in half.
2
v out
v2
Using the basic power relationships, Pout 
and Pin  in , the power gain may be
Rin
RL
rewritten as
P
v 2 RL
vout
Rin

20
log

10
log
A p ( dB)  10 log out  10 log out
Pin
vin
RL
v in2 Rin
The voltage component of the equation is referred to as dB voltage gain. When the amplifier
input and out resistances are equal
v
A p ( dB )  20 log out  Av ( dB ) .
( Rin  RL )
vin
Thus, when the voltage gain of an amplifier changes by –3dB, the power gain of the amplifier
also changes by –3dB.
Low Frequency Response of FET Amplifier
In the low frequency region of a single stage FET amplifier as shown in Figure 2(a), it is the
RC combinations formed by the network capacitors and the network resistive parameters that
determine the cutoff frequency. There are three capacitors – two coupling capacitor CG and
CD , and one bypass capacitor, C S . Let us assume that CG , CD and C S are arbitrarily large
and can be represented by short-circuit. The total resistance in series with CG is given by
RCG  RG  Rin
where Rin  R1 || R2 is the input impedance of the amplifier circuit. The power supplied by
2
the signal generator is Pin  Vgen
/( RG  Rin ) . However, the reactance XCG of capacitance CG
is not negligible at very low frequencies. The frequency at which Pin is cut in half is when
X CG  RG  Rin . Thus the lower half-power point for gate circuit occurs at frequency
1
1
f LG 

2RCG C G 2 RG  Rin CG
+VDD
R2
RG
CG
RD
G
CD
D
RL
S
Vgen
Vin
R1
RS
CS
Figure 2(a): Schematic diagram of a JFET amplifier
EEN1026 Electronics II:
Experiment
CD
RG
CG
VG
G
D
RD
S
Vgen
Vin
R1||R2
RS
RL
CS
Figure 2(b): JFET amplifier low-frequency ac equivalent circuit
D
VD
gmVgs
CD
RD
RL
S
Figure 2(c): Approximate drain circuit of JFET amplifier (assuming the resistance of
the JFET drain terminal, rd, is much larger than RD).
When CG and C S are arbitrarily large and can be represented by short-circuit, the drain
circuit of the JFET amplifier is as shown in Figure 2(c). At high frequency where CD can also
be represented by a short-circuit, the output power to load resistor RL is Pout  VD2 / RL . At low
frequencies where the reactance XCD of capacitance C D is not negligible, Pout is cut in half
when X CD  RL . Thus the lower half-power point for drain circuit occurs at frequency
1
f LD 
2RL C D
At the half-power point, the output voltage reduces to 0.707 times its midband value. The
actual lower cutoff frequency is the higher value between fLG (determined by CG) and fLD
(determined by CD).
High Frequency Response of FET Amplifier
The high frequency response of the FET is limited by values of internal capacitance,
as shown in Figure 3(a). There is a measurable amount of capacitance between each terminal
pair of the FET. These capacitances each have a reactance that decreases as frequency
increases. As the reactance of a given terminal capacitance decreases, more and more of the
signal at the terminal is bypassed through the capacitance.
EEN1026 Electronics II:
Experiment
+VDD
R2
RG
RD
CD
Cgd
CG
Cds
RL
CL
Cgs
Vgen
R1
CS
RS
Figure 3(a): JFET amplifier with internal capacitors that affect the high frequency
response.
RG
Cout(M)
Vgen
R1||R2
Cgs
Cds
CL
RL||RD
Cin(M)
Figure 3(b): FET amplifier high frequency ac equivalent circuit.
The high frequency equivalent circuit for the FET amplifier in Figure 3(a) is shown in Figure
3(b), including all the terminal capacitance values. C gd is replaced with the Miller equivalent
input and output capacitance values given as
Cin ( M )  C gd  Av  1
and Cout ( M )  C gd
Av  1
Av
Cgd
AV
G
G
AV
D
Cin(M)
Figure 4: Miller equivalent circuit for a feedback capacitor.
D
Cout(M)
EEN1026 Electronics II:
Experiment
Note the absence of capacitors CG , C D and C S in Figure 3(b), which are all assumed to be
short circuit at high frequencies. From this figure, the gate and drain circuit capacitance are
given by
CG  C gs  Cin (M )
C D  C out ( M )  C ds  C L
and
where C L is the input capacitance of the following stage. In general the capacitance C gs is
the largest of the parasitic capacitances, with C ds the smallest. The high cutoff frequencies
for the gate and drain circuits are then given by
f HG 
1
 CG
2Rin
and
f HD 
1
2R' L C D
  RG || Rin and R' L  RD || RL . At very high frequencies, the effect of CG is to
where Rin
reduce the total impedance of the parallel combination of R1 , R2 and CG in Figure 3(b). The
result is a reduced level of voltage across the gate-source terminals. Similarly, for the drain
 will decrease with frequency and consequently
circuit, the capacitive reactance of CD
reduces the total impedance of the output parallel branches of Figure 3(b). It causes the
output voltage to decrease as the reactance becomes smaller.
3.0 Procedures
1. Before connecting the circuit of Figure 5, measure the actual resistance of R1, R2, RD, RS
and RL as accurate as possible with a digital multimeter (set it to the best resistance range)
and record the measured values.
2. Connect the common source JFET amplifier circuit as shown in Figure 5 using a
breadboard (refer to Appendix C). Do not connect the power supply and the function
generator to the circuit yet. Keep the connecting wires on the breadboard as short as
possible (< 3 cm) to reduce unwanted inductance and capacitance in your circuit.
3. Set the power supply output to +12V. Connect its output to the circuit and measure its
voltage VDD(meas) as accurate as possible with the multimeter. Calculate the gate DC
voltage VG(cal) using the voltage-divider rule.
4. Measure the DC voltages VG, VD and VS at G, D, and S pins of the transistor as accurate as
possible. Note that the measured VG should be closed to the calculated VG(cal), and VS
should be > VG since VGS must be < 0 V for N-channel JFET.
5. Before connecting the function generator to the circuit, use an oscilloscope to
measure the output voltage of the generator and set it to 200 kHz sine-wave with a
peak-to-peak voltage of 0.1V. Press the attenuation button (ATT) of the generator for
easy adjustment of its output voltage.
6. Connect the generator output to the circuit. Using Channel 1 (CH1) of the oscilloscope
(set at AC input coupling), probe the input voltage vin. Using Channel 2 (CH2) of the
oscilloscope, probe the load resistor RL, as shown in Figure 5. Set the trigger source of the
oscilloscope to CH2. Adjust the trigger level on the oscilloscope to obtain stable
waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the
calibrated (CAL’D) positions.
EEN1026 Electronics II:
Experiment
+VDD=12V
0.1F
CH1
(vin)
Function Generator
50
R1=22k
D
CD=0.01F
G
CH2
(vL)
S
CG=0.47F
Vgen
RD=3.3k
R2 =10k
RS=3.9k
RL=10k
CS=0.47F
D
Figure 5: A Common source JFET amplifier
S
G
7. Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope
screen as big as possible with one to two cycles. Sketch the input AC voltage (vin) and
the load voltage (vL) waveforms on the graph. Record the Time/div and Volts/div used.
Note that the input and output waveforms should be approximately 180 o out of
phase.
8. From your graph, determine VL(pp) and Vin(pp) which are the peak-to-peak voltages of vL
and vin, respectively. Calculate the voltage gain (Av) of the JFET amplifier circuit at 200
kHz. Ask the instructor to check all of your results. You must show the oscilloscope
waveforms to the instructor.
9. Sweep the frequency of the function generator from 1 kHz to 550 kHz (use smaller
frequency steps near the half-power point while larger steps can be used at mid-band
frequencies). Record the peak-to-peak voltages of vin (CH1) and vL (CH2) and calculate
the dB magnitude of the voltage gain Av. Use both coarse and fine adjustment knobs of
the function generator for frequency adjustment.
10. Plot a curve of Av versus frequency.
11. Calculate the lower cutoff frequency fLD(cal) (use the measured RD and RL values). Set the
frequency to 20 kHz. To measure the lower cutoff frequency (fLD), decrease the generator
frequency until VL(pp) decreases to 0.707VL,mid-band(pp), where VL,mid-band(pp) is the VL(pp) value
in the mid-band.
12. Set the frequency to 300 kHz. To measure the upper cutoff frequency (fHD), increase the
generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp).
13. Determine the bandwidth (BW) and the geometric center frequency (fo) of the amplifier
from the above measurements. Ask the instructor to check all of your results. You
must show the oscilloscope waveforms at 550 kHz to the instructor.
14. Design or modify the circuit in Figure 5 in order to measure the parameter of the device,
namely Gate-Source Cutoff Voltage (VGS(off) or Vp ) and Zero-Gate Voltage Current
(IDSS). These two values can be used in the Shockley equation ID = IDSS (1 – VGS/Vp)2 .
Hint: You can use a potentiometer and/or negative power source in the circuit. By solving
the simultaneous equation of the Shockley equation and the load line equation, you can
obtain the calculated value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the
measured value.
EEN1026 Electronics II:
Experiment
APPENDIX A
The Resistor color code chart
Capacitance
ABC
AB x 10C pF
.abc
0.abc F
Potentiometer
A Var B
Log Scale
The distance in a decade of the log scale in the figure below is x mm. Since log101 = 0, it is
used as a refernce point (0 mm) in the linear scale. Then, the reading 10 is located at x mm
and the reading 0.1 is located at –x mm. For a reading F, it is located at [1og10(F)]*x mm.
E.g.:
Reading 0.25 is located at [1og10(0.25)]*x mm = -0.602x mm
Reading 2.5 is loacted at [1og10(2.5)]*x mm = 0.398x mm
Reading 25 is located at [1og10(25)]*x mm = 1.398x mm (not shown in the figure)
Reading 250 is located at [1og10(250)]*x mm = 2.398x mm (not shown)
Conversely, a point at z mm location is read as 10 z / x .
E.g.:
-0.3x mm is read as 10(-0.3x/x) = 0.501
0.6x mm is read as 10(0.6x/x) = 3.98
1.5x mm is read as 10(1.5x/x) = 31.6 (not shown)
2.7x mm is read as 10(2.7x/x) = 501 (not shown)
-x
-0.602x
-0.3x
0
0.398x0.6x
x
Linear scale
(mm)
0.1
2 3 4 5 6 7 8910
0.2 0.3 0.5
1
0.4 0.6
0.7 0.9 2.5
0.25
3.98
0.501 0.8
Log scale
(unit)
EEN1026 Electronics II:
Experiment
Appendix B: Breadboard Internal Connections
Internal
connections
Horizontally connected
Horizontally connected
+VCC
0.1 F
Vertically
connected
8 7 6 5
555
Vertically
connected
1 2 3 4
0V
GND
Internal
connections
General mistakes:
The legs of the resistors and the transistor are shorted
by the breadboard internal connections.
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EEN1026 Electronics II
Experiment EB1: FET Amplifier Frequency Response
Lab Report
(Submit your report on the same day immediately after the experiment)
Name: ________________________ Student I.D.: _______________ Date: __________
Majoring: ____________________
1.
3.
4.
Group: ____________
Table E1: Measured resistance values
R2
RD
R1
VDD(meas) = ________ V,
Table No.: ____________
RS
RL
[5 marks]
[2 marks]
VG(cal) = ________ V
Table E2: Measured DC voltages
VG
VD
VS
[3 marks]
7.
Graph E1: vin and vL waveforms at 200 kHz
Time base : ______ s/div, CH1 (vin) : ______ V/div, CH2 (vL) : ______ V/div
CH1 & CH2
ground
[5 marks]
8.
Av 
VL ( pp)
Vin( pp )
 ________ at 200 kHz
[1 mark]
EEN1026 Electronics II
9.
Experiment EB1
Table E3: Measure VL(pp) and Vin(pp), and calculated AV
f /kHz
VL(pp) /V
Vin(pp) /V
Av (dB)
1
2
5
10
20
40
60
80
100
200
500
550
[6 marks]
10.
Graph E2: Av versus frequency
[5 marks]
11.
f LD ( cal ) 
1
2 RL  RD C D
f LD (meas)
= _________ Hz
= _________ Hz
12.
f HD (meas)
= _________ kHz
13.
BW = fHD – fLD
= _________ kHz
fo 
= _________ kHz
f LD f HD
[5 marks]
2
EEN1026 Electronics II
Experiment EB1
Questions
1. Identify the sources of error in the calculated VG(cal).
________________________________________________________________________
________________________________________________________________________
2. Calculate the actual DC currents flowing through RD and RS, respectively, IRD and IRS
(calculation steps must be included). Explain why they are the same.
________________________________________________________________________
________________________________________________________________________
3. What is the measured Q-point value (VGSQ, VDSQ, IDQ) of the JFET amplifier circuit?
Analyze and compare this with the calculated one.
________________________________________________________________________
________________________________________________________________________
4. Estimate the lower cutoff frequency of the input circuit, fLG (show your calculation steps).
________________________________________________________________________
5. Estimate the total output capacitance which determines the upper cutoff frequency fHD
________________________________________________________________________
[15 marks]
Discussion
1. Identify how the vin and vL waveforms in Step 7 are related in terms of positive and
negative peak voltages, waveform shapes and phase shift.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
3
EEN1026 Electronics II
Experiment EB1
2. Describe the Av versus frequency characteristic.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
3. Explain the difference between the calculated fLD(cal) and the measured fLD.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
4. Propose why fHD cannot be calculated and as to what factor determines this fHD.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
[16 marks]
Conclusion
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
___________________________________________________________________________
__________________________________________________________________________.
[7 marks]
4