2013 18th IEEE European Test Symposium (ETS)
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Computing Detection Probability of Delay Defects
in Signal Line TSVs
C. Metzler, A. Todri-Sanial, A. Bosio, L. Dilillo, P. Girard, A. Virazel
P. Vivet, M. Belleville
LIRMM UMR 5506 - University of Montpellier 2/CNRS
Montpellier, France
Email: [email protected]
CEA - LETI
Grenoble, France
Email: [email protected]
Abstract—Three-dimensional stacking technology promises to
solve the interconnect bottleneck problem by using ThroughSilicon-Vias (TSVs) to vertically connect circuit layers. However,
manufacturing steps may lead to partly broken or incompletely
filled TSVs that may degrade the performance and reduce the
useful lifetime of a 3D IC.
Due to combinations of physical factors such as switching
activity, supply noise and crosstalk, path delays can experience
speed-up or slow-down that could let the effect of resistive open
TSV go undetected by conventional test methods. In this work,
we present a metric based on probabilistic analysis to detect delay
defects induced by resistive opens that occur on signal line TSVs.
Our experimental result will show the accuracy of the proposed
metric.
I. I NTRODUCTION
Through-Silicon-Vias (TSVs) are the key enablers to
three-dimensional (3D) circuit implementation. TSVs provide
shorter and faster interconnects than the conventional 2D
interconnects due to reduced lengths and parasitics [1] while
enabling signal transmission, power and clock lines between
vertical tiers. Despite the on-going advancements on 3D
processing technologies, there are several challenges related
to design and test of 3D ICs. In this work, we study TSV
resiliency by investigating resistive open defects that can occur
during manufacturing steps.
TSVs are created by etching holes in silicon and filling the
void with metal (e.g. copper). The process of electroplating
the metal can result in partial or porous metal fill meaning
that the TSV channel is not completely filled or partly broken
thus, creating an open defect. Also aging can introduce open
defects in TSVs, where unidirectional large currents creates
voids and hillocks on a TSV. Open defects can be categorized
into resistive open (weak open) and open (strong open) defects.
Strong opens can completely interrupt electrical connection
among tiers, whereas weak opens still conduct but with an
increased resistivity which results in excessive path delay.
Path delays already experience a lot of uncertainty and
variation due to physical (i.e. substrate coupling) and electrical
(i.e. supply noise) conditions on a 3D IC. During test, it
is difficult to determine whether the obtained delay increase
is due to a defective TSV or due to other factors such as
voltage drop. Delay variations induced by resistive open TSVs
can vary drastically. For some cases, delay variations lead to
excessive delay, which facilitates detection of resistive open
978-1-4673-6377-8/13/$31.00 ©2013 IEEE
TSV. Conversely, there are also some cases where path delays
decrease, which prevents detections and faulty TSVs can go
undetected. Such cases occur due to the impact of TSV-toTSV coupling (crosstalk) and non-uniform voltage distribution
among gates on a path which can create artificial delay speedup as shown in [2]–[4] and from a test perspective such
behavior reduces TSV fault coverage.
There are many existing works that look into diagnosis, detection and test methods for resistive-open defects on
conventional 2D interconnects [5]–[12]. There are some ongoing works on resistive open TSVs investigated by [14]–
[17]. In [14] a resistive-open fault model is proposed for
TSVs implemented on 3D DRAM stacking. In [15], delay
variations caused by resistive-opens are investigated and a
method to allocate spare TSVs is proposed. A delay test
scheme TSV aware is presented in [16] where they propose a
variable output threshold (VOT) based oscillator ring structure
to detect small delay defects induced by resistive open TSVs.
In [17] they show probabilistic models on independent and
clustered defects distributions for yield analysis. Despite these
few works, TSV-aware test and detection methods are still in
their early development phase.
This work proposes a probability based metric to detect
resistive open TSVs. We exploit mathematical models to
express path delays as a function of physical (TSV size and
TSV-to-TSV coupling) and electrical factors (power supply
noise and ground bounce [20]) to devise a relationship between delay variation and defect size (resistive open value).
The proposed metric computes a probability of detection for
resistive open TSVs by a joint probability density function.
Such mathematical concepts can be thought of as knobs
for solving the problem and have been shown effective on
other research topics [12]. This formulation allows us to sort
defect sizes (resistive open values) in ranges of detectable and
non-detectable. The main contributions of this work can be
summarized as follows:
• We propose a metric for computing the probability of
detection of resistive opens TSVs while considering physical and electrical factors unique to 3D ICs (such as TSVto-TSV coupling and noise on each tier).
• This metric aims to define relationship between open
defect size in TSV and the probability of detection.
• We detect resistive open defects at lower resistive values
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by taking into account the effect of physical and electrical
factors which can be exploited to facilitate detectability
of resistive open TSVs.
The rest of this paper is organized as follows. In section
II, we present the problem formulation and the mathematical
concepts utilized for this work. In Section III, we provide
the analysis on detection probability for resistive open TSVs.
In Section IV, we present a case study to demonstrate the
goodness of our metric. Section V concludes this paper.
TIER 1
TIER 2
Point B
Point A
RTSV LTSV
Vi1
Cload
TSV 1
Driver
Cc
Receiver
RTSV LTSV
Vi2
TSV 2
Cload
II. M ATHEMATICAL F ORMULATION
In this section, we start by explaining the defect modeling
considered in this work. Second, we describe the delay model
in the presence of physical and electrical factors. Lastly, we
define mathematically the conditions for detecting resistive
open TSVs.
A. Stage-Path Delay Modeling
In this work, we consider a single path stage to investigate
rise-to-fall and fall-to-rise transition delays due to a resistive
open TSV. Figure 1 shows the driver buffer gate, TSV and
receiver buffer gate that are found between two tiers. Due
to proximity between TSVs, we assume the TSV is coupled
through the substrate to neighboring TSVs both inductively
and capacitively. We consider stage-path delay, the delay
measured from point A to point B in order to capture any
transition faults.
Stage-path delay can be derived with respect to the delay
of the buffer and TSV interconnect delay. As shown in [20],
buffer delay can experience either delay speed-up or slowdown due to the voltage levels at power and ground terminals.
Buffer delay is also dependent on the input vector and the
output loading parasitics or the TSV. TSV parasitics play a
critical role on delay and TSV-to-TSV coupling can further
exacerbate delay variations. TSV-to-TSV coupling impacts can
be thought of similarly as crosstalk concept on interconnects.
Depending on input vectors, capacitive coupling can speed-up
or slow-down stage-path delays. Thus, stage-path delay can
vary due to multiple parameters introduced from both physical
and electrical factors. Stage-path delay can be expressed as a
function of physical and electrical conditions as:
D0 ≡ ∆d = f (RT SV , LT SV , Cc , VDD , VSS , Vin )
(1)
where RT SV , LT SV , Cc are the TSVs parasitics, VDD and
VSS power and ground supply voltage and Vin the input
vectors that contain the transition states (low to high (LH)
or high to low (HL)).
Thus, to further investigate stage-path delay variations in
the presence of a resistive open TSV, it is important to
understand the sources of path delay variation with ideal TSV
so we can later differentiate the impact of a defective TSV.
In the following subsections, we present stage-path delay as
a function of physical-electrical factors and resistive open
TSV. Based on these mathematical models, we formulate our
detection probability metric.
Fig. 1.
Stage-path delay measured from point A to B.
B. Delay Modeling Considering Physical and Electrical Factors
Delay threshold is normally used to identify a fault or faultfree behavior. As delay can vary due to several aforementioned
factors (either increase or decrease), it is challenging to detect
a fault. In this work, we assume that a stage-path having
a delay greater than delay threshold DT is considered as a
transition fault. For each transition (HL and LH), we identify
transition faults by computing the stage-path delay.
B.1 Delay for Rising (LH) Transition: For a rising transition, the incremental charge on buffer delay considering power
and ground supply noise can be expressed as in [20]:
∆dLH = k1r .(∆VDD + ∆VSS ) − k2r .(∆VDD − ∆VSS ) + k5r
(2)
where k1r and k2r are positive constants and their value
depend on the rising input transition, gate load, and parasitics.
The constants k1r , k2r and k5r are given by [20]:
CT SV
tr + ∆tr
+
2VDD .(1 + α)
2IDO
CT SV
tr + ∆tr
−
k2r =
2VDD .(1 + α)
2IDO
1 − vt
k5r = ∆tr . 0.5 −
1+α
k1r =
(3)
(4)
(5)
where α, is the ratio of drain to source current, vt is the
threshold voltage, IDO is the drain saturation current at
VGS = VDS = Vdd of the inverter. This formulation allows to
compute stage-path delay for LH transition while considering
the parasitics of TSVs, TSV-to-TSV coupling, input vector,
transition time and supply voltages at power and ground
terminals.
B.2 Delay for Falling (HL) Transition: In a similar way
stage-path delay can be estimated for a falling transition, as
in [20]:
∆dHL = −k1f .(∆VDD + ∆VSS ) − k2f .(∆VDD − ∆VSS ) + k5f
(6)
where k1f and k2f are positive constants and their value
depend on the falling input transition, gate load, and parasitics.
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tf + ∆tf
CT SV
k1f =
+
2VDD .(1 + α)
2IDO
tf + ∆tf
CT SV
−
k2f =
2VDD .(1 + α)
2IDO
1 − vt
k5f = ∆tf . 0.5 −
1+α
f (R) = f (Ropen1 , ..., Ropenn )
where
The constants k1f , k2f and k5f are given by [20]:
(7)
(8)
(9)
Both HL and LH stage-path delay formulations once compared to the delay threshold, DT, assure that a transition
fault occurs due to physical and electrical effects. We further
exploit such mathematical formulation to introduce the effect
of resistive open TSV and derive its impact on stage-path
delay.
For each resistive open value, the stage-path delay can be
expressed by normal variables N (µdef , σdef ). Then the mean
(µdef ) and standard deviation (σdef ) of stage-path delay with
resistive open TSV can estimated using multivariate Taylorseries expansion [21] second-order approximation by:
n
X
∂ 2 f (R) 2
σ Ropeni
(11)
µDdef = f (R) + 0.5
2
∂Ropen
i
i=1
and
2
σD
=
def
PDF
μ nominal
(12)
D0 ∼ N (µD0 , σD0 )
(13)
Similarly, the stage-path delay obtained due to a resistive open
TSV, can be expressed as:
Ddef ∼ N (µDdef , σDdef )
(14)
Then, the statistical detection condition for resistive open TSV
causing transition faults can be stated as:
Ddef ∼ N (µDdef , σDdef ) ≥ D0 ∼ N (µD0 , σD0 )
(15)
We will utilize in the following section such comparison in
order to detect statistically the condition of transition faults
caused by a resistive open TSV.
III. P ROBABILITY OF D ETECTION
In this section, we explain the concept of deriving probability of detection, Pdet , for various resistive open values
utilizing the delay probability density functions. We exploit
joint probability density function f (D0 , Ddef ) to calculate the
probability to detect resistive open TSVs. The probability of
detection of resistive open TSV can be analytically estimated
via the area of the joint distributions by taking the double
integral as:
P det[Ddef ≥ D0 ] =
Z
µD0 +3σD0
Z
!
(µDdef +3σDdef )
f (D0 , Ddef )dDdef
µD0 −3σD0
dD0
D0
(16)
Ddef = f (R)
μ
2
n X
∂f (R)
σ 2 Ropeni
∂R
open
i
i=1
The distribution of the parameters can be quite wide as some
preliminary studies have shown [2]. The nominal distribution
function for stage-path delay can be expressed as:
C. Detecting Conditions for Resistive Open TSVs under Physical and Electrical Factors
During 3D ICs manufacturing test, detection of delay variations caused by resistive open TSVs can be very challenging.
The detectability of a defective TSV can be a function of the
size of the open (i.e. open resistivity values) and also due to
combinations of physical and electrical conditions from the
stacked circuit.
Definition: In general terms, delay variations can be represented in a normal distribution. A defect-free TSV has a
stage-path delay normal distribution D0 that can be expressed
as N(µD0 , σD0 ). Whereas, a path-delay containing resistive
open TSV also can be expressed in normal distribution Ddef
such as N(µDdef , σDdef ).
Figure 2 depicts delay distribution D0 for a non-defective
TSV represented by the nominal curve of delay versus probability density distribution (PDF) considering electrical and
physical factors. Such delay distribution would further vary
due to a defective TSV. Intuitively, delay variations Ddef
are greater than D0 due to the increased resistance, but
delay variations induced by resistive open TSVs may lead to
excessive delay or artificial delay speed-up due to physical
and electrical effects, which affects the detectability of such
defects. Since Ddef would further vary due to a defective TSV,
delay variations can be expressed as a function of resistive
open values (Ropen ), as in:
(10)
Delay
Threshold
Delay (ps)
Fig. 2. Delay distribution for a defect-free path delay as a function of physical
and electrical factors. µD0 , σD0 and delay threshold line can vary due to
selected path and design constraints. We assume that path delays passing the
delay threshold line are detectable.
The probability of detection, Pdet would vary as a function
of resistive open values (Ropen ). Strong Ropen values would
lead to large probability of detection. However, weak open (or
small Ropen ) would lead to small probability of detection.
Stage-path delay with resistive open TSV has delay variations great enough to be detected by conventional methods we
consider that Ddef > DT as a transition fault. We assume that
delay threshold, DT , as the detectable delay, thus Pdet = 1.
We further exploit our mathematical formulation of Pdet to
determine the TSV resistive open values that lead to small
delay defects. In the following subsections, we present three
cases of delay distributions with respect to joint probability
density function, Pdet .
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non-defective
3
0.1
0.08
0.06
0.04
0.02
1
2
3
Delay(s)
0.02
N(μdef,σdef)*10-11
defective
0.12
Probability Density
Probability Density Function
Bivariate Normal Distribution
0.14
0.015
0.01
0.005
0
3
2
2.5
Detectable
Region
2
1.5
Non-detectable
Region
3
1
N(μdef,σdef)*10-11
(a)
0
1
2
1
N(μ0,σ0)*10-11
1
1.5
2
2.5
3
N(μ0,σ0)*10-11
(b)
(c)
Fig. 3. Case I shows disjoint stage-path delay distributions. (a) Path delay distributions for a stage-path with a defect-free and defective TSV. (b) We observe
that their PDFs are disjoint (no overlap). (c) Contours plot from bivariate densities with resistive open TSVs shows the open resistivity is detectable (with
high probability of detection) as it is beyond the delay threshold line.
A. Case I: Disjoint Delay Distributions
In this case, we investigate probability density distributions
of path delays derived from a stage-path with a defect-free and
defective TSV. Figure 3a shows the two distributions which
are distinctively disjointed with respect to their mean and
standard deviations, µDdef , σDdef and µD0 , σD0 . For disjoint
delay distribution, we note that:
µDdef >> µD0
(17)
This case demonstrates that the defective TSV has a large
resistive open value for producing a delay distribution that
is disjointed from the defect-free path delay distribution. As
shown in Figure 3b, their joint density distribution is plotted
with respect to defect-free delays on x-axis, defective-delays
on y-axis and their joint densities on z-axis. The contour plot
from joint densities (Figure 3c) serves as the estimate for the
probability of detection. Delay threshold line splits the graph
in two to show the detectable and non-detectable regions.
The area of the contour plot beyond the delay threshold line
provides an estimate of the detection probability, Pdet , which
is a high probability.
B. Case II: Joint Delay Distributions
In this case, the delay distributions from defect-free and
defective TSV have mean and standard derivations that are
closer, as shown in Figure 4. Some of the delays values
obtained from defective TSV can be misinterpreted as delay
variations induced from physical and electrical factors such as
voltage drop. For joint distribution, we note that:
µDdef ≥ µD0 + 3σD0
(18)
This is also shown on their joint distribution, which is much
wider compared to case I and resides in the middle of the
graph. Similarly, the contour plot shows that more than half
its area resides below the delay threshold and these scenarios
can let defective TSVs go undetected. The area of the contour
beyond the delay threshold shows the detectable region, which
has less than 50% probability of detection.
C. Case III: Overlapped Delay Distribution
In this case, stage-path delays from defective and defectfree TSV have very similar distributions with a large overlap
between them as shown in Figure 5. For this case, we note
that:
µDdef − µD0 ≤ σD0
(19)
This demonstrates that the value of resistive open is small
and there are a lot of scenarios where defective TSV can go
undetected. Their joint bivariate densities show a distribution
that is spread closely over the nominal delays. Also, this is
shown from the contour plot, where most of the area is located
below the delay threshold line, thus resulting in very low
probability of detection.
3
non-defective
defective
0.1
0.08
0.06
0.04
0.02
1.2
0.02
0.015
0.01
0.005
0
3
3
2
1
1.4
1.6
1.8
Delay(s)
(a)
2
2.2
2.4
Detectable
Region
2.8
0.025
N(μdef,σdef)*10-11
0.12
Probability Density
Probability Density Function
Bivariate Normal Distribution
0.14
N(μdef,σdef)*10-11
0
(b)
1
2
N(μ0,σ0)*10-11
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
1
Non-detectable
Region
1.5
2
2.5
3
N(μ0,σ0)*10-11
(c)
Fig. 4. Case II shows the joint delay distributions. (a) Path delay distributions for a stage-path with a defect-free and defective TSV. (b) Their delay
distributions are partially joint. (c) Contour plot from bivariate densities passes the delay threshold line, thus, resulting less than 50% probability of detection.
!
!
3
non-defective
2.8
defective
0.1
0.08
0.06
0.04
0.02
1.2
1.4
1.6
1.8
2
2.2
2.4
0.03
N(μdef,σdef)*10-11
0.12
Probability Density
Probability Density Function
Bivariate Normal Distribution
0.14
0.02
0.01
3
2
3
1
N(μdef,σdef)*10-11
1
0
Delay(s)
(a)
2
Detectable
Region
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
N(μ0,σ0)*10-11
Non-detectable
Region
1.5
2
1
2.5
3
N(μ0,σ0)*10-11
(b)
(c)
Fig. 5. Case III shows overlapped stage-path delay distributions. (a) Path delay distributions for a stage-path with a defect-free and defective TSV.(b) Their
delay distributions are mostly overlapping. (c) Contour plot from bivariate densities shows that most of the area is out of detectability region, thus resulting
in a very low probability of detection.
IV. C ASE S TUDY
To illustrate the applicability and relevance of the proposed
probability metric, we use a sample circuit as shown in
Figure 6. The given sample circuit is converted into a 3D
circuit by introducing TSVs between gates to represent the
logic divided into two tiers. Please note that the sample circuit
is combinational for simplicity reasons and our metric is applicable to all types of circuits regardless the TSV distribution.
We utilize TSVs of 3µm radius and 15µm depth, which the
RLC parasitics have been characterized by [18]. We consider
TSV-to-TSV coupling which is derived based on the proximity
between TSVs with pitch of 50µm. We perform HSPICE
simulation on the sample circuit to capture the delay variations
with resistive open TSV. We measure the stage-path delay
between points A and B as shown in Figure 6. Additionally,
we consider electrical factors such as non-uniform power
supply voltages and ground bounce within 10% of VDD . The
circuit was synthesized using 65nm Predictive Technology
Model (PTM) [22] library and Synopsys Tetramax was utilized
to generate the input vectors for sensitizing the path with
the TSV. The applied input vectors for rising and falling
transitions are (V1 ,V2 )=(0011,1100) and (V1 ,V2 )=(0001,1111),
respectively.
Additionally, we utilize MATLAB to perform the mathematical computations of our proposed formulas. Our objective is to
compare the results obtained from our mathematical formulas
versus to the simulation results obtained from HSPICE. The
experiment is performed assuming one of the TSV is defective
as shown in Figure 6. Initially, we perform HSPICE simulations and measure stage-path delay as a function of various
resistive open values or defect sizes. From the mathematical
formulations, we can obtain the mean and standard deviation
values for various resistive open values as shown in Figure 7. It
is important to note that stage-delay distributions for defective
TSVs experience a significant increase in their means and
sigmas with defect size (Ropen ). In Figure 8a, we show the
stage-path delay ratio obtained from defective TSV of various
sizes versus nominal delay obtained from HSPICE simulation.
In Figure 8b, we show the probability of detection, Pdet for
various resistive open sizes obtained from our mathematical
formulations. From Figure 8a, we note that stage-path delays
passing the delay threshold line with condition, µdef ≥DT
occurs around resistance of 50kΩ, or Rf ailure =50kΩ. This
is also defined as CASE I in our analysis. Rf ailure is also
correctly estimated using our mathematical formulas as shown
in Figure 8b for Pdet = 1. Similarly, we estimate the detectable resistance, Rdetectable when probability of detection,
Pdet = 0.5, which occurs around Rdetectable = 36kΩ. This is
defined as CASE II from our analysis. HSPICE simulation
also confirm such Rdectable value when the condition of
µdef = µD0 + 3σD0 is satisfied also as shown in Figure 8a.
For CASE III, we identify the region of resistance open values
less than Rdetectable . TABLE I summarizes the resistance
open values based on the computed probabilities of detection.
Figure 9 shows the joint density distribution and contour plot
for the case of Pdet = 0.5, which strongly confirms our derived
results by 99.2% in accuracy. Half of the contour plot resides
inside the non-detectable region bounded by delay threshold
lines.
A
B
j1
j2
D
TSV2
Cc
C
j4
j3
O1
TSV1
Point A Faulty TSV Point B
Fig. 6. Sample circuit used as a case study for computing probability of
detection.
TABLE I
P ROBABILITY OF D ETECTION , Pdet FOR RANGES OF RESISTIVE OPEN ,
Ropen VALUES .
Ropen values
Ropen ≤ 36kΩ
Ropen = Rdetectable = 36kΩ
36kΩ < Ropen < 50kΩ
Ropen ≥ 50kΩ
Pdet
≤ 50%
50%
50% < Pdet < 100%
100%
V. C ONCLUSION
This work proposes a probability based metric to detect
resistive opens TSVs. This metric aims to derive a relationship
!
!
Resisitive Open (Ω)
(a)
N(μdef,σdef) ps
Resisitive Open (Ω)
(b)
Probability of Detection
Rfailure
Rdetectable
Delay Ratio
Fig. 7. Given the measured delay from HSPICE simulations we obtain
(a) µdef /µ0 and (b) σdef /σ0 for various resistive open values.
10k
Resisitive Open (Ω)
(a)
20k
Rdetectable
Rfailure
30k
50k
40k
60k
Resisitive Open (Ω)
(b)
Fig. 8. (a) Stage-path delay ratio of defective TSVs with nominal delay
obtained from HSPICE simulations, and (b) probability of detection, Pdet
for various resistive open values. We identify Rdetectable = 36kΩ when
Pdet = 0.5 and Rf ailure = 50kΩ.
between defect size and detectability screening resistive open
values and associates a probability of detection to them.
This allows to sort resistive opens in ranges of detectability
i.e. detectable and non-detectable regions. Our probability of
detection metric is based on the joint density distributions of
the defect-free and defective stage-path delays for capturing
transition faults. Our proposed probability of detection metric
computes with high accuracy the detectable and non-detectable
regions for various resistive opens and the results match
well HSPICE results our simulations provide 99.2% accuracy.
As future work, we aim to exploit the probability metric
to develop a TSV-aware detection method while taking into
account the physical and electrical factors on 3D ICs.
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Bivariate Normal Distribution
Detectable
Region
Delay Threshold
Line
Non-detectable
Region
(a)
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(b)
Fig. 9.
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