Comparators
Combinational Design
Comparators
• Equality and Magnitude Comparators
– CSE 171 (Designed using CUPL)
• TTL Comparators
• Comparator Networks
• Cascading 1-bit Comparators
– Design using VHDL
Equality Comparator
XNOR
X
Y
Z
Z = !(X $ Y)
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
4-Bit Equality Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
FIELD A = [A0..3];
FIELD B = [B0..3];
FIELD C = [C0..3];
A_EQ_B
4-bit Equality Detector
A[3..0]
B[3..0]
Equality
Detector
A_EQ_B
4-bit Magnitude Comparator
A[3..0]
B[3..0]
Magnitude
Detector
A_LT_B
A_EQ_B
A_GT_B
Magnitude Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
A_EQ_B
How can we find A_GT_B?
How many rows would a truth table have?
28 = 256!
Magnitude Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
If A = 1001 and
B = 0111
is A > B?
Why?
A_EQ_B
Find A_GT_B
Because A3 > B3
i.e. A3 & !B3 = 1
Therefore, one term in the
logic equation for A_GT_B is
A3 & !B3
Magnitude Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
A_EQ_B
If A = 1101 and
B = 1011
is A > B?
Why?
A_GT_B = A3 & !B3
# …..
Because A3 = B3 and
A2 > B2
i.e. C3 = 1 and
A2 & !B2 = 1
Therefore, the next term in the
logic equation for A_GT_B is
C3 & A2 & !B2
Magnitude Comparator
A0
A1
A2
A3
B0
B1
B2
B3
C0
C1
A_EQ_B
C2
C3
If A = 1010 and
B = 1001
is A > B?
Why?
A_GT_B = A3 & !B3
# C3 & A2 & !B2
# …..
Because A3 = B3 and
A2 = B2 and
A1 > B1
i.e. C3 = 1 and C2 = 1 and
A1 & !B1 = 1
Therefore, the next term in the
logic equation for A_GT_B is
C3 & C2 & A1 & !B1
Magnitude Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
A_EQ_B
If A = 1011 and
B = 1010
is A > B?
Why?
A_GT_B = A3 & !B3
# C3 & A2 & !B2
# C3 & C2 & A1 & !B1
# …..
Because A3 = B3 and
A2 = B2 and
A1 = B1 and
A0 > B0
i.e. C3 = 1 and C2 = 1 and
C1 = 1 and A0 & !B0 = 1
Therefore, the last term in the
logic equation for A_GT_B is
C3 & C2 & C1 & A0 & !B0
Magnitude Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
A_EQ_B
A_GT_B = A3 & !B3
# C3 & A2 & !B2
# C3 & C2 & A1 & !B1
# C3 & C2 & C1 & A0 & !B0
Magnitude Comparator
A0
A1
A2
A3
B0
B1
C0
C1
B2
C2
B3
C3
A_EQ_B
Find A_LT_B
A_LT_B = !A3 & B3
# C3 & !A2 & B2
# C3 & C2 & !A1 & B1
# C3 & C2 & C1 & !A0 & B0
Comparators
• Equality and Magnitude Comparators
– CSE 171 (Designed using CUPL)
• TTL Comparators
• Comparator Networks
• Cascading 1-bit Comparators
– Design using VHDL - Lab 3
TTL Comparators
1
2
3
4
5
B3
A<Bin
A=Bin
A>Bin
A>Bout
6 A=Bout
7 A<Bout
8 GND
Vcc16
A3 15
B2 14
A2 13
A1 12
B1 11
A0 10
B0 9
74LS85
1
2
3
4
5
6
7
8
9
10
P>Q
P0
Q0
P1
Q1
P2
Q2
P3
Q3
GND
Vcc 20
P=Q19
Q7 18
P7 17
Q6 16
15
P6
Q5 14
P5 13
Q4 12
P4 11
74LS682
Cascading two 74LS85s
A3 A2 A1 A0
A7 A6 A5 A4
A<B
+5V
B3 B2 B1 B0
A=B
A>B
B7 B6 B5 B4
Comparators
• Equality and Magnitude Comparators
– CSE 171 (Designed using CUPL)
• TTL Comparators
• Comparator Networks
• Cascading 1-bit Comparators
– Design using VHDL - Lab 3
1-Bit Magnitude Comparator
x
Gout
Eout
Lout
y
1 -bit
comparator
Gin
Lin
The variable Eout is 1 if A = B and Gin = 0 and Lin = 0.
The variable Gout is 1 if A > B or if A = B and Gin = 1.
The variable Lout is 1 if A < B or if A = B and Lin = 1.
4-Bit Magnitude Comparator
x3
gt
eq
lt
y3
G4
x2
x1
y1
G2
G3
1-bit comp
L4
y2
1-bit comp
L3
y0
G1
1-bit comp
L2
X
1101
1110
1011
0101
1010
x0
Y
0110
1011
1011
0111
1011
G0
1-bit comp
L1
gt = 1
eq = 1
lt = 1
L0
Gin=0
Lin=0
Tree comparator network
Comparators
• Equality and Magnitude Comparators
– CSE 171 (Designed using CUPL)
• TTL Comparators
• Comparator Networks
• Comparator Design using VHDL
gt
x(3:0)
y(3:0)
magcomp
eq
lt
Lab 3c
x
Gout
Eout
Lout
y
Gin
comp1bit
Lin
x3
gt
eq
lt
y3
G4
x2
x1
1-bit comp
L3
y1
G2
G3
1-bit comp
L4
y2
x0
y0
G1
1-bit comp
L2
comp4bit
G0
1-bit comp
L1
L0
Gin=0
Lin=0
x3
gt
eq
lt
y3
G4
x2
U3
x1
1-bit comp
L3
y1
G2
G3
1-bit comp
L4
y2
U2
x0
G1
1-bit comp
L2
y0
U1
G0
1-bit comp
L1
U0
Fill in the port maps
L0
Gin=0
Lin=0