A-1
Appendix A: Digital Logic
Principles of Computer Architecture
Miles Murdocca and Vincent Heuring
Appendix A: Digital Logic
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-2
Appendix A: Digital Logic
Chapter Contents
A.1 Introduction
A.2 Combinational Logic
A.3 Truth Tables
A.4 Logic Gates
A.5 Properties of Boolean Algebra
A.6 The Sum-of-Products Form, and Logic Diagrams
A.7 The Product-of-Sums Form
A.8 Positive vs. Negative Logic
A.9 The Data Sheet
A.10 Digital Components
A.11 Sequential Logic
A.12 Design of Finite State Machines
A.13 Mealy vs. Moore Machines
A.14 Registers
A.15 Counters
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-3
Appendix A: Digital Logic
Some Definitions
• Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an
adder.
• Sequential logic: a circuit in which decisions are made based on
combinations of the current inputs as well as the past history of
inputs. e.g. a memory unit.
• Finite state machine: a circuit which has an internal state, and
whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-4
Appendix A: Digital Logic
The Combinational Logic Unit
• Translates a set of inputs into a set of outputs according to one or
more mapping functions.
• Inputs and outputs for a CLU normally have two distinct (binary)
values: high and low, 1 and 0, 0 and 1, or 5 V and 0 V for example.
• The outputs of a CLU are strictly functions of the inputs, and the
outputs are updated immediately after the inputs change. A set of
inputs i0 – in are presented to the CLU, which produces a set of
outputs according to mapping functions f0 – fm.
i0
i1
in
Principles of Computer Architecture by M. Murdocca and V. Heuring
...
...
Combinational
logic unit
f0 (i0, i1)
f1 (i1, i3, i4)
fm(i9, in)
© 1999 M. Murdocca and V. Heuring
A-5
Appendix A: Digital Logic
A Truth Table
• Developed in 1854 by George Boole.
• Further developed by Claude Shannon (Bell Labs).
• Outputs are computed for all possible input combinations (how
many input combinations are there?)
• Consider a room with two light switches. How must they work?
Inputs
GND
Light Z
Output
A
B
Z
0
0
1
1
0
1
0
1
0
1
1
0
“Hot”
Switch A
Principles of Computer Architecture by M. Murdocca and V. Heuring
Switch B
© 1999 M. Murdocca and V. Heuring
A-6
Appendix A: Digital Logic
Alternate Assignment of Outputs to
Switch Settings
• We can make the assignment of output values to input combinations any way that we want to achieve the desired input-output behavior.
Inputs Output
A B
Z
0
1
0
1
1
0
0
1
0
0
1
1
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-7
Appendix A: Digital Logic
Truth Tables Showing All Possible
Functions of Two Binary Variables
Inputs
• The more frequently used functions have names:
AND, XOR, OR,
NOR, XOR, and
NAND. (Always
use upper case
spelling.)
Outputs
A
B
False AND
AB
A
AB
B
XOR
OR
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Inputs
Outputs
B
A+B
A
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
A
B
0
0
1
0
1
1
1
Principles of Computer Architecture by M. Murdocca and V. Heuring
NOR XNOR
A + B NAND True
© 1999 M. Murdocca and V. Heuring
A-8
Appendix A: Digital Logic
Logic Gates and Their Symbols
• Logic symbols
shown for AND, OR,
buffer, and NOT
Boolean functions.
• Note the use of the
“inversion bubble.”
F
0
0
0
1
B
0
1
0
1
A
0
0
1
1
A
B
F=AB
A
B
F=A+B
AND
• (Be careful about
the “nose” of the
gate when drawing
AND vs. OR.)
A
0
1
A
0
1
F=A
Buffer
Principles of Computer Architecture by M. Murdocca and V. Heuring
OR
F
0
1
A
F
0
1
1
1
B
0
1
0
1
A
0
0
1
1
A
F
1
0
F= A
NOT (Inverter)
© 1999 M. Murdocca and V. Heuring
A-9
Appendix A: Digital Logic
Logic Gates and their Symbols (cont’)
A
0
0
1
1
B
0
1
0
1
F
1
1
1
0
A
B
A
0
0
1
1
F= A B
A
B
A
B
B
0
1
0
1
F
1
0
0
0
F= A + B
NAND
A
0
0
1
1
B
0
1
0
1
NOR
F
0
1
1
0
F=A⊕B
Exclusive-OR (XOR)
Principles of Computer Architecture by M. Murdocca and V. Heuring
A
0
0
1
1
A
B
B
0
1
0
1
F
1
0
0
1
F = A ⊕. B
Exclusive-NOR (XNOR)
© 1999 M. Murdocca and V. Heuring
A-10
Appendix A: Digital Logic
Variations of Logic Gate Symbols
A
B
C
A
B
F = ABC
(a)
F = A+ B
(b)
A
A+ B
A+ B
B
(c)
(a) 3 inputs
(b) A Negated input
Principles of Computer Architecture by M. Murdocca and V. Heuring
(c) Complementary outputs
© 1999 M. Murdocca and V. Heuring
A-11
Appendix A: Digital Logic
Transistor Operation of Inverter
OUTPUT VOLTAGE vs. INPUT VOLTAGE
4.0
VCC = +5 V
A
RL
VCC
Vout
A
Collector
Emitter
Base
Vin
A
A
V O –Output Voltage–V
VCC
3.5
V CC = 5 V
3.0
R L = 400 Ω
2.5
2.0
1.5
1.0
0.5
GND = 0 V
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V I–Input Voltage–V
(a)
(b)
(c)
(d)
(a) Inverter showing power terminals; (b) transistor symbol; (c) transistor configured as an inverter; (d) inverter transfer function.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-12
Appendix A: Digital Logic
Assignments of 0 and 1 to Voltages
+5 V
+5 V
Logical 1
2.4 V
Logical 1
2.0 V
Forbidden Range
Forbidden Range
0.8 V
0.4 V
0V
Logical 0
(a)
Principles of Computer Architecture by M. Murdocca and V. Heuring
Logical 0
0V
(b)
© 1999 M. Murdocca and V. Heuring
A-13
Appendix A: Digital Logic
Transistor Operation of Logic Gates
VCC
Vout
(a) NAND; (b) NOR
VCC
AB
V1
A
Vout
A+B
V2
B
V1
A
(a)
Principles of Computer Architecture by M. Murdocca and V. Heuring
V2
B
(b)
© 1999 M. Murdocca and V. Heuring
A-14
Appendix A: Digital Logic
Tri-State Buffers
• Outputs can be 0, 1, or “electrically disconnected.”
C
0
0
1
1
A
C
A
0
1
0
1
F
ø
ø
0
1
F=AC
or
F=ø
Tri-state buffer
Principles of Computer Architecture by M. Murdocca and V. Heuring
C
0
0
1
1
A
C
A
0
1
0
1
F
0
1
ø
ø
F = AC
or
F=ø
Tri-state buffer, inverted control
© 1999 M. Murdocca and V. Heuring
A-15
Appendix A: Digital Logic
Properties of Boolean Algebra
Theorems
• Principle of
duality: The
dual of a
Boolean
function is
obtained by
replacing
AND with OR
and OR with
AND, 1s with
0s, and 0s
with 1s.
Postulates
Relationship
Dual
Property
AB = BA
A+B = B+A
Commutative
A (B + C) = A B + A C
A + B C = (A + B) (A + C)
Distributive
1A=A
0+A = A
Identity
AA = 0
A+A = 1
Complement
0A = 0
1+A = 1
Zero and one theorems
AA =A
A+A = A
Idempotence
A (B C) = (A B) C
A + (B + C) = (A + B) + C
Associative
A = A
Involution
AB= A+ B
A+ B = A B
DeMorgan’s Theorem
AB + AC + BC
( A + B )( A + C )( B +C)
Consensus Theorem
= AB + AC
A (A + B) = A
Principles of Computer Architecture by M. Murdocca and V. Heuring
= ( A + B)(A + C )
A+AB = A
Absorption Theorem
© 1999 M. Murdocca and V. Heuring
A-16
Appendix A: Digital Logic
DeMorgan’s Theorem
A B
0
0
1
1
0
1
0
1
AB = A + B
1
1
1
0
DeMorgan’s theorem:
A
B
F=A+B
Principles of Computer Architecture by M. Murdocca and V. Heuring
A + B = AB
1
0
0
0
1
1
1
0
1
0
0
0
A+B = A+B = AB
A
B
F=AB
© 1999 M. Murdocca and V. Heuring
A-17
Appendix A: Digital Logic
All-NAND Implementation of OR
• NAND alone implements all other Boolean logic gates.
A
A
B
A+ B
A+B
B
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-18
Appendix A: Digital Logic
Sum-of-Products Form: The Majority
Function
• The SOP form for the 3-input majority function is:
M = ABC + ABC + ABC + ABC = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7).
• Each of the 2n terms are called minterms, ranging from 0 to 2n - 1.
• Note relationship between minterm number and boolean value.
Minterm
Index
0
1
2
3
4
5
6
7
A B C
F
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
Principles of Computer Architecture by M. Murdocca and V. Heuring
0 0
0-side
1-side
A balance tips to the left or
right depending on whether
there are more 0’s or 1’s.
© 1999 M. Murdocca and V. Heuring
A-19
Appendix A: Digital Logic
AND-OR Implementation of Majority
A
B
C
• Gate count is
8, gate input
count is 19.
ABC
ABC
F
AB C
ABC
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-20
Appendix A: Digital Logic
Notation Used at Circuit Intersections
Connection
No connection
Connection
No connection
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-21
Appendix A: Digital Logic
OR-AND Implementation of Majority
A
B
C
A+ B+ C
A+ B+C
F
A+ B+ C
A+ B+ C
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-22
Appendix A: Digital Logic
Positive/Negative Logic Assignments
• Positive logic: logic 1 is represented by high voltage; logic 0 is
represented by low voltage.
• Negative logic: logic 0 is represented by high voltage; logic 1 is
represented by low voltage.
Gate Logic: Positive vs. Negative Logic
Normal Convention: Postive Logic/Active High
Low Voltage = 0; High Voltage = 1
Alternative Convention sometimes used: Negative Logic/Active Low
F
Voltage Truth T able
A
low
low
high
high
B
low
high
low
high
F
low
low
low
high
Positive Logic
A
0
0
1
1
Behavior in terms
of Electrical Levels
Principles of Computer Architecture by M. Murdocca and V. Heuring
B
0
1
0
1
Negative Logic
F
0
0
0
1
A
1
1
0
0
B
1
0
1
0
F
1
1
1
0
Two Alternative Interpretations
Positive Logic AND
Negative Logic OR
Dual Operations
© 1999 M. Murdocca and V. Heuring
A-23
Appendix A: Digital Logic
Positive/Negative Logic Assignments
(Cont’)
Positive Logic Levels
Voltage Levels
A
low
low
high
high
A
B
low
high
low
high
F
low
low
low
high
Physical
AND gate
B
A
0
0
1
1
F
A
B
B
low
high
low
high
A
1
1
0
0
F=AB
A
0
0
1
1
F
A
B
Principles of Computer Architecture by M. Murdocca and V. Heuring
B
0
1
0
1
F
1
1
1
0
F=A+B
Negative Logic Levels
F
1
1
1
0
A
1
1
0
0
F= A B
B
1
0
1
0
A
B
Positive Logic Levels
F
high
high
high
low
Physical
NAND gate
F
0
0
0
1
A
B
Voltage Levels
A
low
low
high
high
B
0
1
0
1
Negative Logic Levels
A
B
B
1
0
1
0
F
0
0
0
1
F = A + B
© 1999 M. Murdocca and V. Heuring
A-24
Appendix A: Digital Logic
Bubble Matching
Positive logic x0
Positive
Logic
Positive logic x1
Negative logic x0
Negative
Logic
Negative logic x1
(a)
(b)
x0 Bubble match
Negative logic x0
Negative logic x1
Negative logic
Negative
Logic
Negative
Logic
Negative logic
Bubble mismatch
(c)
Principles of Computer Architecture by M. Murdocca and V. Heuring
x1 Bubble match
(d)
© 1999 M. Murdocca and V. Heuring
A-25
Appendix A: Digital Logic
SN7400 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
description
These devices contain four independent
2-input NAND gates.
Example
Data Sheet
function table (each gate)
INPUTS
A
B
H
L
X
1A
1B
1Y
2A
2B
2Y
GND
L
H
L
V CC
4 kΩ
package (top view)
OUTPUT
Y
H
X
schematic (each gate)
H
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
130 Ω
1.6 kΩ
A
B
Y
absolute maximum ratings
• Simplified data
sheet for 7400
NAND gate,
adapted from Texas
Instruments TTL
Databook [Texas
Instruments, 1988]
Supply voltage, VCC
7V
Input voltage:
5.5 V
Operating free-air temperature range:
0 ˚C to 70 ˚C
Storage temperature range
– 65 ˚ C to 150 ˚C
1 kΩ
GND
recommended operating conditions
MIN NOM MAX
logic diagram (positive logic)
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Y = AB
V CC
Supply voltage
V IH
High-level input voltage
V IL
Low-level input voltage
IOH
High-level output current
4.75
5
5.25
2
IOL
Low-level output current
TA
Operating free-air temperature
UNIT
V
V
0.8
V
– 0.4
mA
0
16
mA
70
˚C
electrical characteristics over recommended operating free-air temperature range
MIN
V OH
V CC = MIN, V IL = 0.8 V, IOH = – 0.4 mA
V OL
V CC = MIN, V IH = 2 V, IOL = 16 mA
IIH
V CC = MAX, V I = 2.4 V
IIL
V CC = MAX, V I = 0.4 V
ICCH
V CC = MAX, V I = 0 V
V CC = MAX, V I = 4.5 V
ICCL
2.4
TYP MAX
UNIT
3.4
V
0.2
0.4
V
40
µA
– 1.6
mA
4
8
mA
12
22
mA
switching characteristics, V CC = 5 V, T A = 25˚ C
PARAMETER
tPLH
tPHL
Principles of Computer Architecture by M. Murdocca and V. Heuring
FROM (input)
A or B
TO (output)
Y
TEST CONDITIONS
R L = 400 Ω
C L = 15 pF
MIN
TYP MAX
UNIT
11
22
ns
7
15
ns
© 1999 M. Murdocca and V. Heuring
A-26
Appendix A: Digital Logic
Digital Components
• High level digital circuit designs are normally created using collections of logic gates referred to as components, rather than using individual logic gates.
• Levels of integration (numbers of gates) in an integrated circuit
(IC) can roughly be considered as:
• Small scale integration (SSI): 10-100 gates.
• Medium scale integration (MSI): 100 to 1000 gates.
• Large scale integration (LSI): 1000-10,000 logic gates.
• Very large scale integration (VLSI): 10,000-upward logic
gates.
• These levels are approximate, but the distinctions are useful
in comparing the relative complexity of circuits.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-27
Appendix A: Digital Logic
Data Inputs
Multiplexer
D0
D1
00
01
D2
D3
10
11
F
A B
F
0
1
0
1
D0
D1
D2
D3
0
0
1
1
A B
Control Inputs
F = A B D0 + A B D1 + A B D2 + A B D3
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-28
Appendix A: Digital Logic
AND-OR Implementation of MUX
D0
D1
F
D2
D3
A
B
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-29
Appendix A: Digital Logic
MUX Implementation of Majority
• Principle: Use the 3 MUX control inputs to select (one at a time)
the 8 data inputs.
A B C
M
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
000
001
0
1
010
011
0
1
100
101
1
1
110
111
F
A B C
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-30
Appendix A: Digital Logic
4-to-1 MUX Implements 3-Var Function
• Principle: Use the A and B inputs to select a pair of minterms.
The value applied to the MUX data input is selected from {0, 1,
C, C} to achieve the desired behavior of the minterm pair.
A B C
F
0
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
00
1
C
01
10
C
11
F
C
C
Principles of Computer Architecture by M. Murdocca and V. Heuring
A B
© 1999 M. Murdocca and V. Heuring
A-31
Appendix A: Digital Logic
Demultiplexer
D
00
F0
01
10
F1
F2
11
F3
A B
F0 = D A B
F2 = D A B
F1 = D A B
F3 = D A B
Principles of Computer Architecture by M. Murdocca and V. Heuring
D A B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F0 F1 F2 F3
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
© 1999 M. Murdocca and V. Heuring
A-32
Appendix A: Digital Logic
Gate-Level Implementation of DEMUX
F0
F1
D
F2
F3
A
B
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-33
Appendix A: Digital Logic
Decoder
Enable = 1
A B
A
B
Enable
00
01
10
11
D0
D1
D2
D3
D0 = A B
0
0
1
1
0
1
0
1
D1 = A B
Principles of Computer Architecture by M. Murdocca and V. Heuring
Enable = 0
D 0 D1 D2 D3
A B
1
0
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
1
D2 = A B
0
1
0
1
D0 D 1 D 2 D 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3 = A B
© 1999 M. Murdocca and V. Heuring
A-34
Appendix A: Digital Logic
Gate-Level Implementation of Decoder
D0
D1
A
B
D2
D3
Enable
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-35
Appendix A: Digital Logic
Decoder Implementation of Majority
Function
• Note that the enable input is not
always present.
We use it when
discussing decoders for
memory.
000
001
A
B
C
010
011
100
101
M
110
111
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-36
Appendix A: Digital Logic
Priority Encoder
•
•
•
•
An encoder translates a set of inputs into a binary encoding.
Can be thought of as the converse of a decoder.
A priority encoder imposes an order on the inputs.
Ai has a higher priority than Ai+1
A0
A1
00
01
A2
A3
10
11
F0
F1
F0 = A0 A1 A3 + A0 A1 A2
F1 = A0 A2 A3 + A0 A1
Principles of Computer Architecture by M. Murdocca and V. Heuring
A0 A1 A2 A3
F0 F1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
© 1999 M. Murdocca and V. Heuring
A-37
Appendix A: Digital Logic
AND-OR Implementation of Priority
Encoder
A0
A1
F0
A2
A3
Principles of Computer Architecture by M. Murdocca and V. Heuring
F1
© 1999 M. Murdocca and V. Heuring
A-38
A
B
Appendix A: Digital Logic
C
Programmable
Logic Array
OR matrix
• A PLA is a
customizable AND
matrix followed by
a customizable
OR matrix.
• Black box view of
PLA:
A
B
C
PLA
F0
F1
Fuses
AND matrix
F0
Principles of Computer Architecture by M. Murdocca and V. Heuring
F1
© 1999 M. Murdocca and V. Heuring
A-39
A
Simplified
Representation
of PLA
Implementation
of Majority
Function
B
C
Appendix A: Digital Logic
ABC
AB C
ABC
ABC
F0
F1
(Majority) (Unused)
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-40
Appendix A: Digital Logic
Example: Ripple-Carry Addition
Carry In
Operand A
Operand B
0
0
0
0
1
1
1
1
0
+ 0
0
+ 1
1
+ 0
1
+ 1
0
+ 0
0
+ 1
1
+ 0
1
+ 1
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1
Carry Sum
Out
Example:
Carry
Operand A
1 0 0 0
0 1 0 0
Operand B
Sum
+ 0 1 1 0
Principles of Computer Architecture by M. Murdocca and V. Heuring
1 0 1 0
© 1999 M. Murdocca and V. Heuring
A-41
Appendix A: Digital Logic
Full Adder
Ai Bi Ci
Si
Ci+1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Principles of Computer Architecture by M. Murdocca and V. Heuring
Bi Ai
Ci
Full
adder
Ci+1
Si
© 1999 M. Murdocca and V. Heuring
A-42
Appendix A: Digital Logic
Four-Bit Ripple-Carry Adder
• Four full adders connected in a ripple-carry chain form a four-bit
ripple-carry adder.
b3 a3
c3
b2 a2
c2
b1 a1
c1
b0 a0
Full
adder
Full
adder
Full
adder
Full
adder
s3
s2
s1
s0
c0
0
c4
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-43
Appendix A: Digital Logic
A
B
Cin
PLA Realization
of Full Adder
Sum
Principles of Computer Architecture by M. Murdocca and V. Heuring
Cout
© 1999 M. Murdocca and V. Heuring
A-44
Appendix A: Digital Logic
Sequential Logic
• The combinational logic circuits we have been studying so far
have no memory. The outputs always follow the inputs.
• There is a need for circuits with memory, which behave differently depending upon their previous state.
• An example is a vending machine, which must remember how
many and what kinds of coins have been inserted. The machine
should behave according to not only the current coin inserted,
but also upon how many and what kinds of coins have been inserted previously.
• These are referred to as finite state machines, because they can
have at most a finite number of states.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-45
Appendix A: Digital Logic
Classical Model of a Finite State
Machine
ik
...
Inputs
io
...
Combinational
logic unit
fo
Outputs
fm
...
...
State bits
Q0 D0
s0
...
• An FSM is composed of a combinational logic
unit and delay
elements (called
flip-flops) in a
feedback path,
which maintains
state information.
Qn Dn
sn
Synchronization
signal
Delay elements (one per state bit)
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-46
Appendix A: Digital Logic
NOR Gate with Lumped Delay
A
1
0
A
B
∆τ
B
1
0
A+ B
1
A+ B
0
∆τ
Timing Behavior
• The delay between input and output (which is lumped at the output for the purpose of analysis) is at the basis of the functioning
of an important memory element, the flip-flop.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-47
Appendix A: Digital Logic
S-R Flip-Flop
• The S-R flip-flop is an active high (positive logic) device.
Qt St Rt
S
R
Q
Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Qi+1
S
0
0
1
(disallowed)
1
0
1
(disallowed)
R
Q
Q
∆τ
∆τ
2∆τ
2∆τ
Timing Behavior
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-48
Appendix A: Digital Logic
NAND Implementation of S-R Flip-Flop
S
R
Q
Q
S
R
Principles of Computer Architecture by M. Murdocca and V. Heuring
Q
Q
S
R
Q
Q
R
S
Q
Q
© 1999 M. Murdocca and V. Heuring
A-49
Appendix A: Digital Logic
A Hazard
A
B
C
AB
S
C
Q
B
A
Glitch caused by
a hazard
S
∆τ
R
AB
R
Q
Q
Q
∆τ
2∆τ
Timing Behavior
• It is desirable to be able to “turn off” the flip-flop so it does not
respond to such hazards.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-50
Appendix A: Digital Logic
Amplitude
A Clock Waveform: The Clock Paces
the System
Time
Cycle time = 25ns
• In a positive logic system, the “action” happens when the clock is
high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs settle at the correct value
when the clock next goes high.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-51
Appendix A: Digital Logic
Scientific Prefixes
• For computer memory, 1K = 210 = 1024. For everything else, like
clock speeds, 1K = 1000, and likewise for 1M, 1G, etc.
Prefix Abbrev. Quantity
Prefix Abbrev. Quantity
milli
m
10–3
Kilo
K
103
micro
µ
10–6
Mega
M
106
nano
n
10–9
Giga
G
109
pico
p
10–12
Tera
T
1012
femto
f
10–15
Peta
P
1015
atto
a
10–18
Exa
E
1018
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-52
Appendix A: Digital Logic
Clocked S-R Flip-Flop
S
R
S
Q
CLK
CLK
Q
Q
R
Q
∆τ
2∆τ
Timing Behavior
• The clock signal, CLK, enables the S and R inputs to the flip-flop.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-53
Appendix A: Digital Logic
Clocked D Flip-Flop
• The clocked D flip-flop, sometimes called a latch, has a potential
problem: If D changes while the clock is high, the output will also
change. The Master-Slave flip-flop (next slide) addresses this problem.
D
D
Q
CLK
CLK
Circuit
Q
Q
Q
∆τ
∆τ
D Q
Symbol
C Q
Principles of Computer Architecture by M. Murdocca and V. Heuring
2∆τ
2∆τ
Timing Behavior
© 1999 M. Murdocca and V. Heuring
A-54
Appendix A: Digital Logic
Master-Slave Flip-Flop
• The rising edge of the clock loads new data into the master,
while the slave continues to hold previous data. The falling
edge of the clock loads the new master data into the slave.
D
Master
Slave
D
D QM
D QS
CLK
Circuit
CLK
C QS
C
QM
QS
D Q
QS
Q
∆τ
∆τ
Symbol
3∆τ 2∆τ
2∆τ
2∆τ
Timing Behavior
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-55
Appendix A: Digital Logic
Clocked J-K Flip-Flop
• The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-R
flip-flop, because Q enables J while Q’ disables K, and vice-versa.
• However, there is still a problem. If J goes momentarily to 1 and
then back to 0 while the flip-flop is active and in the reset state, the
flip-flop will “catch” the 1. This is referred to as “1’s catching.”
• The J-K Master-Slave flip-flop (next slide) addresses this problem.
J
Q
J Q
CLK
Q
K
Circuit
Principles of Computer Architecture by M. Murdocca and V. Heuring
K Q
Symbol
© 1999 M. Murdocca and V. Heuring
A-56
Appendix A: Digital Logic
Master-Slave J-K Flip-Flop
J
Q
J Q
CLK
Q
K
Circuit
Principles of Computer Architecture by M. Murdocca and V. Heuring
K Q
Symbol
© 1999 M. Murdocca and V. Heuring
A-57
Appendix A: Digital Logic
Clocked T Flip-Flop
• The presence of a constant 1 at J and K means that the flip-flop
will change its state from 0 to 1 or 1 to 0 each time it is clocked
by the T (Toggle) input.
1
J
Q
T
Q
T
K Q
Circuit
Principles of Computer Architecture by M. Murdocca and V. Heuring
Q
Symbol
© 1999 M. Murdocca and V. Heuring
A-58
Appendix A: Digital Logic
Negative Edge-Triggered D Flip-Flop
• When the clock is
high, the two input
latches output 0, so
the Main latch remains in its previous
state, regardless of
changes in D.
• When the clock goes
high-to-low, values in
the two input latches
will affect the state of
the Main latch.
• While the clock is
low, D cannot affect
the Main latch.
Stores D
R
Q
CLK
Q
S
Main latch
D
Principles of Computer Architecture by M. Murdocca and V. Heuring
Stores D
© 1999 M. Murdocca and V. Heuring
A-59
Appendix A: Digital Logic
Example: Modulo-4 Counter
• Counter has a clock input (CLK) and a RESET input.
• Counter has two output lines, which take on values of 00, 01, 10,
and 11 on subsequent clock cycles.
Time (t) 4 3 2 1 0
00001
RESET
q0
3-bit
q1
Synchronous
s0
Counter
s1
4 3 2 1 0 Time (t)
01100
01010
D Q
D Q
Q
s1
CLK
Principles of Computer Architecture by M. Murdocca and V. Heuring
s0
Q
© 1999 M. Murdocca and V. Heuring
A-60
Appendix A: Digital Logic
Output 00
state
State
Transition
Diagram for
Mod-4
Counter
Output 01
state
0/01
RESET
A
1/00
B
q1 q0
1/00
1/00
0/10
C
Output 10
state
Principles of Computer Architecture by M. Murdocca and V. Heuring
0/00
1/00
0/11
D
Output 11
state
© 1999 M. Murdocca and V. Heuring
A-61
Appendix A: Digital Logic
State Table for Mod-4 Counter
RESET
Input
0
1
A
B
B/01
C/10
A/00
A/00
C
D
D/11
A/00
A/00
A/00
Present state
Next state
Principles of Computer Architecture by M. Murdocca and V. Heuring
Output
© 1999 M. Murdocca and V. Heuring
A-62
Appendix A: Digital Logic
State Assignment for Mod-4 Counter
Present
state (St)
Input
RESET
0
1
A:00
B:01
01/01
10/10
00/00
00/00
C:10
D:11
11/11
00/00
00/00
00/00
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-63
Appendix A: Digital Logic
Truth Table for Mod-4 Counter
RESET s1 (t)
r(t)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
s0 (t)
0
1
0
1
0
1
0
1
s1 s0 (t+1) q1 q0 (t+1)
01
10
11
00
00
00
00
00
Principles of Computer Architecture by M. Murdocca and V. Heuring
01
10
11
00
00
00
00
00
s0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
s1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
q0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
q1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t)
© 1999 M. Murdocca and V. Heuring
A-64
Appendix A: Digital Logic
Logic Design for Mod-4 Counter
RESET
CLK
DQ
s1
Q
q1
DQ
s0
Q
q0
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-65
Appendix A: Digital Logic
Example: A Sequence Detector
• Example: Design a machine that outputs a 1 when exactly two of
the last three inputs are 1.
• e.g. input sequence of 011011100 produces an output sequence
of 001111010.
• Assume input is a 1-bit serial line.
• Use D flip-flops and 8-to-1 Multiplexers.
• Start by constructing a state transition diagram (next slide).
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-66
Appendix A: Digital Logic
Sequence Detector State Transition
Diagram
0/0
0/0
• Design a machine that
outputs a 1 when exactly two of the last
three inputs are 1.
D
1/0
B
0/0
0/0
E
1/0
A
1/1
0/0
0/0
F
1/1
1/0
C
0/1
1/0
G
1/0
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-67
Appendix A: Digital Logic
Sequence Detector State Table
Input
Present state
A
B
C
D
E
F
G
Principles of Computer Architecture by M. Murdocca and V. Heuring
X
0
1
B/0
D/0
F/0
D/0
F/0
D/0
F/1
C/0
E/0
G/0
E/0
G/1
E/1
G/0
© 1999 M. Murdocca and V. Heuring
A-68
Appendix A: Digital Logic
Sequence Detector State Assignment
Input and Next state
state at and output at
time t
time t+1
Input
X
Present state
A:
B:
C:
D:
E:
F:
G:
S 2S 1S 0
000
001
010
011
100
101
110
0
1
S 2S 1S 0Z
S 2S 1S 0Z
001/0
011/0
101/0
011/0
101/0
011/0
101/1
(a)
010/0
100/0
110/0
100/0
110/1
100/1
110/0
s 2 s1 s 0 x
s2 s1 s0 z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
d
d
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
d
d
1
0
1
0
1
0
1
0
1
0
1
0
1
0
d
d
0
0
0
0
0
0
0
0
0
1
0
1
1
0
d
d
(b)
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-69
Appendix A: Digital Logic
Sequence Detector Logic Diagram
0
x
x
x
000
001
010
011
1
x
1
x
1
0
100
101
110
111
D Q
S2
Q
x
x
x
x
x
0
000
001
010
011
100
101
110
111
D Q
S1
Q
x
x
x
x
000
x
x
100
101
110
111
x
0
001
010
011
0
0
D Q
S0
Q
0
0
x
x
x
0
000
001
010
011
100
101
110
111
Z
CLK
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-70
Appendix A: Digital Logic
Example: A Vending Machine
Controller
• Example: Design a finite state machine for a vending machine
controller that accepts nickels (5 cents each), dimes (10 cents
each), and quarters (25 cents each). When the value of the money
inserted equals or exceeds twenty cents, the machine vends the
item and returns change if any, and waits for next transaction.
• Implement with PLA and D flip-flops.
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-71
Appendix A: Digital Logic
Vending Machine State Transition
Diagram
Q/110
1/0 = Dispense/Do not
dispense merchandise
A dime is
1/0 = Return/Do not return
inserted
a nickel in change
1/0 = Return/Do not
N/100
D/110
return a dime in change
N/000
A
0¢
Q/101
B
5¢
D/000
D
15 ¢
Q/111
D/000 N/000
Q/111
D/100
Principles of Computer Architecture by M. Murdocca and V. Heuring
C
10 ¢
N/000
N = Nickel
D = Dime
Q = Quarter
© 1999 M. Murdocca and V. Heuring
A-72
Appendix A: Digital Logic
Vending Machine State Table and
State Assignment
Input
P.S.
A
B
C
D
N
00
D
01
Q
10
B/000
C/000
D/000
A/100
C/000
D/000
A/100
A/110
A/110
A/101
A/111
B/111
Input
P.S.
s 1 s0
A:00
B:01
C:10
D:11
N
x1 x0
00
01/000
10/000
11/000
00/100
Q
D
x1 x0
x1 x0
01
10
s 1 s0 / z 2 z 1 z 0
10/000
11/000
00/100
00/110
00/110
00/101
00/111
01/111
(a)
(b)
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-73
Appendix A: Digital Logic
PLA Vending Machine Controller
x1
x0
s1
z2
z1
z0
5×5
PLA
s0
x1
x0
Q D
s0
0
(a)
CLK
1
Q D
s1
2
4
B ase 10
equivalent
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P resent
state C oin
D ispense
N ext
R eturn nickel
state
R eturn dim e
s1 s0 x1 x0
s1 s 0 z 2 z 1 z 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
d
1
1
0
d
1
0
0
d
0
0
0
d
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
d
0
1
0
d
1
0
0
d
0
0
1
d
0
0
1
d
0
0
1
d
0
1
1
d
1
1
1
d
0
0
1
d
0
0
0
d
0
0
1
d
0
1
1
d
5
6
8
0
0
0
d
0
0
1
d
0
0
1
d
0
0
1
d
(b)
9
10
12
13
14
(c)
s1
Principles of Computer Architecture by M. Murdocca and V. Heuring
s0
z2
z1
z0
© 1999 M. Murdocca and V. Heuring
A-74
Appendix A: Digital Logic
Moore Counter
• Mealy Model: Outputs are functions of Inputs and Present State.
• Previous FSM designs were Mealy Machines, in which next state
was computed from present state and inputs.
• Moore Model: Outputs are functions of Present State only.
z0 z1
0
00
1
01 4-to-1
10 MUX
x
0
1
00
0
01
1
z0
11
D Q
S0
Q
00
01 4-to-1
MUX
10
11
D Q
S1
Q
z1
1
11
10
0
1
0
CLK
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-75
Appendix A: Digital Logic
Four-Bit Register
• Makes use of tri-state buffers so that multiple registers can gang
their outputs to common output lines.
D3
Write (WR)
CLK
D2
D Q
D1
D Q
D0
D Q
D Q
Enable (EN)
WR D3 D2 D1 D0
Q3
Q2
Q1
Q0
EN Q3 Q2 Q1 Q0
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
A-76
Appendix A: Digital Logic
Left-Right
Shift
Register
with
Parallel
Read and
Write
c0
c1
c1
c0
D3
D2
D1
D0
Shift right
input
Shift left output
Shift right input
D Q
D Q
D Q
Shift right
output
D Q
CLK
Enable (EN)
Q3
Control
c1 c0
0
0
1
1
0
1
0
1
Q2
Q1
Q0
Function
No change
Shift left
Shift right
Parallel load
Principles of Computer Architecture by M. Murdocca and V. Heuring
Shift right input
Shift left output
c
c01
D3 D2 D1 D0
Shift right output
Shift right input
Q 3 Q2 Q1 Q 0
© 1999 M. Murdocca and V. Heuring
A-77
Appendix A: Digital Logic
Modulo-8 Counter
• Note the use of the T flip-flops, implemented as J-K’s. They are
used to toggle the input of the next flip-flop when its output is 1.
1
1
J Q
K
1
J Q
K
J Q
K
CLK
Enable (EN)
RESET
Q2
Q1
Q0
CLK
ENABLE
RESET
Q0
MOD(8) COUNTER
Q2 Q1 Q0
Q1
Q2
Timing Behavior
Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring