COEN6511 LECTURE 7
Electromigration
Electromigration is the force movement of metal ions due to the application of an electric
field.
The metal interconnects layers found in
silicon chips are usually arranged according to
specific hierarchy which depend on the type
of connection provided (near or far locality).
They exist as local, semi-global and global
interconnects.
Examples of global interconnects include
VDD, VSS and clock lines.
Via
Vias are Contact Cuts used to connect two metal layers together. The
connection could be of the upper layer type or Tungsten.
Incubation Period
With time, due to electromigration, the resistance
of metal connectors change. The incubation
period of a metal is the amount of time observed
for a metal to change its resistance characteristics.
The resistance depends on:
 Type of metal
 Structure of metal
 Electromigration threshold value
 Dimension
 Temperature
To determine the conductor quality, we usually
use the Mean Time To Failure (MTTF) measure.
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As current density increases, the MTTF decreases (more subjective to failure). This
parameter is different for AC and DC current.
Example: AC clock distribution network will have different MTTF to a DC power line.
For a DC interconnect, the MTTF is defined as:
E
, where A is the area, J is the current density, E is  0.5eV, K is
kT
the Boltzsman constant, and T is the absolute temperature.
MTTFDC  AJ  2 exp
For AC interconnect, the MTTF is defined as:
E
kT
, where J is the average current density, J is the average
MTTFDC 
AC 2
J J k
J
DC
AC
absolute current density and
is a constant.
DC
A exp
Example
What is the maximum current that a 5um wide metal 2 can carry? (assume J = 1mA/um)
Ans: 5mA
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Lecture#7 Overview
Example
How many contacts of 1 um * 1um is required for
metal-1 carrying 10mA in order to connect to metal-2?
Ans: 20
Assume each contact of 1um * 1um can carry 0.5mA
safely or 0.1mA/um of periphery.
Design tips:
Do not design one big contact due to current
crowding.
Sometimes it is necessary to increase the number of
contacts to have higher periphery contact so as to
reduce the current crowding. See the process manual for more information.
Example
Assume a chip of 0.5cm by 0.5cm fed by one Vdd pad. The chip consumes 1A at
3.3Volts. Determine the voltages on points marked X, Y and Z. Are these values
Acceptable? What can you about it if not?
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Lecture#7 Overview
Ans:
You will realize that although this width satisfy the current density threshold, they are
unrealistic as they consume your area.
Assume J=1mA/uM, we have a symmetrical drawing about B.
Distance from B to X = 2500 + 2500 + 1500
= 6500 uM
Assume R = 0.06  /
from process manual
2500 µ
500µ
1500µ
200µ
2500µ
Number of squares= 4+ 2/3 +1+ 2/3 + 10
=16.5
Voltage drop = 0.06 *16.5 * 500mA
= 495mV
V  495mV or 0.5V
Other voltages can be determined the same way.
Assume a 3.3V voltage supply, V=3.3-0.5=2.8V, which is not acceptable.
One solution is to increase the wire width. But that will eat into the limited amount of
metal interconnect available for the design. Alternatively, you can increase the number of
voltage supply pads on the chip. Current ASIC and FPGA can have hundreds of Vdd and
Vss pads. For example if we use 4 Vdd pads instead of one the width of the power
distribution can be reduced, The length of each segment is also reduced , overall
contributing to less area loss.
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So far, we have only considered DC analysis and only resistive drops! AC analysis due to
di/dt and dv/dt of inductive and capacitive loads has to be taken into account. These are
called Vdd and Ground bounce.
RCDelays
As device sizes decrease the delay of the switching devices decrease, but the delay due to
interconnect keep increasing. This is shown in the figure below.
The length of interconnect is a major parameter affecting delay, usually we try to keep
interconnects as short as possible. A typical interconnects length distribution is shown in
the graph below.
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An interconnect is a distributed RC network, with certain time constant that contribute to
delay due to charging and discharging of the entire line every time the input changes.
For simplicity, the entire line usually approximated to a lumped resistor and a capacitor.
Fringing and Parallel plate Capacitances
Interconnect wires are layed over insulators. As such they have capacitances:
Parallel Plate and Fringing. As wire width are scaled down the effect of the fringing
capacitance are becoming dominant.
Ctotal  C p  C f
Parallel Plate Capacitor can be determined as:
W
Cp  0 L
H
C p  C p 0 *WL where Cp0 is the capacitance per unit area.
The fringing capacitor can be determined empirically using the following relationship:

T
CF   r *

4H
2H
T
ln( 1 
(1  1  ))
T
H
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From the picture above, T is the thickness of wire and H is the distance of wire to
substrate.
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Cross talk between adjacent metal nets
Crosstalk is the unwanted voltages induced in one conductor from a neighboring
conductor due to capacitive coupling between them,
Cross section view of metal interconnects and associated parasitic capacitances
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Delay of interconnect line
Consider an interconnect line of length L and width W,
Capacitance = C/unit area * L (length) * W (width) = C
Resistance = R/ * number of squares = R
What to do if we need to model the RC line in order to get the delay?
1. Time Constant Analysis
LUMPED MODEL
T-MODEL
 -MODEL
2T-MODEL
2  -MODEL
Similarly, 3T or 3  models can be obtained. As we increase the modeling complexity, a
better approximation of the delay is obtained. Table below gives correlation between
different modeling methods.
Voltage Range
0 – 50%
0 – 63%
10 – 90%
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Lumped RC
0.69RC
RC
2.2RC
Distributed RC
0.38RC
0.5RC
0.9RC
Lecture#7 Overview
Assume R = Resistance per unit length,
C = Capacitance per unit area
The line can described as a distributed RC network as
From the analysis,
rc
N ( N  1) , where N is the number of sections or units.
2
rcl 2
, where l is the length of the interconnect.
 delay 
2
 delay 
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