Topics
State assignment.
 Power optimization of sequential machines.
 Design validation.
 Sequential testing.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
State assignment
Encoding bits in symbolic state = state
assignment.
 State assignment affects:

– combinational logic area;
– combinational logic delay;
– memory element area.
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
State assignment in n-space
1
s2 code = 110
s1 code = 111
0
1
1
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
State assignment and delay
output
Next state
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Power optimization
Memory elements stop glitch propagation:
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Sequential testing
Much harder than combinational testing—
can’t set memory element values directly.
 Must apply sequences to put machine in
proper state for test, be able to observe
value of test.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Example
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Testing the machine
To test NAND for stuck-at-1, must set both
NAND inputs to 1.
 Primary input i1 can be controlled directly.
 To set lower NAND input, must set state to
ps0 = ps1 = 1.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Example state machine
State codes:
s0 = 11
s1 = 10
s2 = 01
s3 = 00
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Controlling an FSM
Don’t know initial state of machine.
 Must find a sequence which drives machine
to required state independent of initial state.
 State sequence for test:

* -> s0 -> s1 -> s3.
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Time-frame expansion
A model for sequential test: unroll machine
in time.
 Time frame expansion illustrates how
single-stuck-at fault in sequential machine
appears to be multiple-SA fault.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Time-frame expansion example
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Unreachable states
State assignment may cause some states to
be unreachable.
 As a result, it may not be possible to apply
some required test values.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Unreachable state example
0/
1/
s1
s0
1/
0/
1/
0/
s2
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Example

State codes:
– s0 = 00
– s1 = 01
– s2 = 10.

This creates a fourth state which is
unreachable.
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Implemented FSM
1/
0/
00
01
1/
0,1/
0/
0/
1/
10
Modern VLSI Design 4e: Chapter 5
11
Copyright  2008 Wayne Wolf
LSSD
LSSD = level-sensitive scan design.
 Way to achieve full controllability,
observability of registers.
 Links all registers in a scan chain.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
LSSD latch
Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf
Partial scan
Full scan is expensive—must roll out and
roll in state many times during a set of tests.
 Partial scan selects some registers for
scanability.
 Requires analysis to choose which registers
are best for scan.

Modern VLSI Design 4e: Chapter 5
Copyright  2008 Wayne Wolf