Fault Nodes in Implication Graph for
Equivalence/Dominance Collapsing,
and Identifying Untestable and
Independent Faults
R. Sethuram
[email protected]
M. L. Bushnell
[email protected]
V. D. Agrawal
[email protected]
1
Outline


Purpose
Introduction






Terms and definitions
Implication Graph
The New Functional Fault graph (FFG)
Identify Equivalence/Dominance/Independence
and redundant faults using FFG
Results and analysis
Conclusion
2
Purpose

Fault collapsing



Reducing ATPG Time
Test data volume
Identifying independent faults

Compaction
Extension for other fault models
 Polynomial-time complexity

3
Definitions

Fault dominance


Fault equivalence


f1 dominates f2 if every test of f2 detects f1
If f1 and f2 dominate each other
Fault independence

If every test of f1 does not detect f2
4
Implication Graph (IG) example
Graph represents Boolean expressions
 Nodes represent literals, edges represent
implications

1
2
3
1
3
2
1
2
3
5
Operations on IG

Transitive Closure: adds an edge



For every path
For every common
ancestor
2
5
4
1
Graph condensation
3
Strongly Connected Component (SCC)
a
e
c
b
C3
C1
Condense
d
f
g
C4
C2
6
Functional Fault Graphs (FFG)

New fault node to represent the fault
detectability status
a sa0
a
b
a0
c
a
a
Oa
Complete FFG of a 2-input AND gate
7
Deriving Information

Perform transitive closure and graph
condensation. Then, identify:


Equivalence:
Fault nodes f1, f2, …, fk are in one SCC
Dominance:
f1
f2

Independence:
f1
f2

Untestable faults: f1
f1
8
IGs are incomplete
Observability relationship between stem
and its branches cannot be represented
 It can be partially overcome

If p and q are two signals such that q is the
dominator of p then Op  Oq
p
q
9
An example – i0 dominates d1
a
c
d
e
b
j
h
g
m
i
k
f
1. d1  Od  Og  Om and d1  Od  b
2. d1  a j and d1  a  I
3. Om  j  Ok and Ok  b  Oi. Hence, d1  Oi
4. d1  i and d1  Oi. Hence, d1  i0
10
Extending for other Fault Models

Adding special nodes and edges in IG
enables extending them for other fault
models


Time frame edges for implication across time
frames
Edges annotated with multiple bits
-1
l
lSR
01
Ol
lSR
01
lSR = Slow to raise fault
01
+1
l
01
Ol
11
Results – Fault Collapsing
Total
Structural
Prasad
Ours
# Dominant Faults
16000
14000
12000
10000
8000
6000
4000
2000
0
c2670
c3540
c5315
c6288
c7552
•c6288 has several stems and our technique could not identify additional
observability related implications.
12
Results – Comparison using the
circuit c1355
2500
2000
1500
1000
500
O
ur
s
Pr
as
ad
Ag
ra
w
al
St
r
uc
tu
ra
l
0
To
ta
l
# Dominant Faults
3000
13
Results - Independent fault pairs for
c432
# Ind. Flt. Pairs
Total Faults 1000
800
30000
600
20000
400
10000
200
0
Total Faults
#Ind. Flt. Pairs
40000
0
1
2
3
4
5
Logic Cone
6
7
14
# Transition Delay Faults
Results – Untestable delay faults
2500
K=5
2000
K = 10
1500
K = 15
1000
500
0
s13207
s38417
s38584
b15s
b17s
* Only the first K levels of the netlist were analyzed
15
Conclusion
Proposed and implemented a functional
fault graph for equivalence/dominance
fault collapsing and identifying
independent fault pairs
 Requires only polynomial-time algorithms
 Can be easily enhanced for other fault
models
 Reduces fault set size by up to 66%

16