August 2004
doc.: IEEE 802.11-04/0953r0
Flexible Coding for
802.11n MIMO Systems
Keith Chugg and Paul Gray
TrellisWare Technologies
Bob Ward
SciCom Inc.
[email protected]
Submission
Slide 1
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Overview
•
•
•
•
FEC Requirements for IEEE 802.11n
Introduction to TrellisWare’s F-LDPC Codes
F-LDPC Turbo/LDPC dual interpretation
IEEE 802.11n PHY Layer FEC proposal
–
–
–
–
Description
Features
Performance
Complexity
• Conclusions
Submission
Slide 2
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
FEC Requirements for IEEE 802.11n
• There are a number of essential features that an FEC solution must
possess to satisfy the requirements of IEEE 802.11n
• Frame size flexibility
– Packets from MAC can be any number of bytes
– Packets may be only a few bytes in length
• Code rate flexibility
– Need fine rate control to make efficient use of the available capacity
• Good performance
– Need codes that can operate as close as possible to theory
• High Speed
– Need decoders that can operate at 300-500 Mbps
• Low Complexity
– Need to do all this without being excessively complex
Submission
Slide 3
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
FEC Requirements for IEEE 802.11n (2)
• Benefits of flexibility in IEEE 802.11n:
– Allows one to future-proof the design – i.e., don’t let the FEC
eliminate operational modes in the future
– Can hit best throughput that the channel allows
• maximize spectral efficiency
• Support various multiple antenna Tx/Rx strategies equally well
• Eliminate the need for stuff/padding to accommodate inflexible FEC
– Flexibility comes nearly for free with TrellisWare’s F-LDPC
• Flexibility of the F-LDPC means that it can easily be
configured to operate in 20 MHz or 40 MHz systems, or
with any number of transmit and receive antennas
Submission
Slide 4
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare’s F-LDPC Codes
• A Flexible-Low Density Parity Check Code (F-LDPC)
• Serial concatenation of the following elements:
–
–
–
–
–
Outer code: 2-state rate ½ non-recursive convolutional code
Flexible algorithmic interleaver
Single Parity Check (SPC) code
Inner Code: 2-state rate 1 recursive convolutional code
Systematic code overall
F-LDPC Encoder
P/S (2:1)
S/P (1:J)
input bits
Outer
Code
I
…
J bits
wide
Submission
Slide 5
S
P
C
parity bits
Inner
Code
systematic bits
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare’s F-LDPC Codes (2)
• Use of 2-state constituent codes means very low decoder
complexity
–
–
–
–
Outer code polynomials: (1+D, 1+D)
Inner code polynomial: (1/(1+D))
Outer code uses tail-biting termination
Inner code is unterminated
• For K-bit frames the interleaver is fixed at 2K bits,
regardless of rate.
– Any good algorithmic interleaver will give frame size
programmability down to bit level
• SPC forms single-parity check of J bits.
– Different code rates are achieved by only varying J
– Code rate = J/(J+2)
– Inner code runs at 1/J fraction of speed of outer code
Submission
Slide 6
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare’s F-LDPC Codes (3)
•
•
The F-LDPC offers outstanding flexibility and performance
Code rate flexibility is achieved by simply varying the SPC J parameter
–
–
•
Frame size flexibility is achieved independently by changing the interleaver size
–
–
•
•
Byte-level frame size programmability is simple
Good performance even for frames as small as a few bytes
Performance is very close to finite block size performance bounds across a huge range
of code rates and frame sizes
Unique features of code make it well suited to low complexity, high speed decoder
architectures
–
–
•
Many different code rates are supported
Good performance even for rates above 0.95
Can be decoded by either LDPC or Turbo code decoder architectures
Similar logic complexity as typical LDPC decoders with less memory and faster convergence
(and more flexibility)
Proven technology
–
–
Submission
A number of F-LDPC variants have been implemented in FPGA
A high speed ASIC is near completion that uses a 4-state variant of the F-LDPC called a
FlexiCode (with 4-state codes floors are below 10-10 BER)
Slide 7
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC Duality Interpretations
• Proposed code can be viewed as either
– Concatenation of two-state convolutional codes with a
single-parity check (SPC) block code
– Punctured irregular-LDPC (IR-LDPC)
– IR-LDPC
• Proposed code can be decoded using
– Forward-backward algorithm (BCJR) type SISO
decoders (typically associated with concatenated
convolutional codes)
– Parallel “check node” and “variable node” processors
(typically associated with LDPC codes)
Submission
Slide 8
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC Duality Interpretations (2)
• Performance is comparable to good IR-LDPC code
– Near best performance of best known codes over wide range of
block sizes and code rates
• Decoding complexity (measured by operation counts) is
very low
– Similar to that of DVB-S2 IR-LDPC
– Significantly less that of an 8-state PCCC (e.g., 3GPPP)
• LDPC and “turbo” architectures apply
– Third parties with good solutions for concatenated convolutional
codes and LDPC codes can apply their technology
– Yields high degree of freedom for trade-off between parallelism,
memory architectures, etc.
Submission
Slide 9
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Concatenated CCs
Encoder
P/S (2:1)
S/P (1:J)
K input bits
1+D
…
I
1+D
V=(2K)/J parity bits
S
P
C
1/(1+D)
Rate=J/(J+2)
J bits
wide
“zig-zag” code
K systematic bits
Decoder (standard rules of iterative decoding)
> 0
<
Channel Metrics (LLRs)
for parity bits
Outer
SISO
Hard
decisions
I-1
…
SPC
SISO
Inner
SISO
I
J bits
wide
“zig-zag” SISO
Channel Metrics (LLRs)
for systematic bits
Note: activation begins with outer code
Submission
Slide 10
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC
Recall: Encoder
1+D
b
c
…
I
1+D
(K x 1)
PTc
Tc
(K x 1)
(2K x 1)
S
P
C
e
p
1/(1+D)
J bits
wide
“zig-zag” code
b
c = Gb
e = JPTc
G: generator of outer (1+D) code (K x K)
S: “staircase” accumulator block (V x V)
T: repeat outer code bit twice (2K x K)
P: permutation of interleaver (2K x 2K)
J: SPC mapping (V x 2K )
e + Sp = 0
V
S
K
0
V
JPT 0
I
G
K
K
p
c
b
=0
Low Density Parity Check: Hc’ = 0
Submission
Slide 11
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (2)
100… 001
1100…000
01100…00
001100…0
000110…0
G=
S=
00…00110
000…0011
100… 000
1100…000
01100…00
001100…0
000110…0
P=
00…10000
010…0000
00…00110
000…0011
(K x K)
0000…100
0001…000
10000…00
T=
(pseudo-random permutation matrix)
(2K x 2K)
00…00010
000…0010
00…00001
000…0001
(V x V)
This element is 1 if
outer code is tail-bit; 0
if unterminated
J
This element is 1 if
outer code is tail-bit; 0
if unterminated
(2K x K)
11…1
0
11…1
11…1
J=
0
100… 000
1000…000
01000…00
010000…0
001000…0
001000…0
000100…0
000100…0
H=
11…1
S
0
…
JPT 0
I
G
11…1
(V x 2K)
Submission
Slide 12
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (3)
Inner (zig-zag) code
Present if inner code it tail-bit
…
J
J
J
J
J
I/I-1
2
2
2
2
2
…
Present if outer code it tail-bit
Outer code
Submission
Slide 13
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (4)
K check nodes (from outer code); (dc=3)
V=(2K/J) check nodes (from inner code); (dc=J+2)
…
…
3
3
3
3
3
J+2
J+2
J+2
J+2
J+2
Structured Permutation
2
2
2
2
…
2
b: K Systematic Bits (dv=2)
3
3
3
3
…
3
c: K (hidden) bits (dv=3)
2
2
2
2
…
2
p: V=(2K/J) parity bits (dv=2)
dv
Frac. of 2K(1+1/J) total
dc
Frac. of K(1+2/J) total
2
(J+2)/(2J+2)
3
J/ (J+2)
3
J/[2(J+1)] (hidden)
J+2
2/(J+2)
Note: this assumes inner and outer codes are tail-bit. If not, there will be a small difference as implied in the previous slides
Submission
Slide 14
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (5)
Example of degree distribution for various code rates
J Rate (after punct) Rate (before punc.) frac(dv=2)
frac(dv=3)
frac(dc=3) J+2 frac(dc=J+2)
2
0.5
0.333333333
0.666666667 0.333333333
0.5
4
0.5
4
0.666666667
0.4
0.6
0.4
0.666666667 6 0.333333333
8
0.8
0.444444444
0.555555556 0.444444444
0.8
10
0.2
16 0.888888889
0.470588235
0.529411765 0.470588235 0.888888889 18 0.111111111
• Complexity is roughly measured
by number of edges in the parity
check graph
– TW’s F-LDPC has edge complexity
slightly less than the DVB-S2 IRLDPC code
Submission
Slide 15
Code
Numer of Edges/K
Rate TW's F-LDPC
DVB-S2
0.50
7
7
0.67
6
6.875
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (6)
• Decoder Activation schedules
– “Standard LDPC”: parallel variable-node, parallel
check node
• Number of internal messages stored = number of edges (~7K)
– “Piecewise Parallel (green-red-blue)” schedule
• Number of internal messages stored (~2K)
– “Standard Concantenated Convolutional Code”
schedule
• Same as discussed when interpreting F-LDPC as CCC
• Number of internal messages stored (~2K)
– Piecewise Parallel and Standard CCC exploit structure
of the punctured IR-LDPC permutation
Submission
Slide 16
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (7)
…
…
3
3
3
3
3
J+2
J+2
J+2
J+2
J+2
I/I-1
2
2
2
2
…
2
3
3
3
3
…
3
2
2
2
2
…
2
Structure of permutation enables potential memory savings and
different high-speed decoding architectures
Submission
Slide 17
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (8)
Standard LDPC schedule
2
1
1
2
2
1
2
1
2
1
2
1
Piecewise Parallel (green-red-blue) schedule
1
8
2
7
3
6
4
5
Standard CCC schedule (Outer SISO -> Inner SISO)
Outer SISO
Submission
Inner SISO
Slide 18
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as Punctured IR-LDPC (9)
• Schedule properties
– All are examples of the same standard iterative
message-passing decoding rules with different
activation schedules
– Each have the same computational complexity
per iteration
– Iteration convergence, degree of
parallelism,memory needs, etc. vary with
schedule
Submission
Slide 19
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as IR-LDPC
• Possible to eliminate hidden variables
– Formulates the F-LDPC as in a standard IRLDPC format
• i.e., N variable nodes, V=(N-K) check nodes
V
K
S
0
V
Submission
JPT 0
I
G
K
K
p
c
b
=0
V
S
JPTG
V
Slide 20
=
p
V
b
K
K
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
F-LDPC as IR-LDPC (2)
• Degree distribution
– For high-spread interleaver and K>>J
• V variable nodes with dv=2
• K variable nodes with dv=4
• All checks have dc=2J+2
– Example: r=1/2: 50% dv=2, 50% dv=4, dc=6
• This form has many four-cycles
– Modified schedule or H-matrix transformations
likely required for good performance based on
this graphical model
Submission
Slide 21
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
IEEE 802.11n PHY Layer FEC Proposal
Submission
Slide 22
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Proposal Description
• A single, flexible encoder that is suitable for use in a
variety of MIMO-OFDM systems
• F-LDPC encoder is coupled with a simple puncture circuit
for fine rate control, a bit channel interleaver, and a
flexible mapper
• Code rate and modulation profile can be tuned to maximize
throughput
11n Encoder
P/S (2:1)
output
symbols
S/P (1:M)
systematic bits
input bits
F-LDPC
Encoder
Bit
Interleaver
Puncture
…
Flexible
Mapper
I
Q
parity bits
Submission
Slide 23
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Proposal Description (2)
•
F-LDPC Encoder
– Code words of 3-1024 bytes
– Larger packets transmitted by concatenating multiple code words of near equal
length (avoids small code words)
– 5 Coarse rates of r = 1/2, 2/3, 4/5, 8/9, and 16/17
•
Puncture for fine rate control
–
–
–
–
•
Needed for code rates between ½ and 2/3
9 Fine rates of p = 16/16, 15/16,…., 8/16
Overall rate of r/(r+p(1-r))
45 code rates from 1/2 to 32/33
Interleaver
– Bit interleaving of a single code word
– A simple relative prime interleaver is used here (the size of this interleaver must be
very flexible)
•
Flexible Mapper
– 5 modulations of BPSK, QPSK, 16QAM, 64QAM, and 256QAM
– Gray mapping
– Bit-loading is easily supported
Submission
Slide 24
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Rate Adaptation
• A single encoder is recommended, regardless of the
number of sub-carriers and the number of spatial channels.
• A simple rate adaptation algorithm is used to determine the
optimal code rate given the SNR profile of the channel,
and to provide a modulation profile (bit loading)
• The modulation can be the same on all sub-carriers, but
better performance is achieved if the modulation is varied
across sub-carriers and spatial channels
• The fine code rate control can be used to eliminate or
minimize pad bits. The code rate is decreased slightly to
reduce the number of pad bits
Submission
Slide 25
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Code Rate Flexibility
• The following slides demonstrate the code rate flexibility
of the F-LDPC
• Firstly PER vs. SNR curves are shown for a range of code
rates and modulation orders.
– AWGN channel
– 8000 information bit code word length
– 32 iterations (with early stopping 32 iteration performance can be
achieved with considerably less iterations in practice)
• 1% PER can be achieved from -2 dB to 27 dB SNR in
approximately 0.25 steps
• Next the bandwidth efficiency is shown against SNR
required to achieve a PER of 1%, for the full range of code
rate, modulation types, and frame sizes (from 128 to 8000
information bits)
Submission
Slide 26
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC AWGN Performance - 8000 Information bits 32 Iterations
All Modulations
1
PER
0.1
0.01
Rate 1/2 BPSK – 32/33 256QAM
0.001
0
5
15
10
20
25
30
SNR (dB)
Submission
Slide 27
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC AWGN Performance - 32 Iterations
8
128 bits
256 bits
7
512 bits
1024 bits
2048 bits
6
8000 bits
5
4
3
2
1
Rate 1/2 - 32/33
0
-5
0
5
10
15
20
25
30
Required SNR for 1% PER (dB)
Submission
Slide 28
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Frame Size Flexibility
• The following slides demonstrate the frame size flexibility
• The coding and modulation is fixed at rate 4/5 16QAM
• Firstly PER vs. SNR curves are shown for a range of frame sizes from
8 to 1000 bytes
– AWGN channel
– 8000 information bit code word length
– 32 iterations (with early stopping 32 iteration performance can be
achieved with considerably less iterations in practice)
• Next the SNR required to achieve a PER of 1% is shown against frame
size
– Both automated search and hand tuned interleaver parameters are shown.
It is expected that performance matching that of the hand tuned
parameters will be achieved everywhere eventually
– The finite block size performance bound is also plotted, showing that the
automated search parameters are within 1 dB of this bound, and the hand
tuned parameters are with 0.75 dB (see the performance section for a
description of this bound)
Submission
Slide 29
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC AWGN Performance - rate 4/5 16QAM 32 Iterations
1
PER
0.1
0.01
1000 bytes
8 bytes
Frame Size
0.001
10.5
11
11.5
12
12.5
13
13.5
14
SNR (dB)
Submission
Slide 30
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC AWGN Performance - rate 4/5 16QAM 32 Iterations
13.5
Automated search parameters
Hand tuned parameters
Finite block bound
13
Modulation constrained capacity
12.5
12
11.5
11
10.5
10
0
1000
2000
3000
4000
5000
6000
7000
8000
Frame Size (bits)
Submission
Slide 31
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Early Stopping
•
F-LDPC codes can use early-stopping to reduce the average number of
iterations and increase the data throughput
– The hard decisions from the outer code are re-encoded and compared to hard
decisions of the extrinsic information from the outer code
– If all bits in a codeword agree then no more iterations are performed
– More iterations can be performed when needed
– Requires a larger input buffer and flow-control algorithm to avoid buffer overflow
•
The following plot shows that the performance with early stopping is almost as
good as that with 32 iterations
– Flow control algorithm active with early stopping results
– 50% larger input buffer is assumed
•
The next plot shows the average throughput as a function of required SNR for
a 1% PER, for a range of modulation schemes and code rates
– With early stopping the average number of iterations is less than 12
– Note also that the average number of iterations reduces dramatically as the code
rate increases
•
With early stopping we can achieve 32 iteration performance from a decoder
capable of an average of less than 12 iterations
Submission
Slide 32
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC Early Stopping - 8000 information bits
8
BPSK 32 its
QPSK 32 its
7
16QAM 32 its
64QAM 32 its
256QAM 32 its
6
BPSK Early Stopping
QPSK Early Stopping
5
16QAM Early Stopping
64QAM Early Stopping
4
256QAM Early Stopping
3
2
1
0
-5
0
5
10
15
20
25
30
Required SNR for 1% PER (dB)
Submission
Slide 33
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC AWGN Average Iterations - 8000 information bits
12
BPSK Early Stopping
QPSK Early Stopping
11.5
1/2
16QAM Early Stopping
11
64QAM Early Stopping
2/3
10.5
256QAM Early Stopping
4/5
10
9.5
9
8.5
8
7.5
7
8/9
6.5
-5
0
5
10
15
20
25
30
Required SNR for 1% PER (dB)
Submission
Slide 34
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Finite Block Size Performance Bound
• Useful to compare results to finite block size performance bound
• We use a symmetric information rate (SIR) and sphere packing bound
approximation with a constellation constraint (equation (11) from [1])
• This gives an Eb/No penalty (in dB) for a finite input block size. This
is a function of rate, target PER, and input block size.
• Dolinar, et. al. demonstrate that this penalty approximation is accurate
for no modulation constraint for most cases of interest.
• We observed that this is true relative to constrained constellations as
well. Specifically, adding this penalty to the min. Eb/No(dB) predicted
by the SIR yields performance limits that are useful.
Submission
Slide 35
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
AWGN Performance
• The following plot shows AWGN performance with an
8000 information bit code word for a range of code rates
and modulation types.
• 32 iterations are shown, but with early stopping 32
iteration performance can be achieved with an average of
less than 12 iterations
• All results are for max-log MAP decoding
• Also shown are the finite block size bounds and capacity
• Performance is very good compared to bound
– Except for low code rate, higher order modulation schemes
– This could be improved by iterating the soft-demapper, but this
would increase the complexity significantly
• This plot also demonstrated the fine code rate granularity
possible
Submission
Slide 36
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC AWGN Performance - 8000 information bits 32 Iterations
9
BPSK
QPSK
8
16QAM
64QAM
7
256QAM
BPSK Bound
6
QPSK Bound
16QAM Bound
5
64QAM Bound
256QAM Bound
4
log2(1 + SNR)
3
2
1
0
-5
0
5
10
15
20
25
30
Required SNR for 1% PER (dB)
Submission
Slide 37
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Non-AWGN Performance
• Non-AWGN results were generated using SVD with perfect channel
information
• Channel was the IST project IST-2000-30148 I-METRA Matlab model
• The following plots assume a 801.11a/g OFDM structure:
–
–
–
–
–
64 sub-carriers/20 MHz sampling rate
Same sub-carrier structure
48 sub-carriers for data, 4 sub-carriers for pilot
“DC” sub-carrier empty, 11 sub-carriers for guard band
3.2 µs symbol, 800 ns cyclic prefix
• Bit-loading of each sub-carrier is performed, with the rate adaptation
algorithm determining the code rate and modulation profile
• Tests run with nominal SNR into the rate adaptation algorithm of 0, 5,
10, 15, 20, and 25 dB
Submission
Slide 38
Keith Chugg, et al, TrellisWare Technologies
August 2004
•
doc.: IEEE 802.11-04/0953r0
Well suited to MIMO Environment
FLDPC
– Facilitates variable length packet transmissions, with same byte level resolution as
viterbi coded systems
– Consistent performance across wide variety of code rates
– Supports increased capacity operation with single encoder achitecture adapting
across multiple MIMO channels
– Applied in 802.11n modelled environment as well UCLA testbed demonstrating
these principles with excellent performance
IF 70MHz
IF 70MHz
PC
Wideband
Tx DPU
REF
CL
K
2.4GHz
Radio
2.4GHz
Radio
2.4GHz
Radio
2.4GHz
Radio
Wideband
Rx DPU
PC
2.4GHz
Radio
UCLA
Submission
REF
CL
K
Slide 39
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC Fading Performance - 2x2 Channel E LOS - 8000 information bits 32 Iterations
1
Nominal 0 dB
Nominal 5 dB
Nominal 10 dB
Nominal 15 dB
Nominal 20 dB
Nominal 25 dB
PER
0.1
0.01
0.001
-5
0
5
15
10
20
25
30
SNR (dB)
Submission
Slide 40
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC Fading Performance - 2x2 Channel E LOS - 8000 information bits 32 Iterations
1.6e+08
Nominal 0 dB
Nominal 5 dB
1.4e+08
Nominal 10 dB
Nominal 15 dB
Nominal 20 dB
1.2e+08
Nominal 25 dB
1e+08
8e+07
6e+07
4e+07
2e+07
0
-5
0
5
10
15
20
25
30
SNR Required for 1% PER (dB)
Submission
Slide 41
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=2048, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
FER
10
-2
10
-3
10
22
Submission
24
26
28
30
32
SNR, dB
Slide 42
34
36
38
40
42
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
FER
10
-2
10
-3
10
-4
10
22
Submission
24
26
28
30
32
SNR, dB
Slide 43
34
36
38
40
42
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x3, 1000 bytes, Flexi Code Len=512, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10 Iterations
PCSI, 20 Iterations
PCSI, 30 Iterations
-1
10
-2
FER
10
-3
10
-4
10
-5
10
14
Submission
16
18
20
22
24
SNR, dB
Slide 44
26
28
30
32
34
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x3, 1000 bytes, Flexi Code Len=2048, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
FER
10
-2
10
-3
10
-4
10
14
Submission
16
18
20
22
24
SNR, dB
Slide 45
26
28
30
32
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x3, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, No Stopping, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
FER
10
-2
10
-3
10
-4
10
15
Submission
20
25
SNR, dB
Slide
46
30
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x3, 1000 bytes, Flexi Code Len=2048, 64QAM, Rate=5/6, Genie Aided, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
FER
10
-2
10
-3
10
-4
10
15
Submission
20
25
SNR, dB
Slide
47
30
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
FER
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: B, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
10
-2
10
20
Submission
22
24
26
28
30
SNR, dB
Slide 48
32
34
36
38
40
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: E, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
10
-2
FER
10
-3
10
-4
10
-5
10
22
Submission
24
26
28
30
32
SNR, dB
Slide 49
34
36
38
40
42
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
FER
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: B, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
24
Submission
26
28
30
32
34
SNR, dB
Slide 50
36
38
40
42
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=5/6, Genie Aided, Channel Model: E, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
-4
10
24
Submission
26
28
30
32
34
SNR, dB
Slide 51
36
38
40
42
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
FER
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=5/6, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
10
-2
10
6
Submission
8
10
12
14
SNR, dB
Slide
52
16
18
20
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=3/4, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
-4
10
6
Submission
8
10
12
14
SNR, dB
Slide
53
16
18
20
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=1/2, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
7
Submission
7.5
8
8.5
9
SNR, dB
Slide 54
9.5
10
10.5
11
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=3/4, No Stopping, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
FER
10
-2
10
-3
10
-4
10
26
Submission
27
28
29
30
31
SNR, dB
Slide 55
32
33
34
35
36
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x3, 1000 bytes, Flexi Code Len=8000, 256QAM, Rate=5/6, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10 Iterations
PCSI, 20 Iterations
PCSI, 30 Iterations
-1
FER
10
-2
10
-3
10
-4
10
22
Submission
24
26
28
30
SNR, dB
Slide
56
32
34
36
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
4x4, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=3/4, No Stopping, Channel Model: D, s 2
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10
PCSI, 20
PCSI, 30
threshold=90000
Iterations
Iterations
Iterations
-1
10
-2
FER
10
-3
10
-4
10
-5
10
24
Submission
26
28
30
SNR, dB
Slide 57
32
34
36
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=2048, QPSK, Rate=5/6, No Stopping, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 10 Iterations
PCSI, 20 Iterations
PCSI, 30 Iterations
-1
FER
10
-2
10
-3
10
-4
10
10
Submission
12
14
16
18
SNR, dB
Slide
58
20
22
24
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, 64QAM, Rate=1/2, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
-4
10
17
Submission
18
19
20
21
22
SNR, dB
Slide 59
23
24
25
26
27
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, 16QAM, Rate=3/4, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
14
Submission
16
18
20
22
SNR, dB
Slide
60
24
26
28
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, QPSK, Rate=5/6, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
16
Submission
18
20
22
24
SNR, dB
Slide
61
26
28
30
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
2x2, 1000 bytes, Flexi Code Len=8000, 16QAM, Rate=1/2, Genie Aided, Channel Model: D, s 2 threshold=90000
Preamble based PSAM (Length = 2) designed for channel model F
0
10
PCSI, 20 Iterations
-1
FER
10
-2
10
-3
10
-4
10
11
Submission
12
13
14
15
16
SNR, dB
Slide 62
17
18
19
20
21
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Decoder Throughput
•
Structure of the code lends it to low complexity, high speed decoding
– Similar complexity to DVB-S2 LDPC
– Significantly lower complexity than 3GPP TC
•
•
•
•
•
TrellisWare is near completion of a high speed ASIC implementation of a 4state variant of this code
Based upon this experience the following decoder throughputs have been
calculated
We have used a baseline high speed architecture with a nominal degree of
parallelism of P=1. An architecture with a degree of parallelism of P=n is n
approximately n times as complex as the baseline, with approximately n times
the throughput
Plots are given for both throughput normalized to the system clock (bps per
clk) and actual throughput with a number of system clock assumptions
We are currently developing an P=8 FPGA prototype which can operate with a
system clock of 100 MHz and is expected to achieve a throughput of at least
300 MHz.
Submission
Slide 63
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC Throughput - 8000 information bits
10
P=1
P=2
P=4
P=8
8
6
4
2
0
5
10
15
20
25
30
Iterations
Submission
Slide 64
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
TrellisWare F-LDPC Throughput - 8000 information bits
600
P=4 f=100 MHz
P=8 f=100 MHz
P=4 f=150 MHz
500
P=8 f=150 MHz
P=4 f=200 MHz
P=8 f=200 MHz
400
P=4 f=250 MHz
P=8 f=250 MHz
P=4 f=300 MHz
300
200
P=8 f=300 MHz
FPGA Prototype:
300 Mbps
100
<0.2 dB from 32 iterations
0
5
10
15
20
25
30
Iterations
Submission
Slide 65
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
Comparion Criteria/11n Requirements
are supported well
• As a partial proposal
– Supports overall phy layer demanding requirements
– High Through-put operation – 300 500 Mbps
– Increased capacity – higher spectral efficiences
– Reliable performance  PERs below 1%
– Non Awgn environment
– Applies equally well to larger bandwidth operation
20/40 Mhz
– Supports backwards compatibility with variable length
PDU performance
Submission
Slide 66
Keith Chugg, et al, TrellisWare Technologies
August 2004
doc.: IEEE 802.11-04/0953r0
References
• [1] S. Dolinar, D. Divsalar, and F. Pollara,
"Code Performance as a function of Block
Size," JPL, TMO Progress Report 42-133.
Submission
Slide 67
Keith Chugg, et al, TrellisWare Technologies