ECE 4110– Digital Logic Design
Lecture #16
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Agenda
1. Test 1 Review
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Announcements
1. HW #7 due 10/19/11 with HW#8.
2. Next: Exam #1 Closed Book
Lecture #16
Page 1
Exam Review
PLD Topics:
-PLA’s:
-PAL’s/GAL’s:
Structure, Logic using compact representation
-CPLD’s:
Structure components, function block elements, realize logic functions using function blocks,
distinguishing features, , advantages, disadvantages, configuration programming.
- FPGA's:
Xilinx/Altera families, function block elements, realize logic functions using function blocks,
distinguishing features, configuration programming, advantages, disadvantages, configuration programm
Structure components, Logic using compact representation,
draw custom function blocks, distinguishing features, , advantages, disadvantages, configuration progra
Lecture #16
Page 2
Exam Review
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VHDL Topics: Design Abstraction
Constructs
(entity, architecture, packages)
Ports/Signals
(Internal/External, modes, types)
Data Types
(built-in, added using packages)
Operators
(built-in, added using packages)
Structural Design
(component declaration, instantiating, port maps, generate)
Concurrent Assignments
- Simple Signal Assignment
- Conditional Signal Assignment
- Selected Signal Assignment
Generics & Constants
Behavioral Design
(process execution, synthesis)
Process
(sensitivity lists, wait statements)
Variables
(:= vs <=)
Sequential Assignments
- Simple
- If/Then/Elsif/Else
- Case
- Loops (simple, while, for)
Attributes
(event, transaction, last_value, last_event)
Test Benches
(Structure, reporting)
- Decoders:
Structural, Behavioral, Enables
Lecture #16
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