Fundamentals of Computer Science
Sequential Circuits
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What is a Sequential Circuit?
• A sequential circuit consists of logic gates whose
output(s) at any time are based on the values of
external input(s) and internally generated input(s).
• Sequential circuits are used to implement storage
elements.
inputs
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Sequential
Circuit
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outputs
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What is a Sequential Circuit?
• Sequential circuits are generally part of a larger
circuit that contains combinational circuitry as
well.
• There are two types of sequential circuits
– Synchronous sequential circuits can only be affected at
discrete instances of time. They are driven by clock
generators. When a clock pulse is absent, the circuit
cannot change.
– Asynchronous sequential circuits can be affected at any
instances of time. They are not clock driven.
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Synchronous Sequential Circuits
• Flip-flops are a type of synchronous sequential
circuit.
• Each flip-flop can store 1-bit of data.
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Asynchronous Sequential Circuits
• Latches are a type sequential circuit that may be
asynchronous or synchronous.
• Each latch can store 1-bit of data.
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Unstable Asynchronous Sequential
Circuit
• This is an example of a simplest-case sequential
circuit.
– The circuit is built from a single inverter.
– The output oscillates rapidly between 0 and 1.
– The circuit is essentially useless.
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Stable Asynchronous Sequential
Circuits
• When the circuit settles down, the two outputs
will be the complement of each other.
• There is no way to modify the value stored in the
circuit.
• The circuit is essentially useless.
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Latches
• Latches are the most basic storage element.
• Latches are used to build flip-flops.
• This SR latch is a type of asynchronous sequential
circuit.
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Logic Simulation of SR Latch
Behavior
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SR Latch with NAND Gates
The input signals for the NAND latch are the
complement of the signals for the NOR latch,
hence the name SR latch.
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SR Latch with Control Input
• Latch can only change when C = 1, all other times
the circuit remains in the same state no matter
what values are on the S and R inputs.
• This SR latch is a type of synchronous sequential
circuit.
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D Latch with Control Input
The D latch is designed to eliminate the
undefined state by ensuring that the S and R
inputs are never high at the same time.
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Flip Flops
• A latch is transparent.
– Its input value can be seen directly from its
output value. Which is to say that the outputs
respond immediately to the inputs.
– This is the case with the D latch when its
control, C, is high.
• Flip-flops avoid the transparency problem
by providing a “disconnect” between the
inputs to the flip-flop and the outputs from
the flip-flop.
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Flip Flops
• Imagine the following scenario.
– The clock goes high.
– The output of the D latch, Q, responds to the input, D.
– Before the clock goes low, the new value of Q filters
through the combinational circuit and into the D latch
changing the value of Q for the second time during the
same clock cycle.
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SR Master-Slave Flip-Flop
• A flip-flop contains two clock-driven latches.
– The first flip-flop is the master.
– The second flip-flop is the slave.
• The slave receives the inverse of the clock
signal received by the master.
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SR Master-Slave Flip-Flop
• When the master’s clock input is high (and
the slave’s is low) the slave is impervious to
change so the slave’s outputs become stable.
• When the master’s clock is low (and the
slave’s is high) the slave will respond to the
master’s outputs.
– During this time the master’s outputs will remain
stable since the master’s clock is low.
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Logic Simulation of SR Master-Slave
Flip-Flop
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JK Master-Slave Flip-Flop
• The master-slave JK flip-flop is designed to
eliminate the undefined condition (both S
and R are high) found in SR latches.
• When both J and K are high, the value of
the flip-flop toggles.
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Flip-Flop Characteristic Tables
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Base 4 Binary Counter with Enable
• A base 4 binary counter with enable
repeatedly outputs the bit pattern 00, 01, 10,
11 when ever the enable line is high.
– Since the circuit is clock driven (synchronous),
the count will change when ever the clock goes
from high to low.
– When the enable line is low, the counter stops
counting and the output value remain constant.
• The counter must “remember” what the
current count is so that it knows what value
to output next.
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Base 4 Binary Counter with Enable
• The next state of the circuit is based on the
current state and the value of the enable
line.
– The current state of the counter is stored in two
flip-flops, one per binary digit.
• A state table is used to show what the next
state of the circuit will be relative to the
current state and any external inputs.
– State tables are used in sequential circuit design
much as truth tables are used in combinational
circuit design.
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Base 4 Binary Counter with Enable
Enable
Counter
DA
DB
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Base 4 Binary Counter with Enable
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