Forecasting noise and radiation hardness
of CMOS front-end electronics
beyond the 100 nm frontier
V. Rea,c, L. Gaionib,c, M. Manghisonia,c, L. Rattib,c, G. Traversia,c
aUniversità
di Bergamo
Dipartimento di Ingegneria Industriale
bUniversità
di Pavia
Dipartimento di Elettronica
cINFN
Sezione di Pavia
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
1
Motivation
Industrial microelectronic technologies are today well beyond the
130 nm CMOS generation that is currently the focus of IC
designers for LHC upgrades and other applications
Digital performances (speed, density, power dissipation) are driving
the evolution of CMOS technologies. What about analog
performance?
Sub-100 nm CMOS is appealing for the design of very compact
front-end systems with advanced integrated functionalities, such as
required by pixel sensors with low pitch:
 MAPS
 Hybrid pixels (high resistivity sensors connected to CMOS
readout chips)
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
2
Nanoscale CMOS
Source:Intel
New materials and processing techniques
are used to match specifications of sub100 nm CMOS nodes. The gate dielectric
has evolved to comply with scaling rules
while avoiding too large tunneling currents.
New physical device parameters may impact on functional
properties such as noise and radiation hardness
Gate leakage current and 1/f noise are appropriate tools to
investigate the impact of nanoscale CMOS processing on the quality
of the gate dielectric.
Focus of this talk: provide information for the design of low-noise,
rad-hard analog blocks
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
3
Investigated technologies and devices
130 nm CMOS transistors by foundry A (standard interdigitated
layout) and C (enclosed layout)
90 nm CMOS transistors by foundry A and B (standard
interdigitated layout)
Technology features:
– Supply voltage
– Electrical oxide thickness
– Gate capacitance
130 nm
VDD = 1.2 V
tOX = 2.4 nm
COX = 15 fF/μm2
90 nm
VDD = 1 V
tOX = 2 nm
COX = 18 fF/μm2
Preview of data for 65 nm CMOS LP (Low Power) transistors by
foundry B
These processes continue to use poly gates; a certain level of
nitridation is used in the the SiO2 gate dielectric (no high-k)
Comparison with previous generations, back to 350 nm
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
4
Nanoscale MOSFETs
Thin gate oxide (~ 1-2 nm) for core devices,
Thick Shallow Trench
Isolation Oxide (~ 300 nm);
radiation-induced chargebuildup may turn on noisy
lateral parasitic transistors
Doping profile
along STI
sidewall is
critical; doping
increases with
CMOS scaling
STI
gate tunneling current kept under control by gate
processing (e.g. SiON in the dielectric, new gate
electrode materials).
G
S
D
N+
N+
Strained silicon
to improve
device
performance
STI
P-well
P-substrate
Increasing sidewall doping makes a device less sensitive to
radiation (more difficult to form parasitic leakage paths)
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
5
Operating region
Under reasonable power dissipation constraints, the
preamplifier input device operates in the weak inversion region
100
Strong inversion law
Weak inversion law
m D
g /I [1/V]
NMOS
Operating point for
W/L =400/0.2 (strips),
ID = 100 A
10
PMOS
W/L =40/0.2 (pixels),
ID =10 A
*
I
*
*
Z,P,130
I
I*Z  2COXnVT2
I
Z,P,90
Z,N,90
• μ carrier mobility
CMOS 90 nm
CMOS 130 nm
1
-9
10
10
• COX specific gate oxide
capacitance
• VT thermal voltage
-8
10
-7
I L/W [A]
D
10
-6
10
-5
• n proportional to ID(VGS)
subthreshold characteristic
*
I
Z,N,130
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
6
Gate current
Charge carriers have a nonzero probability (larger for electrons
with respect to holes) of directly tunneling through a silicon dioxide
layer with a physical thickness < 2 nm (100-nm scale CMOS).
Reduction of physical oxide thickness of a few Å may give
several orders of magnitude increase in the gate current.
Gate dielectric nitridation increases the dielectric constant,
allowing for films with a larger physical thickness as compared with
SiO2 (COX = eOX/tOX). This mitigates the gate leakage current;
however, its value can sizably change in devices from different
foundries.
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
7
Gate current density in different
CMOS generations and foundries
We made tests on 65 nm LP (Low Power) transistors (VDD = 1.2 V). These devices
were optimized for a reduced leakage (larger equivalent oxide thickness, different
level of nitridation with respect to other flavours, different silicon stress ).
1
2
Gate Current Density [A/cm ]
10
0
10
-1
10
NMOS Foundry A
PMOS Foundry A
NMOS
|V | = 1 V
GS
V
DS
PMOS
-2
10
=0
90 nm CMOS transistors by
foundries A and B have very
different gate current levels (2-3
orders of magnitude)
The gate current of 65 nm LP
transistors is of the same order as in
the 90 nm node (same foundry)
-3
10
-4
10
-5
10
130 nm
90 nm
65 nm
Technology Node
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
8
Effect of gate current on noise performance

2
ENC 2   SW



Kf
A1

A2 CT2  2qIG  A3  t P
t P C WL

OX

White noise
1/f noise
Parallel noise
Even in the worst case (90 nm
process from Foundry A) series
white noise remains dominant at
tP < 100 ns.
For fast front-end electronics
systems, gate leakage current
should not have a sizable impact
on the noise.
M. Manghisoni, “Gate Current Noise in Ultrathin Oxide
MOSFETs and Its Impact on the Performance of Analog
Front-End Circuits”, IEEE TNS, Vol. 55 no. 4 pp. 23992407 Aug. 2008
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
9
1/f noise: gate stack fabrication process
The process recipe for the gate stack (gate electrode and dielectric)
may affect the density of oxide traps and their interaction with
charge carriers in the channel, impacting on the 1/f noise spectral
density.
Gate dielectric nitridation was found to degrade 1/f noise because
of the higher interface state density.
For a physical oxide thickness < 2 nm (same order of the tunnelling
distance) the traps at the interface between the gate dielectric and
the gate electrode (fully silicided poly gates) can play a major role.
1/f noise may be affected by mechanical stress in the silicon
channel (enhanced carrier mobility and drive current).
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
10
1/f noise in NMOS:
CMOS generations from 250 nm to 65 nm
2
S1/f
(f) 
W/L = 2000/0.45, 250 nm process
W/L = 1000/0.5, 130 nm process
W/L = 600/0.5, 90 nm process
W/L = 600/0.35, 65 nm process
1/2
Noise Voltage Spectrum [nV/Hz ]
100
1/f noise has approximately the same magnitude (for a same WLCOX)
across different CMOS generations. White noise has also very similar
properties (weak/moderate inversion).
10
• αf 1/f noise slope-related
coefficient
IN
I = 100 A
Channel thermal noise
D
NMOS
10
3
10
4
10
5
10
Frequency [Hz]
6
10
7
COX WLf  f
• kf 1/f noise parameter
C = 6 pF
1
Kf
1/f noise
10
8
4k T
S2W  B ,
gm
• kB Boltzmann’s constant
   W n
• γ channel thermal noise
coefficient
• T absolute temperature
• αw excess noise coefficient
In weak g  ID
m
inversion:
nVT
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
11
1/f noise from 350 nm to 65 nm CMOS
The 1/f noise parameter Kf does not show dramatic variations across
different CMOS generations and foundries.
COX WLf
NMOS
f
• kf 1/f noise parameter
f
Kf
K
2
S1/f
(f) 
• αf 1/f noise slope-related
coefficient
-24
10
( 0.85 in NMOS,  1 – 1.1 in PMOS)
-25
10
350 nm 250 nm 180 nm 130 nm 90 nm 65 nm
Technology Node
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
12
1/f noise in PMOS:
CMOS generations from 250 nm to 90 nm
1/2
Noise Voltage Spectrum [nV/Hz ]
1/f noise appears to increase (for a same WLCOX) with CMOS scaling
90 nm Foundry B W/L = 600/0.35
130 nm Foundry A W/L = 1000/0.35
250 nm Foundry C W/L = 2000/0.36
10
C = 5 pF
IN
PMOS
|V | = 0.6 V
1
DS
I = 500 A
D
10
3
10
4
10
5
10
6
10
7
10
8
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
13
1/f noise: NMOS vs PMOS
In bulk CMOS, the fact that PMOSFETs feature a smaller 1/f noise
with respect to equally sized NMOSFETs was generally related to
buried channel conduction.
In deep submicron processes, it was expected that the PMOS would
behave as a surface channel device, rather than a buried channel one
as in older CMOS generations.
With an inversion layer closer to the oxide interface, 1/f noise is
expected to increase. Ultimately, PMOSFETs should feature the same
1/f noise properties as NMOSFETs. However, this was not observed
in CMOS generations down to 130 nm and 90 nm.
A possible interpretation can be related to the different interaction
of electrons (NMOS) and holes (PMOS) with traps in the gate
dielectric (different barrier energies experienced by holes and
electrons across the Si/SiO2 interface) .
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
14
NMOS and PMOS in an FD-SOI technology
We previously found that NMOS and PMOS have the same 1/f noise
only in one case, that is, in fully-depleted 180 nm CMOS SOI
transistors. A possible explanation was that in a very thin silicon film
(40 nm) conduction takes place very close to the Si-SiO2 interface.
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
100
PMOS
10
FD-SOI CMOS devices
W/L = 100/0.5
I = 50 A
D
V
DS
1
10
3
= 0.6 V
10
4
10
5
10
6
10
7
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
15
1/f noise: NMOS vs PMOS
Difference tends to decrease with newer CMOS generations.
100
PMOS
10
I = 500 A
D
1
180 nm NMOS Foundry A
W/L = 2000/0.2
3
10
10
4
5
10
Frequency [Hz]
180 nm
6
10
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
NMOS
1/2
Noise Voltage Spectrum [nV/Hz ]
100
7
10
10
8
PMOS
10
I = 500 A
D
1
90 nm NMOS Foundry B
W/L = 600/0.35
3
10
10
4
5
10
6
10
7
10
10
Frequency [Hz]
90 nm
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
16
8
65 nm LP process: 1/f noise
In the 65 nm LP process by Foundry B, NMOS and PMOS have similar 1/f noise
(especially longer transistors).
]
100
100
1/2
Noise Voltage Spectrum [nV/Hz
Noise Voltage Spectrum [nV/Hz
1/2
]
This could be explained by a “surface channel” behavior for both devices, and/or
by the fact that the gate dielectric nitridation decreases the barrier energy
experienced by holes across the silicon-dielectric interface. This would make it
easier for the PMOS channel to exchange charges with oxide traps.
NMOS
PMOS
10
65 nm transistors W/L=600/0.35
@ ID=50 A, VDS=0.6 V
1
3
10
10
4
5
10
6
10
Frequency [Hz]
7
10
10
8
NMOS
PMOS
10
65 nm transistors W/L=600/0.10
@ ID=50 A, VDS=0.6 V
1
3
10
10
4
5
10
6
10
7
10
10
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
17
8
Ionizing radiation effects in sub-100 nm CMOS
Radiation induced positive charge is removed from thin gate oxides
by tunneling (which also prevents the formation of interface states)
Isolation oxides remain thick (order of 100 nm) also in nanoscale
CMOS, and they are radiation soft.
With scaling, the effect of positive charge buildup in STI oxides
appears to be mitigated by the higher doping of the silicon bulk.
However, the radiation-induced noise degradation may be sizable. This
is associated to noisy lateral parasitic transistors. The use of
enclosed devices for low-noise functions will help.
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
18
NMOSFETs and lateral leakage
In NMOSFETs edge effects due to radiation-induced positive
charge in the STI oxide generate sidewall leakage paths.
Shaneyfelt et al,
“Challenges in Hardening
Technologies using
Shallow-Trench Isolation”
IEEE TNS, Dec. 1998
Lateral
transistors have
the same gate
length as the
main MOSFET
L
NMOS finger
n
+
Drain
polyGate
Source
STI
Drain
Multifinger NMOS
Gate
STI
1
2
mf
Source
n+
Lateral parasitic
devices
STI
Main transistor
finger
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
19
Radiation effects on noise: 90 nm NMOS
100
10
before irradiation
10 Mrad
1
3
10
4
10
5
10
6
10
Frequency [Hz]
7
10
10
1000
1/2
STM 130 nm process
open layout
NMOS W/L=1000/0.20
Id=100 A
Vds=0.6 V
Noise Voltage Spectrum [nV/Hz
Noise Voltage Spectrum [nV/Hz
1/2
]
]
In 90 nm open layout NMOSFETs, at 10 Mrad total dose the main radiation
effect is a 1/f noise increase at low current density, due to the contribution
of lateral parasitic devices. No increase in the white noise region is detected.
8
90 nm process
core NMOS
W/L=200/0.20
Id=20 A @ Vds=0.6 V
100
10
before irradiation
10 Mrad
1 3
10
10
4
5
10
6
10
7
10
10
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
20
8
Radiation effects: 90 nm vs 130 nm NMOS
The noise increase seems to saturate at a total dose of several Mrad
(smaller in 130 nm devices). This is in agreement with the behavior of the lateral
leakage current in irradiated devices (saturation effect in positive charge buildup in the STI oxide, along with a compensating effect from interface states)
100
1/2
NMOS 1000/0.35 @ VDS = 0.6 V
Id = 100 A
130 nm
10
before irradiation
1
1 Mrad
10 Mrad
3
10
10
4
10
5
f [Hz]
130 nm
6
10
7
10
NMOS W/L=1000/0.13
Id=50 A @ Vds=0.6 V
90 nm Foundry A
1/2
Noise Voltage Spectrum [nV/Hz ]
Noise Voltage Spectrum [nV/Hz ]
100
10
8
10
100 Mrad
10 Mrad
1 Mrad
1
before irradiation
3
10
10
4
5
10
6
10
7
10
10
Frequency [Hz]
90 nm
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
21
8
Radiation effects on noise:
130 nm enclosed NMOS
100
100
nd
2 130 nm vendor
NMOS enclosed
W/L=1000/0.24
Id=100 A @ Vds=0.6 V
10
1
before irradiation
100 MRad
0,1 3
10
10
4
5
10
6
10
Frequency [Hz]
7
10
STM 90 nm process
PMOS W/L=1000/0.35
I =100 A
1/2
Noise Voltage Spectrum [nV/Hz ]
Noise Voltage Spectrum [nV/Hz
1/2
]
In 130 nm enclosed NMOSFETs and in PMOSFETs, at 100 Mrad total dose, noise
degradation is negligible. This provides evidence for a model where the basic
mechanism underlying noise increase in irradiated devices is associated to lateral
parasitic transistors.
10
8
D
10
|V |=0.6 V
DS
1
pre-rad
100 Mrad
0,1 2
10
10
3
4
10
5
10
10
6
7
10
10
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
22
8
Conclusions
Nanoscale MOSFETs have very interesting new features in terms
of device processing and physics.
At the 90 nm and 65 nm nodes, low-noise analog design will pose
challenges but, according to the study of key analog parameters,
appears to be still viable. PMOSFETs appear to gradually lose their
1/f noise advantage over NMOSFETs.
Isolation oxides are the main threat to ionizing radiation tolerance.
Enclosed devices may still be necessary for low-noise performance
under irradiation.
The price of these technologies will of course have an impact on their
use in our fields; this was beyond the scope of this talk.
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
23
Backup slides
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
24
Modeling lateral leakage
W
lat,finger
C
OX,lat
[fF/m]
From the ID,lat vs VGS curves for the equivalent parasitic transistor, it is
possible to extract the product of its gate width and of its effective oxide
capacitance WlatCOX,lat.
This product increases with
TID induced
increasing dose, since a larger
0.12
positive charge
portion of the STI sidewall gets
gate
inverted.
0.1
The effective gate width, oxide
thickness and capacitance are
determined by the extension of the
inverted regions along sidewalls.
tOX,lat,min
t
OX,lat,min
0.08
θ
STI
0.06
P-type
Substrate
0.04
substrate
(Well)
tOX,lat,max
tOX,lat,max
0.02
0
1
10
Inverted region
TID
[Mrad]
At STI
sidewall
100
At low doses, only the sidewall
bottom is inverted because bulk
doping is lower in that region; at
higher doses the inversion region
extends towards the surface,
involving thinner STI oxide regions.
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
25
Effects of lateral leakage at different ID
The radiation-induced increase of ID,lat appears to saturate beyond 10 Mrad.
This may be due to a saturation effect in positive charge build-up in the STI
oxide, along with a compensating effect from interface states.
Total drain current
-3
10
-4
Drain Current [A]
10
-5
10
total ID @ 100 Mrad
ID,main before irradiation
ID,lat @ 100 Mrad
ID,lat @ 10 Mrad
ID,lat @ 1 Mrad
Lateral
leakage
current
-6
10
-7
10
core NMOS
W/L = 100/0.35
VDS=0.6V
-8
10
90 nm Foundry A
-9
10
-0.2
-0.1
0
0.1
0.2
0.3
0.4
ID,lat goes from a weak inversion
behavior (logID linear with VGS) to
a strong inversion one (with a
reduced slope of ID vs VGS) at a
smaller VGS than the drain current
ID of the main device.
The contribution of ID,lat to
the total device current as
well as the other effects due
to lateral parasitic
transistors are larger at
small values of ID.
Gate-to-Source Voltage [V]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
26
Lateral leakage in 130nm and 90nm core transistors
The radiation-induced increase of ID,lat is considerably larger in 130 nm
devices than in 90 nm transistors. This could be explained by a higher doping
concentration in the p-type body for the 90 nm process, which mitigates the
inversion of the surface along the STI sidewalls.
-3
10
-4
10
-5
10
-6
10
-7
10
-8
Doping of P and N-wells increases
with CMOS scaling, to keep
drain/source depletion regions small
with respect to gate length.
Lateral leakage current in
NMOSFETs irradiated at 10 Mrad(SiO )
2
More scaled CMOS technologies
appear to be less sensitive to
lateral leakage effects
associated to the STI oxide.
130 nm process
I
D,lat
[A]
10
90 nm process
-9
10
-0.2
-0.1
0
V
GS
0.1
[V]
0.2
0.3
Enclosed devices may not be
strictly required in rad-hard
systems.
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
27
65 nm LP process: operating regions (preview)
In terms of the gm/ID ratio, LP 65 nm transistors have an advantage over
previous CMOS generation only at large drain current densities.
This seems to point out that the device parameters (carrier mobility?) are
optimized for large drive currents in digital circuits (large overdrive voltages)
100
Weak inversion law
m D
g /I [1/V]
Strong inversion law
10
NMOS 130 nm
NMOS 90 nm
NMOS 65 nm
1 -9
10
-8
10
-7
10
10
-6
-5
10
-4
10
I L/W [A]
D
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
28
Radiation effects on noise:
NMOS 130 nm open layout
1/2
STM 130 nm process
open layout
NMOS W/L=1000/0.20
Id=100 A
Vds=0.6 V
100
Noise Voltage Spectrum [nV/Hz
Noise Voltage Spectrum [nV/Hz
1/2
]
]
In 130 nm open layout NMOSFETs, at 10 Mrad total dose the main radiation
effect is again a 1/f noise increase at low current density, due to the
contribution of lateral parasitic devices. Since the impact of lateral devices is
larger for this process, a noise increase in the white spectral region is also
detected at low currents.
10
before irradiation
10 Mrad
1
3
10
4
10
5
10
6
10
Frequency [Hz]
7
10
10
8
STM 130 nm process
open layout
NMOS W/L=1000/0.20
Id=1 mA
Vds=0.6 V
100
10
before irradiation
10 Mrad
1
3
10
4
10
5
10
6
10
7
10
10
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
29
8
65 nm NMOS: white noise
100
10
1
NMOS W/L = 600/0.20
@ VDS=0.6 V
0.1
10
3
10
4
10
5
10
Frequency [Hz]
6
10
7
1/f Slope (f=1)
1/2
Noise Voltage Spectrum [nV/Hz ]
1/2
Noise Voltage Spectrum [nV/Hz ]
100
ID=20 A
ID=50 A
ID=100 A
ID=250 A
ID=500 A
1/f Slope (f=1)
10
8
10
1
ID=20 A
ID=50 A
ID=100 A
ID=250 A
NMOS W/L=1000/0.13
@ VDS=0.6 V
0.1
10
3
10
4
10
5
10
6
10
7
10
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
30
8
Channel thermal noise – STM 90 nm
Equivalent Noise Resistance [
300
Equivalent channel thermal noise
resistance
90 nm tech
NMOS L>0.13 m
Linear fit
offset = 1.68 +/- 1.45
slope = 0.96 +/- 0.02
250
200
R Th
S 2W

4k B T
150
slope  excess noise coefficient w
100
offset  noise contributions from
parasitic resistors
50
0
0
50
100
150
200
250
300
n/g [
m
w close to unity  no sizeable short channel effects in the considered operating
regions (no data available for channel thermal noise in devices with L ≤0.13 m)
Negligible contributions from parasitic resistances
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
31
Annealing
-4
10
100
-5
10
90 nm
before irradiation
100 Mrad
after annealing before irradiation
100 Mrad
after annealing
-5
10
10-6
10
-7
-4
130 nm
10
100
I [A]
D
1/2
Noise Voltage Spectrum [nV/Hz ]
I [A] [nV/Hz 1/2]
Noise Voltage Spectrum
D
In 90 nm transistors, contribution from sidewall leakage to the drain current
disappears. Removal of radiation-induced positive charge from STI oxide
switches off the lateral parasitic transistor and cancels its noise contribution.
Annealing is instead only partially effective in 130 nm devices.
before irradiation
1100 krad
after annealing
before irradiation
100 Mrad
after annealing
-6
1010
core 90 nm NMOS
W/L = 100/0.35
core NMOS 90 nm
W/L = 1000/0.13
I = 50 A @ V = 0.6 V
0.1DS 0.15
0.2
1 0 D 0.05
3
4
5
6
10
10
10VGS [V]10
10
Frequency [Hz]
0.25
7
10
0.3
core
NMOS
nm
core
130 130
nm NMOS
W/L
= 1000/0.35
W/L
= 1000/0.35
I = 50 A @ V = 0.6 V
0.1DS 0.15
0.2
0.25
0.3
10 D 0.05
3
4
5
6
7
10
10
10 [V] 10
10
V
-7
10
GS
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
32
1/f noise: gate stack fabrication process
1/f noise is systematically larger (not very sizably) in 90 nm Foundry B
devices as compared with Foundry A transistors (see very different
behavior of the gate leakage current: different level of nitridation in
the oxide?).
100
10
I = 100 A
D
90 nm NMOS
1
3
10
4
10
10
5
Frequency [Hz]
6
10
W/L = 600/0.5, Foundry B
W/L = 600/0.5, Foundry A
1/2
Noise Voltage Spectrum [nV/Hz ]
W/L = 200/0.35, Foundry B
W/L = 200/0.35, Foundry A
1/2
Noise Voltage Spectrum [nV/Hz ]
100
7
10
10
I = 100 A
D
90 nm NMOS
1
3
10
10
4
5
10
6
10
7
10
10
Frequency [Hz]
V. Re – 11th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, 2009
33
8