Computer Architecture I: Digital Design
Dr. Robert D. Kent
Logic Design
Medium Scale Integration and
Programmable Logic Devices
Part II
Review
• At the outset of designing a complex system, such as a modern
computer or network, it is clear that design is extraordinarily
difficult and computationally challenging when performed at the
level of fundamental Boolean logic gates.
• For these reasons modern design approaches are based on
hierarchical, component based methods.
– Leading to simplified, localized component design,
– lowering of design costs,
– shifting some aspects of design to the component interface (the
compatibility problem).
• We now continue our study of MSI circuits to better understand
this process of MSI design.
Goals
• We continue our study of simple, but functional Combinational
circuits:
– we continue constructing a small library of useful components
– through study of the solution process using Boolean algebra and
Boolean calculus (simplification, etc.) we better understand the
meaning of SSI design
– we seek to identify these components for their re-use potential
– through our study we will better understand how MSI increases the
level of abstraction in solving problems - SSI design is relatively
concrete.
Circuit # 4 : Binary Subtractor
Circuit # 4 : Binary Subtractor
• Before proceeding to design a subtractor circuit, consider a few
examples of the operation D = X - Y:
• Example 1 :
Example 1 :
Considered “easy”
because:
X
0 0 1 1
1-1 = 0 is easy
-Y
0 0 0 1
1-0 = 1 is easy
=======
0-0 = 0 is easy
0 0 1 0
But .....
D
Circuit # 4 : Binary Subtractor
• Example 2 :
– This is not straightforward – it requires the concept of “borrowing” from
the column on the left.
– Use a trick – add zero! Introduce a borrow constant, B. For an L-bit
representation, B = 2L.
Example 2 :
B= 1 0 0 0 0
X
0 0 1 1
-Y
0 1 0 1
=======
D
1 1 1 0
This is not a
mathematical zero.
Rather, it is a practical
zero since we only use
the low-order 4 bits.
Circuit # 4 : Binary Subtractor
• Example 2 :
– This is not straightforward – it requires the concept of “borrowing” from
the column on the left.
– Use a trick – add zero! Introduce a borrow constant, B. For an L-bit
representation, B = 2L.
Example 2 :
B= 0 1 2 0 0
B= 1 0 0 0 0
X
-Y
0 0 1 1
0 1 0 1
=======
D
Instead of XK – YK, we have
recast this in the form BK +
XK – YK.
1 1 1 0
NOTE: By borrowing from
the left, each successive
borrow digit becomes a 1
until the column which
forces the first borrow. This
specific borrow digit has the
value 2 (binary 10).
Circuit # 4 : Binary Subtractor
• Example 2 :
– This is not straightforward – it requires the concept of “borrowing” from
the column on the left.
– Use a trick – add zero! Introduce a borrow constant, B. For an L-bit
representation, B = 2L.
Now we note that we have
already borrowed from this
Example 2 :
column (in the next-to-right
B= 0 1 2 0 0
column).
B= 1 0 0 0 0
X
0 0 1 1
-Y
0 1 0 1
=======
D
1 1 1 0
But we also had to borrow
from the next-to-left column.
Hence, we borrow a ‘2’ from
the left, then borrow ‘1’ from
this ‘2’ to the right, the net
result is to add ‘1’ to the
current column.
The rest of the subtraction
(+2-1+0-0)=1 is easy.
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
YK
BK
DK
BK+1
XK and YK are the inputs for
(XK-YK) and DK is the difference
(within the K’th column)
BK refers to the amount of
borrowing already performed
(in order to carry out a
subtraction in the next-to-right
column)
BK+1 refers to the amount of
borrowing that must be done
from the next-to-left column (in
order to carry out a subtraction
in the current K’th column)
NOTE: It is understood that a
‘1’ denotes a borrow of ‘2’ in
the current K’th column.
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
YK
0
BK
0
DK
0
BK+1
0
-
0
0
XK minuend
YK subtrahend
0
DK difference
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
YK
0
BK
0
DK
0
BK+1
0
There is no need
to perform a
“borrow”
operation.
-
0
0
XK minuend
YK subtrahend
0
DK difference
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
YK
0
0
BK
0
1
DK
0
1
BK+1
0
0
-
1
0
0
1
XK minuend
YK subtrahend
BK prior borrow
1
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
YK
0
0
BK
0
1
DK
0
1
BK+1
0
0
Assume that a “borrow” was
required in a previous column
subtraction - then we must
subtract 1 from the minuend in
this column.
-
1
0
0
1
XK minuend
YK subtrahend
BK prior borrow
1
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
YK
0
0
BK
0
1
DK
0
1
BK+1
0
1
If the subtraction cannot be
performed, then we must
“borrow” from the next
column. We note this borrow
as BK+1 , and then use the
value 2 (!) for the minuend,
XK .
2
0
0
1
-
1
1
XK minuend
YK subtrahend
BK prior borrow
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
YK
0
0
1
BK
0
1
0
DK
0
1
1
BK+1
0
1
1
-
1
0
1
XK minuend
YK subtrahend
1
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
YK
0
0
1
BK
0
1
0
DK
0
1
1
BK+1
0
1
1
If the subtraction cannot be
performed, then we must
“borrow” from the next
column. We note this borrow
as BK+1 , and then use the
value 2 (!) for the minuend,
XK .
2
0
1
-
1
1
XK minuend
YK subtrahend
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
YK
0
0
1
1
BK
0
1
0
1
DK
0
1
1
0
BK+1
0
1
1
1
-
1
0
1
1
XK minuend
YK subtrahend
BK prior borrow
0
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
YK
0
0
1
1
BK
0
1
0
1
DK
0
1
1
0
BK+1
0
1
1
1
If the subtraction cannot be
performed, then we must
“borrow” from the next
column. We note this borrow
as BK+1 , and then use the
value 2 (!) for the minuend,
XK .
2
0
1
1
-
0
1
XK minuend
YK subtrahend
BK prior borrow
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
YK
0
0
1
1
0
BK
0
1
0
1
0
DK
0
1
1
0
1
BK+1
0
1
1
1
0
There is no need
to perform a
“borrow”
operation.
-
0
1
0
0
XK minuend
YK subtrahend
BK prior borrow
1
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
YK
0
0
1
1
0
0
BK
0
1
0
1
0
1
DK
0
1
1
0
1
0
BK+1
0
1
1
1
0
0
There is no need
to perform a
“borrow”
operation.
-
0
1
0
1
XK minuend
YK subtrahend
BK prior borrow
0
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
YK
0
0
1
1
0
0
1
BK
0
1
0
1
0
1
0
DK
0
1
1
0
1
0
0
BK+1
0
1
1
1
0
0
0
There is no need
to perform a
“borrow”
operation.
-
0
1
1
0
XK minuend
YK subtrahend
BK prior borrow
0
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
If the subtraction cannot be
performed, then we must
“borrow” from the next
column. We note this borrow
as BK+1 , and then use the
value 2 (!) for the minuend,
XK .
2
1
1
1
-
1
1
XK minuend
YK subtrahend
BK prior borrow
DK difference
BK+1 next borrow
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
• The circuit expressions for the outputs are derived:
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
• The circuit expressions for the outputs are derived:
DK = XK’YK’BK + XK’YKBK’ + XKYK’BK’ + XKYKBK
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
• The circuit expressions for the outputs are derived:
DK = XK’YK’BK + XK’YKBK’ + XKYK’BK’ + XKYKBK
= BK xor XK xor YK
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
DK = BK xor XK xor YK
• The circuit expressions for the outputs are derived:
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
DK = BK xor XK xor YK
• The circuit expressions for the outputs are derived:
BK+1
= XK’YK’BK + XK’YKBK’ + XK’YKBK + XKYKBK
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
DK = BK xor XK xor YK
• The circuit expressions for the outputs are derived:
BK+1
= XK’YK’BK + XK’YKBK’ + XK’YKBK + XKYKBK
= XK’YK(BK + BK’) + XK’(YK + YK’)BK + (XK + XK’)YKBK
Circuit # 4 : Binary Subtractor
• We begin the design by constructing a 3-input/2-output truth table:
XK
0
0
0
0
1
1
1
1
YK
0
0
1
1
0
0
1
1
BK
0
1
0
1
0
1
0
1
DK
0
1
1
0
1
0
0
1
BK+1
0
1
1
1
0
0
0
1
DK = BK xor XK xor YK
BK+1 = XK’YK + XK’BK + YKBK
• The circuit expressions for the outputs are derived:
BK+1
= XK’YK’BK + XK’YKBK’ + XK’YKBK + XKYKBK
= XK’YK(BK + BK’) + XK’(YK + YK’)BK + (XK + XK’)YKBK
Circuit # 4 : Binary Subtractor
• This leads to the expressions:
DK = BK xor XK xor YK
BK+1 = XK’YK + XK’BK + YKBK
• These have the logic gate realizations:
Circuit # 4 : Binary Subtractor
• This leads to the expressions:
DK = BK xor XK xor YK
BK+1 = XK’YK + XK’BK + YKBK
• These have the logic gate realizations:
BK
XK
YK
FS
DK
BK+1
Circuit # 4 : Binary Subtractor
• This leads to the expressions:
DK = BK xor XK xor YK
BK+1 = XK’YK + XK’BK + YKBK
Binary Full Subtractor
• These have the logic gate realizations:
Full Subtractor
FS
BK
BK
XK
YK
FS
DK
XK
YK
DK
BK+1
BK+1
Circuit # 4 : Binary Subtractor
• We can now employ the 1-bit Full Subtractor to construct a multibit subtractor
– we use a FS with B0 = 0 for the first bit.
– this can be replaced with a specialized Half-Subtractor circuit.
BK
XK
YK
FS
DK
BK+1
Circuit # 4 : Binary Subtractor
• We can now employ the 1-bit Full Subtractor to construct a multibit subtractor
– we use a FS with B0 = 0 for the first bit. (This can be replaced with a
specialized Half-Subtractor circuit).
4-bit MSI: Ripple Subtractor
Y3
Y
X3
X
Bout
Y2
Bin
S
S3
Bout
Y
X2
X
Bout
Y1
Bin
S
S2
Y
X1
X
Bout
Y0
Bin
S
S1
Y
X0
X
Bout
0
Bin
S
S0
Circuit # 4 : Binary Subtractor
• We can now employ
the 1-bit
Subtractor
to construct a multi4-bit MSI:
FullFull
Ripple
Subtractor
bit subtractor
Y3 Y2 Y1 Y0
X3 X2 X1 X0
– we use a FS with B0B=out 0 for the first bit. This
Bin can be replaced with a
D3 circuit.
D2 D1 D0
specialized Half-Subtractor
4-bit MSI: Ripple Subtractor
Y3
Y
X3
X
Bout
Y2
Bin
D
D3
Bout
Y
X2
X
Y1
Bin
Bout D
D2
Y
X1
X
Bout
Y0
Bin
D
D1
Y
X0
X
Bout
0
Bin
D
D0
Circuit # 4 : Binary Subtractor
• Note that the Full Adder and Full Subtractor are identical, except
for a single inverter applied to the first input (A or X):
CK
XK
FA
YK
BK
DK
XK
CK+1
YK
Binary Full Adder
DK
BK+1
Binary Full Subtractor
Full Subtractor
FS
FA
Cin
A
B
FS
BK
S
XK
YK
DK
Cout
BK+1
Circuit # 4 : Binary Subtractor
• There are alternative methods to performing subtraction, based on
1’s and 2’s complement representations.
Circuit # 4 : Binary Subtractor
• There are alternative methods to performing subtraction, based on
1’s and 2’s complement representations.
• Since (X - Y) is the same as (X+Y’+1) using 2’s complement
arithmetic, we can use the adder to perform subtraction by adding
inverters to the Y inputs and setting the input carry bit to 1.
Circuit # 4 : Binary Subtractor
• There are alternative methods to performing subtraction, based on
1’s and 2’s complement representations.
• Since (X - Y) is the same as (X+Y’+1) using 2’s complement
arithmetic, we can use the adder to perform subtraction by adding
inverters to the Y inputs and setting the input carry bit to 1.
Y3 Y2 Y1 Y0
Cout
X3 X2 X1 X0
4-bit MSI
Full Ripple Adder
S3
S2
S1
S0
Cin
1
Circuit # 5 : Binary Adder/Subtractor
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
Proof: 0 xor 1 = 1 = 0’
1 xor 1 = 0 = 1’
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
A xor 0 = A
Proof: 0 xor 1 = 1 = 0’
1 xor 1 = 0 = 1’
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
Proof: 0 xor 1 = 1 = 0’
A xor 0 = A
Proof: 0 xor 0 = 0
1 xor 1 = 0 = 1’
1 xor 0 = 1
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
Proof: 0 xor 1 = 1 = 0’
A xor 0 = A
Proof: 0 xor 0 = 0
• These properties of the
xor gate allow us to
construct a circuit that
can perform either
addition or subtraction:
1 xor 1 = 0 = 1’
1 xor 0 = 1
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
Proof: 0 xor 1 = 1 = 0’
A xor 0 = A
Proof: 0 xor 0 = 0
• These properties of the
xor gate allow us to
construct a circuit that
can perform either
addition or subtraction:
Y3
Y2
1 xor 1 = 0 = 1’
1 xor 0 = 1
Y1
Y0
X3 X2 X1 X0
4-bit MSI
Full Ripple
Adder/Subtractor
S3
S2
S1
S0
Add(0)/
Sub(1)
Circuit # 5 : Binary Adder/Subtractor
• Finally, we note the following facts about the xor gate:
A xor 1 = A’
A xor 0 = A
The input carry bit
is used as a toggle
Proof: 0 xor 1 = 1 = 0’
1 xor the
1 = 0 = 1’
to control
choice of addition
subtraction.
Proof: 0 xor 0 = 0 or
1 xor
0=1
• These properties of the
xor gate allow us to
construct a circuit that
can perform either
addition or subtraction:
Y3
Y2
Y1
Y0
X3 X2 X1 X0
+/- +/- +/- +/-
4-bit MSI
Full Ripple
Adder/Subtractor
S3
S2
S1
S0
Add(0)/
Sub(1)
Circuit # 5 : Binary Adder/Subtractor
• Now that it has been demonstrated that subtraction can be carried
out using addition circuits, we may henceforth treat only addition
cases, without any loss of generality.
Y3
Y2
Y1
Y0
X3 X2 X1 X0
+/- +/- +/- +/-
4-bit MSI
Full Ripple
Adder/Subtractor
S3
S2
S1
S0
Add(0)/
Sub(1)
Circuit # 6 : Carry Lookahead Adder
Circuit # 6 : Carry Lookahead Adder
• The representation of the Carry-out circuit for the full adder is:
CK+1 = XK YK + CK XK + CK YK
= XK YK + CK (XK + YK)
Circuit # 6 : Carry Lookahead Adder
• The representation of the Carry-out circuit for the full adder is:
CK+1 = XK YK + CK XK + CK YK
= XK YK + CK (XK + YK)
• Define terms:
gK = XK YK
• We may now write:
CK+1 = gK + CK pK
and,
pK = (XK + YK)
Circuit # 6 : Carry Lookahead Adder
• The representation of the Carry-out circuit for the full adder is:
CK+1 = XK YK + CK XK + CK YK
= XK YK + CK (XK + YK)
• Define terms:
gK = XK YK
and,
pK = (XK + YK)
• We may now write:
CK+1 = gK + CK pK
• Also, recall that the sum bit is generated using the expression:
SK =
CK xor AK xor BK
Circuit # 6 : Carry Lookahead Adder
• Using the expressions:
CK+1 = gK + CK pK
SK =
CK xor AK xor BK
We define the Sigma-block circuit:
XK YK CK
PK
GK
SK
Circuit # 6 : Carry Lookahead Adder
• Using the expressions:
CK+1 = gK + CK pK
SK =
XK YK CK
CK xor AK xor BK
We define the Sigma-block circuit:
• This may be abbreviated as the MSI
component:
XK YK CK
SIG
PK
GK
SK
PK
GK
SK
Circuit # 6 : Carry Lookahead Adder
• Using the expressions:
Note that both P
CK+1 = gK and
+ CKGponly
K
require evaluation
SK = ofCKone
r logic
AK r
BK
gate.
We define the Sigma-block circuit:
• This may be abbreviated as the MSI
component:
XK YK CK
SIG
PK
GK
SK
XK YK CK
PK
GK
SK
Circuit # 6 : Carry Lookahead Adder
• These results suggest that the previous ripple-adder circuit may be
replaced by the following circuit, using Sigma-blocks:
C0
Carry lookahead network
C4
X3 Y3 C3
X2 Y2 C2
X1 Y1 C1
X0 Y0 C0
SIG
SIG
SIG
SIG
P3
G3
P2
S3
G2
P1
S2
G1
P0
S1
G0
S0
Circuit # 6 : Carry Lookahead Adder
• Expanding the carry terms for a 4-bit adder:
C1 = g0 + C0 p0
C2 = g1 + C1 p 1
= g1 + (g0 + C0 p0 )p1
= g1 + g0 p 1 + C 0 p 0 p1
C3 = g2 + C2 p2
= g2 + g1 p 2 + g 0 p 1 p2 + C 0 p0 p 1 p2
C4 = g3 + C3 p3
= g3 + g2 p 3 + g 1 p 2 p3 + g 0 p1 p 2 p3 + C 0 p0 p 1 p2 p 3
Circuit # 6 : Carry Lookahead Adder
• Expanding the carry terms for a 4-bit adder:
C1 = g0 + C0 p0
C2 = g1 + C1 p 1
= g1 + (g0 + C0 p0 )p1
Note that all the carry
expressions require
only two evaluation
stages (one for the
and, the other for the
or).
= g1 + g0 p 1 + C 0 p 0 p1
C3 = g2 + C2 p2
= g2 + g1 p 2 + g 0 p 1 p2 + C 0 p0 p 1 p2
C4 = g3 + C3 p3
= g3 + g2 p 3 + g 1 p 2 p3 + g 0 p1 p 2 p3 + C 0 p0 p 1 p2 p 3
Circuit # 6 : Carry Lookahead Adder
• These results can now be used to complete the Carry lookahead
network portion of the 4-bit adder:
C0
Carry lookahead network
C4
X3 Y3 C3
X2 Y2 C2
X1 Y1 C1
X0 Y0 C0
SIG
SIG
SIG
SIG
P3
G3
P2
S3
G2
P1
S2
G1
P0
S1
G0
S0
Circuit # 6 : Carry Lookahead Adder
• These results can now be used to complete the Carry lookahead
network portion of the 4-bit adder:
Carry lookahead network
C0
C4
P3
G3
C3
P2
G2
C2
P1
G1
C1
P0
G0
Circuit # 6 : Carry Lookahead Adder
Now it is clear that
evaluation
of each
carry the Carry lookahead
• These results can
now be used
to complete
requires,
at most,
network portion
of the 4-bit
adder:3 logic
gates. Thus, each sum
digit requires at most 4
Carry lookahead network
logic gates.
C4
P3
G3
C3
P2
G2
C2
P1
G1
C1
P0
G0
C0
Circuit # 6 : Carry Lookahead Adder
• This brings us back to the basic, 4-bit MSI Adder/Subtractor,
which may now be assumed to be optimized with carry lookahead
circuits.
• These may be used, in turn, to develop more powerful multi-bit
adder/subtractors.
Y3
Cout
Y2
Y1
Y0
X3 X2 X1 X0
4-bit MSI
Full
Adder/Subtractor
S3
S2
S1
S0
Add(0)/
Cin
Sub(1)
Circuit # 7 : Decimal Adder
Circuit # 7 : Decimal Adder
• There are many situations where it is useful to employ decimal
arithmetic on decimal representations (e.g. BCD: 8421).
– BCD:
0
1
2
7
8
9
0000, 0001, 0010, … , 0111, 1000, 1001
Remind yourself that BCD uses a 4-bit
representation to store the values of
digits 0..9, but this leaves wastage of
some bit patterns (unused patterns).
Circuit # 7 : Decimal Adder
• There are many situations where it is useful to employ decimal
arithmetic on decimal representations (e.g. BCD: 8421).
– BCD:
0
1
2
7
8
9
0000, 0001, 0010, … , 0111, 1000, 1001
• To illustrate some of the issues we consider one example of
decimal addition of single digits, leading to a full decimal adder.
– This design will be based on the use of the binary adder.
Circuit # 7 : Decimal Adder
• Note that the problem of adding two decimal digits together, in
general, also requires accounting for an input carry and an output
carry.
Minimum Sum:
0 (No carry)
0
+ 0
0
(No Carry out)
DECIMAL ARITHMETIC
Maximum Sum:
+
1
9
9
19
(Carry)
(Carry out)
• Note also that the maximum number of distinct sums is 20.
Circuit
#
7
:
Decimal
Adder
Consider the example:
• Note that the problem
of adding1110
two decimal digits together, in
Carry
general, also requires accounting for an input carry and an output
999
carry.
+ 99
Minimum Sum:
+
0
0
0
0
Sum
====
Maximum Sum:
1998
(No carry)
DECIMAL ARITHMETIC
+
1
9
9
19
(Carry)
(Carry out)
• Note that the maximum number of distinct sums is 20.
Circuit # 7 : Decimal Adder
• We can obtain the sums
in two stages.
Circuit # 7 K: Decimal
Adder
P P P P
3
• We can obtain the sums
in two stages.
• First, list all possible
outputs from the direct
sum of the decimal
digits, then …..
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Direct sum of
decimal digits,
ranging from
0 to 1910,
represented in 5bit form with highorder bit K.
Circuit # 7 K: Decimal
Adder
P P P P
C
3
2
1
• We can obtain the sums
0 0 0 0 0
0 0 0 0 1
in two stages.
0 0 outputs,
0 1 0
Expected
0 0 0 1 1
with0 sum
0 1bits
0 S
0J
• First, list all possible and carry-out
0 0 1 0bit1C.
0 0 1 1 0
outputs from the direct
0 0 1 1 1
sum of the decimal
0 1 0 0 0
0 1 0 0 1
digits, then …..
• Beside each sum place
the expected values of
the sum bits and the
carry out bit.
S 3 S2
S1 S 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
Circuit # 7 K: Decimal
Adder
P P P P
C
3
• The first-stage sums
divide into two groups:
– the first ten sums
produce the correct
final sum and carry
bit patterns
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
S 3 S2
S1 S 0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Circuit # 7 K: Decimal
Adder
P P P P
C
3
• The first-stage sums
divide into two groups:
– the first ten sums
produce the correct
final sum and carry
bit patterns
– the last ten sums
are all incorrect by
the same amount,
they should have
6 added to them to
produce the correct
final bit patterns.
2
1
0
S 3 S2
S1 S 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
Circuit # 7 K: Decimal
Adder
P P P P
C
3
• The first-stage sums
divide into two groups:
– the first ten sums
produce the correct
final sum and carry
bit patterns
– the last ten sums
are all incorrect by
the same amount,
they should have
6 added to them to
produce the correct
final bit patterns.
2
1
0
S 3 S2
S1 S 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
+6=
+6=
Circuit # 7 K: Decimal
Adder
P P P P
C
3
• The condition used to
identify and control the
correction process is
expressed in terms of
the carry-out bit, C:
C = K + P3 P2 + P3 P1
2
1
0
S 3 S2
S1 S 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
Circuit # 7 K: Decimal
Adder
P P P P
C
3
• The condition used to
identify and control the
correction process is
expressed in terms of
the carry-out bit, C:
C = K + P3 P2 + P3 P1
• Thus, if C = 0 then no
correction is applied.
2
1
0
S 3 S2
S1 S 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
Circuit # 7 K: Decimal
Adder
P P P P
C
3
2
1
0
• The condition used to
0 0 0 0 0
0
0 0 0 0 1
0
identify and control the
0 0 0 1 0
0
correction
process
is
0 “Excess-64”
1 1
0
This
is referred
to00as00the
1 0 0
0
expressed in terms
of
technique for0 BCD
0 1 addition.
0 1
0
the carry-out bit, C:
0 0 1 1 0
0
C = K + P3 P2 + P3 P1
• Thus, if C = 0 then no
correction is applied.
• If C = 1, then 6 is added
directly to the initial sum
bits PJ .
S 3 S2
S1 S 0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
+6=
+6=
Circuit # 7 : Decimal Adder
• The condition used to
identify and control the
correction process is
expressed in terms of
the carry-out bit, C:
A3 A2 A1 A0
K
B 3 B 2 B1 B0
x3 x2 x1 x0 y3 y 2 y 1 y0
C4 4-bit binary adder C0
s 3 s2 s1 s 0
P3 P2
Cout
P1 P0
C = K + P3 P2 + P3 P1
• A decimal full-adder
circuit follows using
a two-stage 4-bit binary
adder MSI circuit and
• Uses the carry bit value
directly to generate the
value 610, or 01102.
Add 6
0
x3 x2 x1 x0 y3 y2 y 1 y0
C4 4-bit binary adder C0
s 3 s2 s1 s 0
S3
S2
S1 S0
Cin
Circuit # 7 : Decimal Adder
• This MSI circuit is used
to form the basis for a
multi-decade decimal
adder.
A3 A2 A1 A0
x3 x2 x1 x0 y3 y 2 y 1 y0
C4 4-bit binary adder C0
s 3 s2 s1 s 0
K
P3 P2
Cout
A3 A2 A1 A0
Add 6
x3 x2 x1 x0 y3 y2 y 1 y0
C4 4-bit binary adder C0
C0
s 3 s2 s1 s 0
S3
S2
P1 P0
B 3 B2 B1 B0
0
x3 x2 x1 x0 y3 y2 y 1 y0
C4
BCD Decade adder
s 3 s2 s1 s0
S3
B 3 B 2 B1 B0
S1
S0
S2
S1 S0
Cin
Time out for some Design Philosophy!
Time out for some Philosophy!
• In software design and construction the programmer/analyst
becomes familiar with identifying different aspects of the problem
in terms of abstract models.
• Some of these models are quite concrete (bottom-up design) while
others are relatively more abstract and require gradual expression
of their detail (top-down design).
Time out for some Philosophy!
• Increasingly, modern Software Design is expressed in terms of
components (functions, classes/objects, templates,
metaprogramming) and focuses on software component re-use.
• One critical problem of software re-use lies in the proper, robust,
flexible and standards-based design of the component interfaces.
• Other issues arise in the contexts of software complexity,
performance, cost and other factors.
Time out for some Philosophy!
• Differential layering of abstraction in design also has its place in
hardware design.
SSI:
Boolean algebra / Simplification / Logic gates
MSI: Interconnection networks / Iterative re-use / Components
• These differences have been demonstrated in each of the
circuits/components that we have considered so far.
Time out for some Philosophy!
• Differential layering of abstraction inAdesign
alsoB3has
its
place in
B2 B
3 A2 A1 A0
1 B0
hardware design.
x3 x2 x1 x0 y3 y2 y 1 y0
C4 4-bit binary adder C0
Simplification
/sLogic
gates
s2 s1 s0
3
K
Cin
SSI:
Boolean algebra /
MSI:
P2 P1 P0
Cout
Interconnection networks
/ IterativeP3 re-use
/ Components
• These differences
Binary Full Adderhave been demonstrated in each of the
Add 6
circuits/components
that we have considered so far.
FA
0
Cin
A
B
S
Cout
x3 x2 x1 x0 y3 y2 y 1 y0
C4 4-bit binary adder C0
s 3 s2 s1 s0
S3
S2
S1 S0
Circuit # 8 : Comparator
Circuit # 8 : Comparator
• The comparison of two (binary) numbers is of considerable
importance.
– if ( A < B ) then …
– while ( A > B ) do ...
Circuit # 8 : Comparator
• The comparison of two (binary) numbers is of considerable
importance.
– if ( A < B ) then …
– while ( A > B ) do ...
• It is possible to design a comparator circuit that establishes whether
two input binary strings, A and B, satisfy the conditions:
A=B
A>B
A<B
Circuit # 8 : Comparator
• The comparison of two (binary) numbers is of considerable
importance.
– if ( A < B ) then …
– while ( A > B ) do ...
• It is possible to design a comparator circuit that establishes whether
two input binary strings, A and B, satisfy the conditions:
A=B
A>B
A<B
These conditions may be encoded using 3 flag bits:
E=1
G=1
L=1
Circuit # 8 : Comparator
• One strategy is to perform the comparison bit-wise and from right
to left.
Circuit # 8 : Comparator
• One strategy is to perform the comparison bit-wise and from right
to left.
• Express the two bit strings to be compared, A and B:
AN … AK AK-1 … A1 A0
and
BN … BK BK-1 … B1 B0
Circuit # 8 : Comparator
• One strategy is to perform the comparison bit-wise and from right
to left.
• Express the two bit strings to be compared, A and B:
AN … AK AK-1 … A1 A0
and
BN … BK BK-1 … B1 B0
• Now, restrict attention to the substrings:
AK AK-1 … A1 A0
and
BK BK-1 … B1 B0
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
AK-1 … A1 A0 = BK-1 … B1 B0
EK-1 = 1 , GK-1 = 0 , LK-1 = 0
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
AK-1 … A1 A0 = BK-1 … B1 B0
EK-1 = 1 , GK-1 = 0 , LK-1 = 0
AK-1 … A1 A0 > BK-1 … B1 B0
EK-1 = 0 , GK-1 = 1 , LK-1 = 0
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
AK-1 … A1 A0 = BK-1 … B1 B0
EK-1 = 1 , GK-1 = 0 , LK-1 = 0
AK-1 … A1 A0 > BK-1 … B1 B0
EK-1 = 0 , GK-1 = 1 , LK-1 = 0
AK-1 … A1 A0 < BK-1 … B1 B0
EK-1 = 0 , GK-1 = 0 , LK-1 = 1
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
AK-1 … A1 A0 = BK-1 … B1 B0
EK-1 = 1 , GK-1 = 0 , LK-1 = 0
AK-1 … A1 A0 > BK-1 … B1 B0
EK-1 = 0 , GK-1 = 1 , LK-1 = 0
AK-1 … A1 A0 < BK-1 … B1 B0
EK-1 = 0 , GK-1 = 0 , LK-1 = 1
• Note that only one of EK-1, GK-1 or LK-1 may have value 1 at a time.
Circuit # 8 : Comparator
• We begin with three distinct, possible assumptions:
AK-1 … A1 A0 = BK-1 … B1 B0
EK-1 = 1 , GK-1 = 0 , LK-1 = 0
AK-1 … A1 A0 > BK-1 … B1 B0
EK-1 = 0 , GK-1 = 1 , LK-1 = 0
AK-1 … A1 A0 < BK-1 … B1 B0
EK-1 = 0 , GK-1 = 0 , LK-1 = 1
• Note that only one of EK-1, GK-1 or LK-1 may have value 1 at a time.
• Our goal is to derive expressions for outputs EK, GK and LK based
on the inputs AK , BK , EK-1 , GK-1 and LK-1 .
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
AK
0
0
0
0
0
0
1
1
1
1
1
1
BK
0
0
0
1
1
1
0
0
0
1
1
1
EK-1
0
0
1
0
0
1
0
0
1
0
0
1
GK-1
0
1
0
0
1
0
0
1
0
0
1
0
LK-1
1
0
0
1
0
0
1
0
0
1
0
0
EK
0
0
1
0
0
0
0
0
0
0
0
1
GK
0
1
0
0
0
0
1
1
1
0
1
0
LK
1
0
0
1
1
1
0
0
0
1
0
0
• Note that all other (missing) rows are represented using don’t care output
values.
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
AK
0
0
0
0
0
0
1
1
1
1
1
1
BK
0
0
0
1
1
1
0
0
0
1
1
1
EK-1
0
0
1
0
0
1
0
0
1
0
0
1
GK-1
0
1
0
0
1
0
0
1
0
0
1
0
LK-1
1
0
0
1
0
0
1
0
0
1
0
0
EK
0
0
1
0
0
0
0
0
0
0
0
1
GK
0
1
0
0
0
0
1
1
1
0
1
0
LK
1
0
0
1
1
1
0
0
0
1
0
0
Condition is not
altered when
AK = BK
Condition is not
altered when
AK = BK
• Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
AK
0
0
0
0
0
0
1
1
1
1
1
1
BK
0
0
0
1
1
1
0
0
0
1
1
1
EK-1
0
0
1
0
0
1
0
0
1
0
0
1
GK-1
0
1
0
0
1
0
0
1
0
0
1
0
LK-1
1
0
0
1
0
0
1
0
0
1
0
0
EK
0
0
1
0
0
0
0
0
0
0
0
1
GK
0
1
0
0
0
0
1
1
1
0
1
0
LK
1
0
0
1
1
1
0
0
0
1
0
0
Condition LK = 1
always applies
when
AK < BK
• Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• Construct an abbreviated truth-table:
AK
0
0
0
0
0
0
1
1
1
1
1
1
BK
0
0
0
1
1
1
0
0
0
1
1
1
EK-1
0
0
1
0
0
1
0
0
1
0
0
1
GK-1
0
1
0
0
1
0
0
1
0
0
1
0
LK-1
1
0
0
1
0
0
1
0
0
1
0
0
EK
0
0
1
0
0
0
0
0
0
0
0
1
GK
0
1
0
0
0
0
1
1
1
0
1
0
LK
1
0
0
1
1
1
0
0
0
1
0
0
Condition GK = 1
always applies
when
AK > BK
• Note that all other (missing) rows are represented using don’t care output values.
Circuit # 8 : Comparator
• This leads to Boolean expressions for the outputs (using don’t cares):
AK
0
0
0
0
0
0
1
1
1
1
1
1
BK
0
0
0
1
1
1
0
0
0
1
1
1
EK-1
0
0
1
0
0
1
0
0
1
0
0
1
GK-1 LK-1
EK
GK LK
0
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0GK =1 AK BK + AK0 GK-10 + B1K GK-1
1
0
0
0
1
0E =0 A B E 0 + A0 B 1E
K
K
K
K-1
K
K
K-1
0
1
0
1
0
1
0
0
1
0
LK = AK BK + AK LK-1 + BK LK-1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
0
1
0
0
Circuit # 8 : Comparator
• The 1-bit comparator circuit is expressed:
AK
BK
GK-1
GK
EK-1
EK
LK-1
LK
Circuit # 8 : Comparator
• The 1- bit comparator circuit is expressed in MSI form:
AK BK
GK
EK
LK
1-bit
C
o
m
p
a
r
a
t
o
r
GK-1
EK-1
LK-1
Circuit # 8 : Comparator
As with previous
• The 1- bit comparator circuit is expressed in MSI form: circuits, the 1-bit
comparator circuit
can be extended to
form multi-bit, MSI
ripple comparators.
GK
EK
LK
AK BK
AK-1 BK-1
1-bit
C
o
m
p
a
r
a
t
o
r
1-bit
C
o
m
p
a
r
a
t
o
r
GK-1
EK-1
LK-1
GK-2
EK-2
LK-2
Summary - Part II
• We continue to study logic design in the contexts of Small Scale Integration
(SSI) and Medium Scale Integration (MSI) of gate devices and programmable
logic devices (PLD).
• We have studied the design of a number of specific, practical functional
circuits with a view to re-using those circuits as components in MSI design.
Adders
Subtractors
Comparator
• We note the differing design approaches, or emphases, effected by differential
layering of abstraction. (The same design issue arises in the context of
software engineering as well.)
SSI:
Boolean algebra / Simplification / Logic gates
MSI:
Interconnection networks / Iterative re-use / Components