DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
UNIVERSITI MALAYSIA PERLIS
DKT 212/3 :
DIGITAL SYSTEM II
Lab 1 : Flip – Flops
Name
:
Matrix No.
:
Program
:
Date
:
School of Computer and Communication Engineering
Universiti Malaysia Perlis
DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
LAB 1: FLIP-FLOPS
OBJECTIVES
1. To construct the basic circuit of latches and flip-flops using basic gates.
2. To investigate the operation of latches and flip-flops.
3. To determine the input and output states of the circuits constructed.
EQUIPMENTS/COMPONENTS
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Power Supply of 5V DC output
Multimeter
Function generator
Bread Boards
Logic ICs : 7402(1pc), 7408(1pc), 7432(1pc), 7476(1pc)
Light Emitting Diode (4pc)
Resistors : 330Ω (4pc)
Toggle Switches (4pc)
INTRODUCTION
In DKT 112-Digital System I, you have studied forms of combinational logic. So, for this
session you will introduce the fundamentals of sequential logic. You will be introduced to
two types of device which perform the basis of multi-vibrators such as bi-stable, monostable and a-stable and memory elements like registers. The two categories of device which
are bi-stable are the latches and the flip-flop. A bi-stable device means that it has two stable
states called SET and RESET; in which they can retain either of these states indefinitely,
making bi-stable devices useful to be functioned as storage devices.
The latch and flip-flop are basic elements that are able to store binary information. Even
though they are made up of combinational logic gates that have no storage capability, the
way they are connected permits information to be stored. Both have basic feedback design
circuits but the differences between the latch and the flip-flop is how it can be triggered to
change their outputs between the two states.
This lab, will introduce you the design to build your own latch and flip-flops. You will
construct, examine and verify its operations individually. Finally you will determine the
actual difference between the two fundamental devices.
School of Computer and Communication Engineering
Universiti Malaysia Perlis
DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
PROCEDURE
1. R-S flip-flop: Construct a circuit as shown in Figure 1.1. Connect switches to the input
and complete Table 1.1 given by monitoring the output using the LED display.
Figure 1.1 : NOR-Gate in Logic IC - 7402
2. Make a modification on the previous circuit by connecting the circuit as illustrated at
Figure 1.2. Connect another switch for the CLK input and complete Table 1.2 given in
last pages.
Figure 1.2 : NOR-Gate in Logic IC – 7402 and AND-Gate in Logic IC-7408
3. J-K flip-flop: Combine the circuit constructed in procedure 2 with gate AND as shown
in Figure 1.3. Perform the following series of test on the circuit by completing Table 1.3
in data sheet.
Figure 1.2
Figure 1.3 : Combination of RS Flip-Flops with AND-Get (Logic IC-7408)
can embedded as Logic IC-7476
School of Computer and Communication Engineering
Universiti Malaysia Perlis
DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
4. Figure 1.4 shows IC 7476 which is a JK flip-flop. Verify the operation of JK flip-flop by
ignoring the PRE and CLR input. Fill in the results at Table 1.4 in data sheet.
Figure 1.4 : Logic Symbol for JK Flip-Flops (Logic IC-7476)
5. D flip-flop: Connect an inverter to the input K of flip-flop JK as illustrated in
Figure 5.6 and complete Table 1.5.
Figure 1.5 : Combination of Logic Symbol for JK Flip-Flops (Logic IC-7476)
with NOT-gate(Logic IC-7432)
School of Computer and Communication Engineering
Universiti Malaysia Perlis
DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
REPORT REQUIREMENT
The Lab report should include the following:

The report should briefly describe : o summary of each experiment done,
o discussions for comparison between experiment result and theory result,
o remarks any possible failures during the laboratory session,
o step have done to overcome that problem,

The proposal should not be more than 4 pages (without front pages
[name/matrix/program/lecturer name etc], Arial Font and Size12 .
If Late submitted , marks will deducted.

School of Computer and Communication Engineering
Universiti Malaysia Perlis
DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
DKT 212 DIGITAL SYSTEM II
NAME: ____________________________________
MATRIX NO.: ________________________
COURSE:__________________________________
TABLE NO.:
Input
Output
R
S
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
0
Q
Input
Q
R
S
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Table 1.1
Remarks: _____________________
J
1
1
0
0
0
0
1
1
1
________________________
Input
Output
K
CLK
Q
0
0
0
1
0
0
0
1
1
0
1
1
1
0
1
1
1
0
Table 1.3 :
Remarks:___________________
School of Computer and Communication Engineering
Output
CLK
Q
0
1
0
1
0
1
0
1
Table 1.2
Remarks:___________________
J
1
1
0
0
0
0
1
1
1
Input
K
0
0
0
0
1
1
1
1
1
Output
CLK
Q
0
1
0
1
0
1
0
1
0
Table 1.4
Remarks:___________________
Universiti Malaysia Perlis
Q
DKT 212 - DIGITAL SYSTEMS II
LAB 1 : FLIP-FLOPS
Input
Output
D
CLK
1
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
Q
Q
Table 1.5
Remarks:___________________
School of Computer and Communication Engineering
Universiti Malaysia Perlis