IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
417
Efficient Boolean Characteristic Function for Timed
Automatic Test Pattern Generation
Yu-Min Kuo, Student Member, IEEE, Yue-Lung Chang, and Shih-Chieh Chang, Member, IEEE
Abstract—Timing analysis is critical for many circuit optimizations. An accurate timing analysis can be achieved by finding input
vectors that simultaneously satisfy both functional and temporal
requirements. The problem of finding such input vectors can be
modeled as a Boolean equation called the timed characteristic
function (TCF). Despite the usefulness of the TCF, traditional TCF
construction and solving is slow for large circuits. In this paper,
we present a more efficient way to use the TCF. On average, our
method is much faster than other most recent works.
Fig. 1. Example of a combinational circuit.
Index Terms—Boolean function, logic design, modeling, timed
characteristic function (TCF), timing analysis.
I. I NTRODUCTION
A
CCURATE timing analysis is extremely important for an
advanced very large scale integration design. Most previous papers in timing analysis attempt to estimate the delay of
a circuit pessimistically by taking false paths into account [3],
[4], [12], [15], [17], [18]. However, applications such as those
in [4], [6], [8], [10], and [11] require input vectors that, when
evaluated, can meet some functional and temporal requirements
simultaneously. In addition, the temporal requirement is not
necessarily limited to the longest delay of the circuit. The
problem of finding input vectors that satisfy functional and
temporal requirements simultaneously is normally referred to
as timed automatic test pattern generation or timed ATPG [4],
[20], [21], [22]. For example, in Fig. 1, each node has the delay
of 1. Given the objective of finding an input vector such that
output r is 0 and r is stable later than time t = 5, an input vector
(a, b, e, g, j, m, o) = (1, 0, 1, 1, 0, 1, 0) may be returned. It can
sensitize a path from node a to node r with delay = 7 in the
floating mode of operation shown in Fig. 2. We observe that
input vector (1, 0, 1, 1, 0, 1, 0) satisfies not only the functional
requirement, r = 0, but also the temporal requirement, for r to
be stable later than time t = 5.
Several previous papers specify the need for an input vector
generator or timed ATPG as a core engine to solve problems
related to timing analysis. For example, crosstalk analysis
requires knowing whether a transition at some time instant
Manuscript received March 7, 2008; revised June 14, 2008 and September 5,
2008. Current version published February 19, 2009. This work was supported
by the R.O.C. National Science Council under Grants NSC 97-2220-E-007041 and NSC 96-2220-E-007-006. This paper was recommended by Associate
Editor I. Markov.
Y.-M. Kuo and S.-C. Chang are with the Department of Computer Science,
National Tsing Hua University, Hsinchu 300, Taiwan (e-mail: ymkuo@cs.
nthu.edu.tw; [email protected]).
Y.-L. Chang is with Globalunichip, Inc., Hsinchu 300, Taiwan (e-mail:
[email protected]).
Digital Object Identifier 10.1109/TCAD.2009.2013269
Fig. 2. Input vector satisfies the objective of finding output r = 0 to be stable
later than time t = 5.
of a line might induce noise on another line. A timed-ATPG
approach is proposed for finding input vectors to activate and
observe the crosstalk effects [10]. A timed-ATPG approach is
reported for finding input vectors to activate the maximum instantaneous current [8]. Moreover, the methods proposed in [4],
[6], and [17] find the delay of a circuit based on timed ATPG.
Traditionally, the path-oriented decision making (PODEM)
algorithm is extended to consider the temporal domain [4].
Backtracking is performed when logic or timing conflicts occur.
Additionally, implications are conducted forward and backward
based on timed calculus, which handles the logic and timing
propagations simultaneously. However, several previous papers
have reported that this PODEM-based method was not scalable
using the PODEM method of implementation. In [1] and [9],
the researchers show that the PODEM-based method cannot
handle large circuits even though the timed ATPG gets better
results than other approaches such as simulated annealing and
genetic algorithms.
An alternative way of finding input vectors is to construct
a Boolean function called the timed characteristic function
(TCF) or characteristic function [13] whose on-set contains
input vectors having a delay greater than a time instant when
evaluated. Let us consider the same example in Fig. 1. The TCF
of node r = 0 to be stable later than time t = 5 is equal to (eg +
eo + j ) · (a b eg + a b ej + a b eo + mo) . Then, the TCF
can be solved by running a satisfiability (SAT) solver [5], [14],
[16], [19] or an ATPG engine on the corresponding TCF. For
example, input vector (a, b, e, g, j, m, o) = (1, 0, 1, 1, 0, 1, 0)
0278-0070/$25.00 © 2009 IEEE
418
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
belongs to the on-set of the aforementioned TCF, and this input
vector causes node r = 0 with delay = 7 in the floating mode
of operation. In [2], the algebraic decision diagram, a data
structure similar to BDD, is proposed to represent the relation
between each input vector and its corresponding output arrival
time. However, the method is not feasible for large circuits due
to the high cost of computation. In [3], [12], [13], [17], [23],
and [24], several recursive formulas are derived based on the
sensitization criteria for the TCF. The functional and temporal
requirements of a node are modeled by a TCF, which can be
recursively constructed.
In this paper, we propose effective ways to model the TCF,
which dramatically speed up the run time. We also demonstrate
that our algorithm can derive more compact TCFs than the
previously reported results in [17] and [26]. In addition, we
extract the useful correlation information about TCFs so that
SAT solvers or ATPG engines can easily find solutions. Our
experimental results show that, among a set of selected circuits
using the TSMC 0.13-μm cell library, on average, the combined
technique is 13.25 times faster than that of [17] for the run time
of the TCF construction and 8.98 times faster than that of [17]
for the run time of the SAT solver. Moreover, to demonstrate
the effectiveness of our TCFs, we have successfully applied
our method to an important application, the circuit-delay
computation.
The remainder of this paper is organized as follows.
Section II introduces the TCF, and Section III provides the efficient implementation of the TCF. Then, Section IV shows the
overall algorithm. Section V shows the experimental results.
Section VI concludes this paper, summarizing our contributions.
stability later than or equal to time t = 5, can be expressed as
the on-set of the Boolean function TCF(r = 0, 5+).
Most previous papers related to timing analysis discuss
path-sensitization criteria to determine whether a path is true
or false in the floating-mode model. For example, the static
sensitization describes a path sensitized by a vector if all the
side inputs along the path stabilize noncontrolling values. Also,
the viability sensitization [13] describes the criterion that a
path is sensitized by a vector if side inputs are required to be
noncontrolling values or to stabilize later than the node on the
path. Chen and Du [3] proposed a general framework to present
different path-sensitization criteria for comparison.
Unlike those proposing path sensitization, several papers do
not trace the path. They model the path-sensitization criteria
using a Boolean function and then test the SAT of the function.
Basically, this paper belongs in this category. McGeer et al. [12]
proposed an efficient method for generating the functional
forms of timing analysis and robust path delay-fault test generation. Silva et al. [17] conducted a comprehensive study of
modeling circuit-delay computation, accounting for false paths
as a sequence of instances of Boolean SAT. The research in [17]
provides three sensitization criteria to obtain the TCF. In the following, we consider only the exact floating-mode sensitization
criterion. If node y is an OR gate, I(y) denotes all inputs of node
y, and d denotes the delay of node y. If node y is an OR gate
TCF(y = 1, t+)
=
[z = 1] ·
TCF (z = 1, (t − d)+)
z∈I(y)
·
z∈I(y)
{TCF (w = 1, (t − d)+) + [w = 0]}
(1)
TCF(y = 0, t+)
=
[z = 0] ·
TCF (w = 0, (t − d)+)
(2)
w∈I(y)
II. TCF
In this section, we review the definitions of the TCF and a
way to compute the Boolean function. As with most previous
papers, we use the floating mode of operation and apply all
input vectors at time t = 0. In the floating mode of operation
[3], a transition is defined as a value change from an unknown
state to a known state of a node in the circuit.
In addition, for simplicity of discussion, each node has a
constant delay of 1 in all examples. The general delay model
can be easily extended to cope with the industrial cell library
with variable rise and fall delays, different pin-to-pin delays,
and the interconnect delay.
Let y be a circuit node, val be a functional requirement, and
t be a temporal requirement. The Boolean function TCF(y =
val, t+) characterizes the set of input vectors that, when evaluated, can cause node y = val to stabilize later than or equal to
time t but not earlier than time t. In other words, given an input
vector x, the Boolean function TCF(y = val, t+) is equal to 1
if and only if node y = val is stable later than or equal to time
t when input vector x is applied. The functional requirement
val can be 0 or 1. The symbol “+” is used to emphasize the
concept of “later than” or equal to the temporal requirement
t. For example, in Fig. 1, suppose that we are interested in
finding input vectors that cause node r = 0 to be stable later
than or equal to time t = 5. All input vectors satisfying the
functional requirement, r = 0, and the temporal requirement,
z∈I(y)
w∈I(y)
where we use [z = 1] to denote the functional requirement of
node z to stabilize at 1, use the summation symbol Σ to denote
the OR operation, and use the multiplication symbol Π to denote
the AND operation. TCF(y = 1, t+) describes the sensitization
condition when node y stabilizes at 1 later than time t. The
requirements of the condition are as follows: 1) at least an
input must stabilize at 1 later than time t − d and 2) each input
must stabilize at 1 later than time t − d or stabilize at 0 without
the timing constraint. Similarly, TCF(y = 0, t+) describes the
sensitization condition when node y stabilizes at 0 later than
time t. The requirements of the condition are as follows: 1) all
inputs must stabilize at 0 and 2) one of all inputs must stabilize
at 0 later than time t − d. Similarly, if node y is an AND gate
TCF(y = 1, t+)
[z = 1] ·
TCF (w = 1, (t − d)+)
=
z∈I(y)
(3)
w∈I(y)
TCF(y = 0, t+)
=
[z = 0] ·
TCF (z = 0, (t − d)+)
z∈I(y)
·
w∈I(y)
z∈I(y)
{TCF (w = 0, (t − d)+) + [w = 1]} .
(4)
KUO et al.: EFFICIENT BOOLEAN CHARACTERISTIC FUNCTION FOR TIMED ATPG
Let us consider the example in Fig. 1. Using the aforementioned equations, TCF(r = 0, 5+) can be derived from its
inputs’ TCFs, which again are derived from their inputs’ TCFs.
Finally, with logic minimization, we obtain TCF(r = 0, 5+) =
(eg + eo + j ) · (a b eg + a b ej + a b eo + mo) .
During the recursive construction process, intermediate
TCFs with different temporal requirements are constructed.
When certain boundary conditions are met, an intermediate
TCF can be determined without further recursive construction.
Let us consider node f in Fig. 1 and try to find TCF(f = 0, 1+).
First, there are three paths from the primary inputs to node f :
paths {a, c, d, f } and {b, c, d, f } with a path delay of 3 and
path {e, f } with a path delay of 1. Since all paths from the
primary inputs to node f have a path delay greater than 1, the
temporal requirement, stability later than or equal to time t = 1,
is met for all input vectors. Since the temporal requirement of
TCF(f = 0, 1+) is met, we need only to consider the functional
requirement f = 0. Therefore, we have TCF(f = 0, 1+) = f .
Recently, Roy et al. [26] proposed the use of the event
propagation conditions to obtain an accurate circuit-delay computation. The key difference between [26] and this paper is the
assumption of the mode of operation. Whereas [26] assumes
the transition mode, we adopt the floating mode. Because the
transition mode may violate the monotonic speedup property
[25], Roy et al. [26] performs an optimistic estimation of the
circuit delay, whereas ours performs a pessimistic estimation.
419
of all four Boolean functions are mutually exclusive. For
example, an input vector satisfying TCF(y = 1, t−) = 1
must cause TCF(y = 0, t−) = 0, TCF(y = 1, t+) = 0,
and TCF(y = 0, t+) = 0 by the definition of TCF. As a
result, we have the following: TCF(y = 1, t−) = TCF(y =
0, t−) + TCF(y = 1, t+) + TCF(y = 0, t+). Thus, we obtain
TCF(y = 1, t−) · y
= TCF(y = 0, t−) + TCF(y = 1, t+)
+ TCF(y = 0, t+) · y
= TCF(y = 0, t−) · y + TCF(y = 1, t+) · y
+ TCF(y = 0, t+) · y.
(7)
Let us consider the term TCF(y = 0, t−) · y in (7). It can be
easily shown that TCF(y = 0, t−) · y = 0 because it is impossible to have an input vector that causes y = 0 and y = 1
simultaneously. Similarly, we have TCF(y = 0, t+) · y = 0.
Moreover, TCF(y = 1, t+) · y = TCF(y = 1, t+) because an
input vector that causes node y = 1 to be stable earlier than
time t must also cause node y = 1 to be stable. Therefore, we
can obtain
TCF(y = 1, t−) · y = TCF(y = 1, t+).
Similarly, we can also obtain
TCF(y = 0, t−) · y = TCF(y = 0, t+).
III. E FFICIENT TCF I MPLEMENTATION
Using the procedure in the previous section, we can derive
a TCF. However, the size of the TCF can be much larger than
the original circuit. In Section III-A, we show novel compact
recursive formulations and then propose reduction techniques
in Sections III-B and C.
Theorem 2: Given a circuit node y whose inputs are denoted
by I(y) and delay is denoted by d, we have the following.
If node y is an OR gate
TCF (z = 1, (t − d)−)
(8)
TCF(y = 1, t−) =
z∈I(y)
A. Recursive TCF Formulations
First, we discuss some properties of a TCF. Note that
TCF(y = val, t+) defined previously uses the + symbol to
express the concept of later than or equal to the temporal
requirement t. We can also use the “−” symbol to express
the concept of “earlier than” the temporal requirement t. The
Boolean function TCF(y = val, t−) characterizes the set of
input vectors that, when evaluated, can cause node y = val to
stabilize earlier than time t and to stay stable later than time t.
A TCF with the − symbol is called an earlier timed TCF, and a
TCF with the + symbol is called a later timed TCF.
We now discuss the reasons why the recursive formulations
of earlier timed TCFs can lead to a compact representation for
TCFs. The two theorems are shown as follows.
Theorem 1: Given a circuit node y and a temporal requirement t, we have the following:
TCF(y = 1, t+) = TCF(y = 1, t−) · y
(5)
TCF(y = 0, t+) = TCF(y = 0, t−) · y .
(6)
Proof: First,
TCF(y = 1, t−) + TCF(y = 0, t−) +
TCF(y = 1, t+) + TCF(y = 0, t+) = 1. Also, the on-sets
TCF(y = 0, t−) =
TCF (z = 0, (t − d)−) .
(9)
TCF (z = 1, (t − d)−)
(10)
z∈I(y)
If node y is an AND gate
TCF(y = 1, t−) =
z∈I(y)
TCF(y = 0, t−) =
TCF (z = 0, (t − d)−) . (11)
z∈I(y)
Proof: First, let us consider the case when node y is an
gate. Because the controlling value of OR gate y is 1, y is
stable at 1 earlier than the time t if one of the inputs of node y
is stable at the controlling value 1 earlier than the time t − d.
The corresponding TCF formulation is summarized in (8). On
the other hand, because the noncontrolling value of OR gate
y is 0, y is stable at 0 earlier than the time t if all inputs of
node y are stable at the noncontrolling value 0 earlier than the
time t − d. The corresponding TCF formulation is summarized
in (9). Similarly, one can prove the cases when node y is
an AND gate.
OR
420
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
Fig. 4. Recursive derivation process TCF(r = 0, 5+) using the gate
representation.
TABLE I
VARIABLE AND CLAUSE COMPARISONS FOR A K-INPUT OR GATE
BETWEEN THAT OF [17] AND OUR EQUATIONS
B. Sharing Mechanism for TCFs
Fig. 3. Recursive derivation process TCF(r = 0, 5+) using the equation
representation.
Theorem 1 shows that a later timed TCF can always be
translated to an earlier timed TCF, and Theorem 2 shows that an
earlier timed TCF of a node can be expressed by earlier timed
TCFs of the node’s inputs. In our algorithm, if a TCF is later
timed, it is translated into an earlier timed TCF by (5) or (6) in
Theorem 1. Then, we recursively derive the earlier timed TCF
by (8)–(11) in Theorem 2. In this way, all TCFs are of the same
type, which is important for the sharing mechanism discussed
in the next section.
Let us consider the problem of finding TCF(r = 0, 5+)
in Fig. 1. First, we translate TCF(r = 0, 5+) to TCF(r =
0, 5+) = TCF(r = 0, 5−) · r by (6). Then, we recursively
derive TCF(r = 0, 5−). Since node r in Fig. 1 is an OR
gate, we need to use the formula from (9), and then, we
have TCF(r = 0, 5−) = TCF(h = 0, 4−) · TCF(q = 0, 4−) ·
TCF(p = 0, 4−). After that, we will need to derive the equations for TCF(h = 0, 4−), TCF(q = 0, 4−), and TCF(p =
0, 4−). The construction process continues toward the primary
inputs. The entire derivation of TCF(r = 0, 5+) is shown in
Fig. 3, and its gate representation is shown in Fig. 4.
Generally speaking, we provide equations to derive earlier
timed TCFs, which are simpler than the later timed TCFs of
[17]. For example, in Table I, we show the comparisons of the
SAT variables and clauses for a K-input OR gate between that
of [17] and our equations by using the method in [27]. The
later timed TCFs of a K-input OR gate of [17] are (1) and (2)
while the earlier timed TCFs of a K-input OR gate of ours are
(8) and (9). We can observe that our variables and clauses are
fewer than that of [17]. In addition, we also provide equations
to transform later timed TCFs to earlier timed TCFs.
A TCF derived directly by the recursive formulation may be
much larger than the original circuit, mainly because all fanout branches of a node may require different TCFs. Let us
consider node f in Fig. 1, which has three fan-out branches.
During the recursive construction process of TCF(r = 0, 5+),
three intermediate TCFs, TCF(f = 0, 1−), TCF(f = 0, 2−),
and TCF(f = 0, 3−), are needed for node f .
In general, each fan-out branch of a node may have its
own functional and temporal requirements. Without careful
planning, we may need to build TCFs for all fan-out branches of
a node. However, some TCFs are functionally equivalent, even
with different temporal requirements. Before a TCF is finally
constructed, the equivalence of two different intermediate TCFs
can be difficult to recognize. For example, TCF(f = 0, 2−) and
TCF(f = 0, 3−) have different temporal requirements but have
equal functionality after construction.
We propose the collection of useful arrival-time information,
which allows equivalent TCFs to be recognized during the recursive construction process. First, there can be many different
paths from the primary inputs to a node n. Each path delay
from a primary input to node n represents a possible delay or a
possible arrival time when an input vector is applied. For the
same example, in Fig. 1, there are three paths—{a, c, d, f },
{b, c, d, f }, and {e, f }—from the primary inputs to node f ,
where {a, c, d, f } and {b, c, d, f } have a path delay of 3 and
{e, f } has a path delay of 1. Therefore, there are two possible
arrival times for node f after applying an input vector: 1 and 3.
Let {Aj } be a sorted set of possible arrival times for node y,
i.e., Ak < Ak+1 . In addition, let {Ti } be a set of the temporal
requirements for which we must construct the earlier timed
TCFs on node y. We say that the arrival time Ak is the nextlarger arrival time of Ti if Ak−1 < Ti ≤ Ak . Let us consider
the example in Fig. 1. Node f has two possible arrival times:
1 and 3. In addition, node f has three temporal requirements:
1, 2, and 3. The next-larger arrival time of temporal requirement
2 is 3, and the next-larger arrival time of temporal requirement
3 is 3. Then, we have the following lemma.
KUO et al.: EFFICIENT BOOLEAN CHARACTERISTIC FUNCTION FOR TIMED ATPG
Fig. 5.
421
TCF(r = 0, 5+) after applying sharing mechanism.
Lemma 3: For the two TCFs TCF(y = val, t1−) and
TCF(y = val, t2−), if these two temporal requirements t1 and
t2 have the same next-larger arrival time
TCF(y = val, t1−) = TCF(y = val, t2−).
Proof: Let the next-larger arrival time for t1 and t2 be Ak .
The on-set of TCF(y = val, t1−) must contain all the vectors
that belong to the on-set of TCF(y = val, Ak −) because the
on-set of TCF(y = val, Ak −) contains all input vectors whose
path delays to node y are less than Ak , and each path delay to
node y must be exactly equal to a possible arrival time of node
y. Therefore, we can obtain
TCF(y = val, t1−) = TCF(y = val, Ak −).
(12)
Similarly, we can also obtain
TCF(y = val, t2−) = TCF(y = val, Ak −).
(13)
By (12) and (13), we can obtain TCF(y = val, t1−) =
TCF(y = val, t2−).
In Fig. 3 or Fig. 4, TCF(f = 0, 2−) and TCF(f = 0, 3−) are
equivalent according to Lemma 3, since temporal requirements
2 and 3 have the same next-larger arrival time. Therefore, we
need to build only one of these two TCFs. The result is shown
in Fig. 5.
In our algorithm, the arrival-time information can be derived
by the same algorithm in [7]. After that, during the recursive
construction process of a TCF, we use Lemma 3 to merge
intermediate TCFs whose temporal requirements have the same
next-larger arrival time, without constructing several equivalent TCFs.
C. Correlation Information Extraction
In this section, we illustrate how to extract the correlation
information about TCFs to SAT solvers or ATPG engines.
The correlation information, which can be easily recognized
during the recursive construction process of a TCF, describes
the relationship between two intermediate TCFs of a node. We
have the following two lemmas.
Lemma 4: For a circuit node y and two temporal requirements t1 and t2 where t1 < t2
TCF(y = val, t1−) ⊆ TCF(y = val, t2−)
or
TCF(y = val, t1−) + TCF(y = val, t2−) = 1.
Fig. 6. Flow diagram of the TCF construction algorithm.
Proof: If TCF(y = val, t1−) is 1, TCF(y = val, t2−)
must be 1 because any input vector that causes node y = val
to be stable earlier than t1 must also cause node y = val to be
stable earlier than t2.
Lemma 5: For a circuit node y and two temporal requirements t1 and t2
TCF(y = val, t1−) ∩ TCF(y = val , t2−) = ∅
or
TCF(y = val, t1−) + TCF(y = val , t2−) = 1.
Proof: If TCF(y = val, t1−) is 1, TCF(y = val , t2−)
must be 0 because any input vector that causes y = val to be
stable must not cause y = val to be stable.
When the condition in Lemma 4 is satisfied, we add
an extra Boolean function TCF(y = val, t1−) + TCF(y =
val, t2−) = 1 to the overall TCF. When the condition in
Lemma 5 is satisfied, we add an extra Boolean function
TCF(y = val, t1−) + TCF(y = val , t2−) = 1 to the overall
TCF. These extra Boolean functions do not change the on-set of
the overall TCF but provide the correlation information when
we solve the overall TCF.
IV. O VERALL A LGORITHM F LOW
Now, we describe our overall algorithm for constructing a
TCF in Fig. 6. Given the functional and temporal requirements
of a node, we model these two requirements as a TCF.
1) If the TCF is later timed, it is translated to an earlier timed
TCF by (5) or (6) in Theorem 1.
2) Then, the arrival-time information of each node is
computed.
3) After that, we construct the TCF recursively from the
node toward the primary inputs by (8)–(11) in Theorem 2.
422
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
TABLE II
RESULTS UNDER THE UNIT DELAY MODEL
During the recursive construction process, we use
Lemma 3 to merge all equivalent intermediate TCFs.
4) After constructing the overall TCF, we apply the correlation information from Lemmas 4 and 5.
V. E XPERIMENTAL R ESULTS
In this section, we demonstrate and evaluate our TCF construction algorithm. We perform two experiments including
the TCF construction in Section V-A and the circuit-delay
computation in Section V-B. Experiments are conducted on the
Sun Microsystems sun4u Sun Blade 2500 whose CPU clock
frequency is 1600 MHz, system clock frequency is 160 MHz,
and memory size is 4 GB.
A. Results of the Efficient TCF Construction
We reimplement the algorithm shown in [17] and conduct
experiments on a set of MCNC benchmark circuits. Since the
main purpose in [17] is to find a circuit’s delay, in order to
compare fairly with their results, we generate ten temporal requirements, from the largest to the smallest possible arrival time
with an equal interval. Then, for each temporal requirement
t, we attempt to find an input vector that causes at least one
primary output to be stable later than or equal to time t. This
requirement is modeled as (14). Then, we solve the TCF using
the SAT solver MiniSat [5]
[TCF(y = 0, t+)+TCF(y = 1, t+)]. (14)
TCFC+ (t)=
y∈P O(C)
We perform experiments under different delay models such
as the unit delay model where each node has a constant delay
of 1, the unit fan-out delay model where each node has a delay
of 1 plus the value 0.2 multiplied by the fan-out number of
the node, and the TSMC 0.13-μm cell library. Let us take
C1908 using the TSMC 0.13-μm cell library as an example.
The latest and the earliest arrival times among all primary
outputs are 2.74 and 0.15 ns. First, we determine the interval
by (2.74 − 0.15)/(10 − 1) = 0.28. Therefore, the ten temporal
requirements for C1908 are 2.74, 2.46, 2.18, 1.90, 1.62, 1.34,
1.06, 0.78, 0.50, and 0.22. Then, we can apply our approach to
the circuit for these ten temporal requirements. The largest and
smallest possible arrival times are also known as the delay of
the longest topological path (LTP) and the delay of the shortest
topological path, respectively.
Note that, in the floating mode of operation, the first vector is
pessimistically assumed to be unknown. Thus, TCF(y = 1, t−)
describes the condition that a rising transition of node y is stable
earlier than time t. Moreover, the delay d in (8) and (10) should
be obtained from the rise delay of node y. Similarly, TCF(y =
0, t−) describes the condition that a falling transition of node
y is stable earlier than time t. Moreover, the delay d in (9) and
(11) should be obtained from the fall delay of node y.
Table II shows the results under the unit delay model.
Table III shows the results under the unit fan-out delay model.
Table IV shows the results using the TSMC 0.13-μm cell
library. Column 1 shows the name of the circuit. Column 2
shows the gate count of a circuit. Columns 3, 4, and 5 show the
average number of variables of the TCF (titled as Vars), the
average run time of the TCF construction (titled as TCF),
and the average run time of the SAT solver (titled as SAT),
respectively, for the ten temporal requirements by [17] while
columns 6, 7, and 8 show the results of our approach with the
correlation information, and columns 9, 10, and 11 show the
results of our approach without the correlation information. To
avoid too many Boolean functions obtained from Lemmas 4
and 5 for the correlation information, we limit the number of
these Boolean functions within the 5% of the TCF’s variables
by using some engineering rules in the following: 1) The node
in the tested network is a multiple fan-out node; 2) the node
is close to primary inputs; and 3) the node has many temporal
requirements.
We have made several observations from the experiment
results among a set of selected circuits. First, both the run
time of the TCF construction and the run time of the SAT
solver are reduced significantly. For the run time of the TCF
construction, our approach is 4.68 times faster than that of
[17] under the unit delay model, 14.59 times faster than that
of [17] under the unit fan-out delay model, and 13.25 times
faster than that of [17] using the TSMC 0.13-μm cell library.
For the run time of the SAT solver, our approach is 8.05 times
faster than that of [17] under the unit delay model, 8.09 times
KUO et al.: EFFICIENT BOOLEAN CHARACTERISTIC FUNCTION FOR TIMED ATPG
423
TABLE III
RESULTS UNDER THE UNIT FAN-OUT DELAY MODEL
TABLE IV
RESULTS USING THE TSMC 0.13-μm CELL LIBRARY
faster than that of [17] under the unit fan-out delay model, and
8.98 times faster than that of [17] using the TSMC 0.13-μm
cell library. Finally, we would like to mention that, with the
correlation information, the run time of the SAT solver is
reduced by about 27% compared with the run time without the
correlation information. However, when including the run time
of the TCF construction, the total run time is only improved
marginally. We would like to mention that the improvement
from the correlation information extraction is not always very
effective since the SAT solver may spend time for the additional
clauses of the correlation information from Lemmas 4 and 5.
B. Results of the Circuit-Delay Computation
A key application of the TCF is the circuit-delay computation. The TCF can solve the false-path problem to avoid
overconservative circuit-delay values [4], [6], [17]. For the
circuit-delay computation, we use a stepping method similar
to that in [17] to approach the true delay of a circuit using
a dynamically adjustable step size. Then, we integrate the
stepping method and our proposed TCF construction algorithm
to compute the delay of a circuit. The TCF is constructed as (14)
with and without the correlation information to model at least
one primary output to be stable later than or equal to time t.
Then, we reimplement the algorithms of the circuit-delay
computation in [17] and [26] and then apply these to several
MCNC/ITC 99 benchmark circuits and several practical
circuits including a Triple Data Encryption Standard design,
an Advanced Encryption Standard design, an MD5 hash core,
an Audio Codec ’97, and a 32-b multiplier using the TSMC
0.13-μm cell library. Table V shows the results of the benchmark circuits, and Table VI shows the results of the large practical circuits. Column 1 shows the name of the circuit. Column 2
shows the number of the gates. Columns 3 and 4 show the
delay of the LTP (titled as LTP) and the delay calculated by our
method (titled as Delay). Columns 5, 6, and 7 show the largest
number of variables of the TCF among TCFs with different
temporal requirements (titled as Vars), the total run time of the
TCF construction (titled as TCF), and the total run time of the
SAT solver (titled as SAT) of the method in [17]. Columns 8, 9,
and 10 show the results of the method in [26]. Columns 11, 12,
and 13 show the results of our approach with the correlation
information. In the table, the entries labeled ∗ indicate that the
results cannot be obtained due to the memory shortage.
For the run time of the TCF construction, on average, our
approach is about 5.18 times faster than that of [17]. For
the run time of the SAT solver, on average, our approach is
about 1.67 times faster than that of [17]. The run time of the
424
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
TABLE V
RESULTS OF THE CIRCUIT-DELAY COMPUTATION FOR BENCHMARK CIRCUITS
TABLE VI
RESULTS OF THE CIRCUIT-DELAY COMPUTATION FOR PRACTICAL CIRCUITS
SAT solver is improved slightly, but the run time of the TCF
construction is improved greatly even for large circuits. In
addition, for the run time of the TCF construction, on average,
our approach is about 191.58 times faster than that of [26].
For the run time of the SAT solver, on average, our approach
is about 178.62 times faster than that of [26]. Note that [26]
adopts the transition mode of operation while Silva et al. [17]
and we adopt the floating mode of operation. It may not be fair
to directly compare results with different modes of operation.
The maximum memory usage is 2310 MB when our approach
is applied to ITC benchmark circuit b19.
VI. C ONCLUSION
In this paper, we present very effective ways for the TCF
modeling. Our contributions include the compact formulations,
the sharing mechanism, and correlation information extraction
techniques for TCFs. On average, our algorithm is 13.25 times
faster than that of [17] for the run time of the TCF construction,
and our algorithm is 8.98 times faster than that of [17] for
the run time of the SAT solver. Moreover, we demonstrate the
effectiveness of our TCF formulas by means of finding the
delay of a circuit. On average, our algorithm is 5.18 times faster
than that of [17] for the run time of the TCF construction,
and our algorithm is 1.67 times faster than that of [17] for
the run time of the SAT solver. On average, our algorithm is
191.58 times faster than that of [26] for the run time of the TCF
construction, and our algorithm is 178.62 times faster than that
of [26] for the run time of the SAT solver.
R EFERENCES
[1] P. Ashar and S. Malik, “Functional timing analysis using ATPG,” IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 8,
pp. 1025–1030, Aug. 1995.
[2] R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi, “Timing
analysis of combinational circuits using ADDs,” in Proc. IEEE Eur. Des.
Test Conf., 1994, pp. 625–629.
[3] H. C. Chen and D. Du, “Path sensitization in critical path problem,”
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 2,
pp. 196–207, Feb. 1993.
[4] S. Devadas, K. Keutzer, and S. Malik, “Computation of floating mode
delay in combinational circuits: Theory and algorithms,” IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 12, pp. 1913–
1923, Dec. 1993.
[5] N. Een and N. Sörensson, “A SAT solver with conflict-clause
minimization,” in Proc. SAT, 2005. [Online]. Available: http://minisat.se/
MiniSat.html
[6] J. L. Güntzel, A. C. M. Pinto, and R. Reis, “A timed calculus for ATGbased timing analysis of circuits with complex gates,” in Proc. IEEE Latin
Amer. Test Workshop, 2001, pp. 234–239.
[7] H. Kriplani, F. Najm, and I. N. Hajj, “Pattern independent maximum
current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution,” IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 8, pp. 998–1012,
Aug. 1995.
[8] Y. M. Jiang, A. Krstic, and K. T. Cheng, “Estimation for maximum
instantaneous current through supply lines for CMOS circuits,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 1, pp. 61–73,
Feb. 2000.
[9] Y. M. Jiang, K. T. Cheng, and A. Krstic, “Estimation of maximum power
and instantaneous current using a genetic algorithm,” in Proc. IEEE Custom Integr. Circuits Conf., 1997, pp. 135–138.
[10] R. Kundu and R. D. Blanton, “Timed test generation for crosstalk switch
failure in domino CMOS circuits,” in Proc. IEEE VLSI Test Symp., 2002,
pp. 379–385.
[11] R. Kundu and R. D. Blanton, “ATPG for noise-induced switch
failures in domino logic,” in Proc. Int. Conf. Comput.-Aided Des., 2003,
pp. 765–768.
KUO et al.: EFFICIENT BOOLEAN CHARACTERISTIC FUNCTION FOR TIMED ATPG
[12] P. C. McGeer, A. Saldanha, P. R. Stephan, R. K. Brayton, and
A. L. Sangiovanni-Vicentelli, “Timing analysis and delay-fault test
generation using path-recursive functions,” in Proc. Int. Conf. Comput.Aided Des., 1991, pp. 180–183.
[13] P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal
Domains in Logic Design. Norwell, MA: Kluwer, 1991.
[14] M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik,
“Chaff: Engineering an efficient SAT solver,” in Proc. Des. Autom. Conf.,
2001, pp. 530–535.
[15] J. P. M. Silva and K. A. Sakallah, “Efficient and robust test
generation-based timing analysis,” in Proc. Int. Symp. Circuits Syst., 1994,
pp. 303–306.
[16] J. P. M. Silva and K. A. Sakallah, “GRASP: A search algorithm for
propositional satisfiability,” IEEE Trans. Comput., vol. 48, no. 5, pp. 506–
521, May 1999.
[17] L. G. Silva, J. P. M. Silva, L. M. Silveira, and K. A. Sakallah, “Satisfiability models and algorithms for circuit delay computation,” ACM Trans.
Design Autom. Electron. Syst., vol. 7, no. 1, pp. 137–158, Jan. 2002.
[18] H. Yalcin and J. P. Hayes, “Hierarchical timing analysis using conditional
delays,” in Proc. Int. Conf. Comput.-Aided Des., 1995, pp. 371–377.
[19] H. Zhang, “SATO: An efficient propositional prover,” in Proc. Int. Conf.
Autom. Deduction, 1997, pp. 272–275.
[20] M. K. Michael, T. Haniotakis, and S. Tragoudas, “A unified framework
for generating all propagation functions for logic errors and events,”
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 6,
pp. 980–987, Jun. 2004.
[21] S. Padmanaban and S. Tragoudas, “Efficient identification of (critical)
testable path delay faults using decision diagrams,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 24, no. 1, pp. 77–87, Jan. 2005.
[22] K. Yang, K. T. Cheng, and L. C. Wang, “TranGen: A SAT-based ATPG for
path-oriented transition faults,” in Proc. Asian South Pacific Des. Autom.
Conf., 2004, pp. 92–97.
[23] Y. M. Kuo, Y. L. Chang, and S. C. Chang, “Efficient Boolean characteristic function for fast timed ATPG,” in Proc. Int. Conf. Comput.-Aided Des.,
2006, pp. 96–99.
[24] W. K. C. Lam and R. K. Brayton, Timed Boolean Functions: A Unified
Formalism for Exact Timing Analysis. Norwell, MA: Kluwer, 1994.
[25] S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis. New York:
McGraw-Hill, 1994.
[26] S. Roy, P. P. Chakrabarti, and P. Dasgupta, “Event propagation for accurate circuit delay calculation using SAT,” ACM Trans. Design Autom.
Electron. Syst., vol. 12, no. 3, p. 36, Aug. 2007.
[27] T. Larrabee, “Test pattern generation using Boolean satisfiability,” IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 11, no. 1, pp. 4–
15, Jan. 1992.
425
Yu-Min Kuo (S’08) received the B.S. and M.S.
degrees in computer science from National Tsing
Hua University, Hsinchu, Taiwan, in 2002 and 2004,
respectively, where he is currently working toward
the Ph.D. degree in computer science.
His current research interests include the noiseaware timing analysis, logic optimization, and related computer-aided design techniques.
Yue-Lung Chang received the B.S. and M.S. degrees in computer science from National Tsing Hua
University, Hsinchu, Taiwan, in 2004 and 2006,
respectively.
Since 2007, he has been with Globalunichip, Inc.,
where he is currently an Engineer in the Design Flow
and Development Group 2. His current research
interests include design for testability and related
computer-aided-design techniques.
Shih-Chieh Chang (S’92–M’95) received the B.S.
degree from National Taiwan University, Taipei,
Taiwan, in 1987 and the Ph.D. degree from the University of California, Santa Barbara, in 1994, both in
electrical engineering.
He was with Synopsys, Inc., Mountain View, CA,
from 1995 to 1996. Then, he was with the faculty of
the Department of Computer Science and Information Engineering, National Chung Cheng University,
Minsyong, Taiwan, from 1996 to 2001. He is currently a Professor with the Department of Computer
Science, National Tsing Hua University, Hsinchu, Taiwan. His current research
interests include logic synthesis, functional verification for systems-on-a-chip,
and noise analysis.
Dr. Chang is the recipient of the Best Paper Award at the 1994 Design
Automation Conference.