« Floating Point » Charge Sensitive Amplifier
for the focal plane of S3
Ph.Vallerand – GANIL [email protected]
E.Delagnes – IRFU [email protected]
T.Chaminade – IRFU [email protected]
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Implantation Silicon Detector

Technical Specifications for DSSSD



Number of channels : 256
Counting rate / channel : 10 kHz
10 µs
Energy range :
 100 keV to 15 MeV with a resolution ~ 15keV FWHM
 15 MeV to 500 MeV with a resolution ~ 1% FWHM
1) Accurate measurement of an  decay particle of 10 MeV
few 10 µs
after the huge energy deposition related to the heavy ion implantation
challenge
2) Dynamic range ~ 80,000 = 16-17 bits rms
to provide with only one channel digitizer (14 bits)
CSA based on a dynamic configuration of the gain :
« Floating Point » CSA
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
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Principle of the Floating Point CSA

Adapt the CSA gain to the energy
to be measured in real time :
2 gains
 a high gain for low energy ~ 44.4 mV/MeV
 a low gain for high energy ~ 2.1 mV/MeV
(Cf = 1pF)
(Cf = 21pF)
detector
ADC
only one output to digitalize
switching a feedback
capacitor for changing the
gain as a function of output
signal level
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Principle of the Floating Point CSA

Block diagram of the Floating Point CSA
1pF
60pF
700kΩ
Allowing a return of the CSA output
signal to the baseline in less than the
specified 10µs, with a drawback of
parallel noise. Time constant is
supposed to be cancelled after
digitization
CSA_output(t)
threshold
21pF
detector + cable
capacitor
35kΩ
Set-up for simulations :
Low Gain : Rf=35KΩ ; Cf=21pF
High Gain : Rf=700KΩ ; Cf=1pF
t
Discri output
time
constant
Cmd_LG
of 700ns
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
2.4ms
t
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Simulation results

Transcient simulations
in V

Operation : single pulse energy scan from 1MeV to 33MeV
FPCSA output
30 MeV HG
25 MeV HG
20 MeV HG
typical shape of the
output signal
15 MeV HG
10 MeV HG
5 MeV HG
1 MeV HG
time (s)
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
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Simulation results

Transcient simulations
in V

Operation : single pulse energy scan from 35MeV to 500MeV
FPCSA output
atypical shape of the
output signal
500 MeV LG
400 MeV LG
300 MeV LG
200 MeV LG
100 MeV LG
50 MeV LG
35 MeV LG
digital
treatment
required
time (s)
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
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Simulation results

Noise simulations : CR-RC2 filtering

Equivalent Noise Charge vs peaking time
ENC eV
Low Gain
ENC eV
ENC eV
High Gain
ENC ~ 13.3 keV rms
ENC ~ 6.5 keV rms
ENC ~ 3.2 keV rms
Rf=700KΩ
Cf=1pF
ENC ~ 9.6 keV rms
peaking time in s
ENC ~ 3.2 keV rms
 7.2keV FWHM
Rf=35KΩ
Cf=21pF
peaking time in s
ENC ~ 9.6 keV rms
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 23keV FWHM
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Simulation results

Integrated Non-Linearity simulations
Low Gain
in V
in V
High Gain
energy (MeV)
INL (Measure - Fit)  24.10-3 %
 8.6keV
energy (MeV)
INL (Measure - Fit)  33.10-2 %
 1.6MeV
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Prototype chip

2 channel prototype ASIC in AMS CMOS 0.35µm



packaging : 44-pin ceramic CQFP
area = 1800 µm x 1900 µm ~ 3.3 mm2
2 channel test board :
Voltage supply
one channel :
500 µm x 1100 µm
LG digital output
Test set-up :
digitizer CAEN 100MHz – 14 bits
Inputs :
HT,
Current,
Test
Differential
Analog
Outputs
Size : 100 x 72 mm
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
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Test results

High gain - Low energy
Charge Injection
on Ctest :
220mV*2pF = 440pC
 9.77MeVSi
1/5
FPCSA
differential
signal output
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

High gain - Low energy

2/5
Risetime
Risetime = 12ns (without capa det)
Risetime = 23ns (with capa det)
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

High gain - Low energy
Charge Injection on Ctest :
83mV*4.7pF =  390.1 fC
 8.66MeV Si
3/5
FPCSA
differential
signal output
Vout diff  385mV
(213mV & 186mV)
=>
High Gain  44mV/MeV
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

High gain - Low energy
Charge Injection
on Ctest :
-83mV*4.7pF = -390.1 fC
 -8.66MeV Si
4/5
FPCSA
differential
signal output
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

High gain - Low energy
Charge Injection
on Ctest :
226mV*4.7pF = 1.06pC
 23.9MeVSi
5/5
FPCSA
differential
signal output
the FPCSA stay
in high gain: 1.02 V
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

Low gain - High energy
Charge Injection
High
on Ctest :
Gain
227mV *4.7pF = 1.07pC
 24MeVSi
1/4
Low
Gain
Internal
charge
injection
High
Gain
Vpeak  50mV
Low gain back
to high gain after 2.4µs
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

Low gain - High energy
Charge Injection
High
on Ctest :
Gain
450mV *4.7pF = 2.12pC
 47.6MeVSi
2/4
Low
Gain
High
Gain
Vpeak  90mV
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

Low gain - High energy
Charge Injection
on Ctest :
de 1.93V *4.7pF =
9.07pC
 204MeVSi
3/4
Vpeak  400mV
High
Gain
Low
Gain
High
Gain
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

Low gain - High energy
4/4
Vpeak  1.05V
Charge Injection
on Ctest :
4.9V *4.7pF = 23pC
 518 MeVSi
High
Gain
Low
Gain
High
Gain
Vout diff  1.05V
=>
Low Gain  2mV/MeV
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results
Double pulse mode
Pulse 60 MeV followed by 2 MeV with 6µs delay

Low
Gain
High
Gain
1/3
High
Gain
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

Double pulse mode
2/3
Pulse 20 MeV followed by 2MeV : Only High gain
High
Gain
High
Gain
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Test results

Double pulse mode
3/3
Pulse de 260 MeV followed by 38 MeV : Only Low Gain.
Low
Gain
High
Gain
Low
Gain
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Analysis

Pulse 9.4MeV followed by 1.4Mev : Only High gain

200 superimposed events
Digital filtering output
digital filtering : PZ cancellation + 1µs triangular shaper
FPCSA output
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Analysis

Pulse 9.4MeV followed by 1.4Mev : Only High gain

Resolution after digital filtering PZ cancellation
+ 1µs triangular shaper
Histogram
zoom
E  12.3keV FWHM
@ 1.4 MeV
E  14.7keV FWHM
@ 9.4 MeV
E = 1300e-rms  11keV FWHM on the baseline
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
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Analysis


Pulse 75MeV and 150MeV : Only Low gain
Histogram
zoom
Resolution after customized digital filtering (Multiple Correlated Sampling)
due to test pulser ??
E  370 keV FWHM  0.5% @ 75 MeV
to be verified…
E  450 keV FWHM  0.3% @ 150 MeV
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
CONCLUSION
« Floating Point » Charge Sensitive Amplifier
 Tests
are not finished but results are already satisfied
 resolution seems to be in agreement with specifications
 non linearity characterization expected in June 2012
 specific digital filtering MRC mainly for the low gain need
to be ended
 Floating Point CSA architecture : a good compromise in
terms of performances, complexity, cost and integration
design a multi-channel chip : 8 or 16 … to be defined with
the collaboration S3
 To
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Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Thanks for your attention !
Ph.Vallerand – GANIL [email protected]
E.Delagnes – IRFU [email protected]
T.Chaminade – IRFU [email protected]
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
Focal plane detector setup

To study the stopped recoil
Tunnel of Silicon Detectors
for backward emitted alpha,
electrons and X-rays
Germanium detector
Array
Time of flight
Tracking detector
Secondary Electron
Devices for position
& time measurements
Implantation detector :
Double Sided Silicon Strip Detector
for energy and time measurements of heavy ions,
 and e- decay particles
Journées VLSI Lyon 2012 – Floating Point Charge Sensitive Amplifier – 7th june 2012 –Ph.Vallerand
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