GISMO Kickoff Meeting
Digital Receiver & Processing System
RSS iRAP System Overview
– 2/4 Channel FPGA-based Digital Receiver (DARM)
– FPGA-based Algorithm Processor (DARM)
– FPGA-based Disk Striping CARD (DARM)
– 3rd Party Cards
• Ultra High Speed Communication Backplane (BRD)
• Redundant Supplies
GISMO Kickoff Meeting – 14 January 2009
Digital Receiver Module (DARM)
Digital Receiver Module (DARM)
Digital Receiver Module (DARM)
Digital Receiver Module (DARM)
Algorithm Processor (DARM)
Algorithm Processor (DARM)
Algorithm Processor (DARM)
• Network Processor (NPM)
• Switch Fabricate (SFM)
• 8 FPGA Processor Slots
Algorithm Processor (DARM)
– 8 / 12 Slot Configurations
– Conduction Cooled
Switch Fabricate Module (SFM)
• 3U Form Factor
Power Supply(s)
System Components
Network Processor (NPM)
Power, Communication and Processing Bus (BRD)
DARM: Digital Receiver Module
Digital Receiver Configuration
System Block Diagram
DARM Module
• Virtex 5 SX95T FPGA processor.
JTAG
ADC Mezzanine
(1, 2, 4 channels)
SMBUS
XJ4
EPROM
– Supports up to 4 IF signals.
– Supports up to 18 bit ADCs.
EXP Bus
Digital
IF
C-SIO
SFM Communications
P-SIO
PSIO x2 Local Bus
P-SIO
PSIO x2 Processor 1 Bus
V5 SX95T
XJ3
High Speed
Digital Data
P-SIO
PSIO x2 Processor 2 Bus
P-SIO
PSIO x2 Processor 3 Bus
P-SIO
PSIO x2 Processor 4 Bus
APM
Cfg.
DRM
Cfg.
• ADC Mezzanine Card.
• Multi-Channel Digital Receiver
– Provides support for 2 or 4 IF channels.
– Up to 8 / 4 sub channels per IF.
– Independent NCO, bandwidth and match filter
per sub channel.
– Up to 200 MHz bandwidth per IF.
– Pre-summing capability (18 bit resolution).
– Sub channels reconfigurable on the fly.
GISMO Kickoff Meeting – 14 January 2009
DARM: Digital Receiver (cont.)
Digital Receiver Data Bus
System Block Diagram
DARM Module
JTAG
ADC Mezzanine
(1, 2, 4 channels)
SMBUS
XJ4
EPROM
EXP Bus
Digital
IF
C-SIO
SFM Communications
P-SIO
PSIO x2 Local Bus
P-SIO
PSIO x2 Processor 1 Bus
P-SIO
PSIO x2 Processor 2 Bus
P-SIO
PSIO x2 Processor 3 Bus
P-SIO
PSIO x2 Processor 4 Bus
V5 SX95T
XJ3
High Speed
Digital Data
APM
Cfg.
DRM
Cfg.
• 10 Gb/s communications to NPM.
• 6.4 Gb/s communications to each DARM
algorithm processor slot (up to four).
• 6.4 Gb/s between adjacent receivers.
• Supports PCIe communications.
• Same card used as algorithm processor.
• High Speed Digital Input Interface.
• Conduction Cooled / High Altitude Operation
GISMO Kickoff Meeting – 14 January 2009
Switch Fabric Module
SFM Features:
Power
Conditioning
/
Distribution
• Implements PCI Express switch.
•
•
•
•
•
SWITCH BOARD
XJ1
VddCore
= 1.0
VddPE= 1.0
VddAPE
= 1.0
VttPE=1.5
SMBUS
XJ4
EPROM
Clock
Circuitry
REFCLK
[1:0]
[3:2]
3
[1:0]
[3:2]
4
[1:0]
[3:2]
NC
5
[1:0]
[3:2]
NC
6
[1:0]
[3:2]
NC
7
[1:0]
[3:2]
NC
8
[1:0]
[3:2]
NC
9
[1:0]
[3:2]
NC
-
PCIe Switch
Clock Reference pair
associated with each
PCIe Interface
GISMO Kickoff Meeting – 14 January 2009
2
NC
UpStream11[1:0]
NC
01
PCIe2
x2
NC
10[1:0]
[3:2]
[3:2]
PCIe1
x2
NC
PCIe3
x2
PCIe4
x2
PCIe5
x2
PCIe6
x2
PCIe7
x2
PCIe8
x2
PCIe9
x2
PCIe10
x2
L
Clock Refernce pair
associated with each
PCIe Interface
CLK0-4
Ie
- 12 ports, 48 lanes
- x8 Root Complex
Provides communication to / from
processor slots:
- 5 Gb/s data rate both ways.
- Expandable to 10 Gb/s. .
Provides bus clocks.
Standard bus to support 3rd party cards.
Conduction cooled design.
Supports high altitude operations.
JTAG
CLK1/2
CLK2/2
CLK3/2
CLK4/2
CLK5/2
CLK6/2
CLK7/2
CLK8/2
CLK9/2
CLK10/2
XJ4
XJ4
EP0
XJ4
XJ4
XJ2
XJ2
XJ2
XJ2
XJ5
EP N-1
XJ5
[3:0] [3:0]
PCIe0
x8
CLK
uPC
CLK0/2
XJ3
NPM
XJ3
Network Processor Module
System Block Diagram
XLA[6:31]
LLA[0:31]
XLA[27:31] XLA[6:30]
CPLD
BCSR
CS1/3
Flash
32MB
CS0
XLD[7:0]
XLD[15:0]
SDRAM3
Parity
32MBx16
LDP[0:3]
I2C1
Address
Latch
SDRAM2
32MBx16
SDRAM1
32MBx16
LAD[15:00]
LAD[31:16]
LAD[0:31]
I2C2
Boot
EEprom
DDR
SPD
EEprom
Core
PWR
POT
RTC
ADDR 50h
ADDR 51h
ADDR 54h
ADDR 68h
Brd
EEprom
ADDR 50h
XLD[0:15]
PHY
PHY
5.0V
12 > 5.0V
MUX
5.0V>CoreV
Pwr Conn
5.0V>
DDR_VDD
5.0V>3.3V
3.3V
MUX
Debug
Power
Backplane connector
12V
TSec2
TSec3
PCIe RC
PCIe
Osc
PCIe
Osc
PCIe x8
BSCR
TSec4
MDQ[0:63]
MECC[0:7]
MDQS[0:8]
MDM[0:8]
MA[0:15]
MBA[0:2]
MODT0
MODT1
MCAS
MRAS
MWE
MCS0
MCS1
MCK0
MCK0MCKE0
MCKE1
72Bit
200Pin
SODIMM
DDR Sel
(1=II,0=I)
2.5/1.8V
DDR
P/S
3.3V
Prototype / Development Board
JTAG
PHY
TSec1
MPC8548E
Ext. Comms
Backplane connector
PCIe x8
Backplane connector
XCTRL
PHY
NPM Features:
• Freescale MPC8548E Processor.
• Supports:
- 4 Gigabit Ethernet Engines.
- x8 CompactPCIe Root Complex.
- 4 SerDes (RocketIO).
- I2C bus.
- RS-232/RS-422.
• Linux 2.6 Kernel.
• Implements software layer
-RSS System Object Language.
• Conduction Cooled Design.
• High Altitude Operations (70 Kft).
GISMO Kickoff Meeting – 14 January 2009
GISMO Nominal Configuration
• Four Digital Receiver Cards (DARM)
– Three cards dedicated to interferometric radar.
• Four IF channels per digital receiver.
• 40-60 MHz bandwidth per IF channel.
• Four channel 12-bit ADC mezzanine card.
– One card dedicated to WISE.
• DARM or 3rd Party Card
– SATA striping solution.
• Network Processor / SFM
– Communication to other subsystems, communication systems and users.
• Future Expansion / Trade Space
– Support up to 20 interferometer channels plus WISE.
– Single cage or dual cage solution.
– Real-time sequential and/or parallel processing and storage.
GISMO Kickoff Meeting – 14 January 2009