MIGRATING FROM
SDRAM TO DDR
Bill Gervasi
Vice Chairman, JEDEC Memory Timing
Technology Analyst
[email protected]
Topics to Cover
 About
JEDEC & DDR
 Market Segments & Fragments
 Design Architectures
 DDR Solutions
 Changes from SDR to DDR
 Timing Diagrams
 Impact to board design
 Why Not Rambus?
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About JEDEC & DDR
 Setting
open standards for >25 years
 Consortium of 350 companies
Memory suppliers
 Users from all market segments

 Double
Data Rate (DDR) SDRAM
Latest approved JEDEC standard
 Results of collaborative market analysis

3
Segments & Fragments
Servers
PC100
PC133
DDR
Workstations
PC100
PC133
DDR
PC Segment 2
PC Segment 1
PC Segment 0
Mobile
Graphics
Rambus
DDR
PC100
PC100
PC100
PC66
SS167
Rambus
DDR
PC133
DDR
PC133
PC100
PC133
DDR SDRAM (x16)
DDR
DDR SDRAM(x32)
2H99 1H00 2H00 1H01 2H01
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Market Factors
 Server
per-system memory capacity
increasing faster than PC
 Segments 1, 2 split Intel & non-Intel
 UMA graphics takes over Segs 0 & 1

“Sealed Box” PC for home market
 Mobile

market mostly skips PC-133
DDR power lower than SDR
 Graphics
early: short design cycles
5
RAM Evolution
3200MB/s
Mainstream
Memories
2100MB/s
1000MB/s
400MB/s
320MB/s
Simple,
incremental
steps
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Continued Tradition
DDR is the logical incremental step
 Performance enhancements
 Detailed documentation
 Full support from vendors & users
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System Designs
PC/Server
Small
Memory
Systems
Controller*
Controller
* Single chip or separate
clock, data & address chips
 Point
to point
 200MHz clock
 3.2GB/s transfer
 Sockets
& Stubs
 133MHz clock
 2.1GB/s transfer
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DDR Solutions
PC/Server Applications
Small Systems
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How Different is DDR?
 Simple
upgrade to SDR designs
Similar PCB characteristics
 Same fast RAS/CAS command set

A
few evolutionary improvements
Bidirectional data strobe
 Low voltage swing I/O

 JEDEC
Standards
Data sheet including IBIS curves
 Module gerbers, application notes

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From SDR to DDR
Signaling
Clocks
Pin Count
Data Strobe
Packages
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From SDR to DDR
Signaling
Clocks
Pin Count
Data Strobe
Packages
12
DDR Signaling
 SSTL_2
low voltage swing inputs
2.5V I/O with 1.25V reference voltage
 Low voltage swing with termination
 Rail to rail if unterminated

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From SDR to DDR
Clocks
Signaling
Pin Count
Data Strobe
Packages
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DDR Clocks
 Differential
clocks on adjacent traces
 Timing is relative to crosspoint
 Helps insure 50% duty cycle
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“Slow” Signal Timing
on CK 
 Loading mismatch,  single data rate
 Addresses & Control signals
 Based
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From SDR to DDR
Signaling
Clocks
Pin Count
Data Strobe
Packages
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“Fast” DDR Read Timing
 Data
valid on rising & falling edges
 Source Synchronous:

Data Strobe “DQS” travels with data
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Read Timing 200MHz CK
tDV insures worst case shift on DQS can’t happen
(sufficient timing margin for system design!)
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A Totally Sync Design
 Operate
solely in memory clock
timing domain
 Fast

design for small systems
Tight layout required
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“Fast” DDR Write Timing
 DQS
centered in data valid eye
 DM timing & loading identical to DQ
 Flexible
to support large systems
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DDR Write Design Hint
 Early
DQS stresses back to back ops
 Late stresses the array update

1.0 * tCK is best
“Perfect” alignment
at 1.0 * tCK
Good solution for
single chip
controllers
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Emphasis on “Matched”
 DM/DQS
loading identical to DQ
 Route as independent 8bit buses
CONTROLLER
DDR SDRAM
DQ/DQS
VREF
VREF
DM
VREF
VREF
Disable
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64 = 8 x 8
 64bit
bus is 8 sync’ed 8bit buses
 Allows external “copper” flexibility
 8 buses resync upon entry to FIFO
x16 DDR
SDRAM
Copper
from
controller
to SDRAMs
Inside
Controller
Sync to
Controller
clock
8 DQ
1 DM
1 DQS
x16 DDR
SDRAM
x16 DDR
SDRAM
8 DQ
1 DM
1 DQS
x16 DDR
SDRAM
8 DQ
1 DM
1 DQS
8bit Buffer
8bit Buffer
64bit Memory Controller Internal FIFO
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From SDR to DDR
Signaling
Clocks
Pin Count
Data Strobe
Packages
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Packages
 Device
66pin TSOP same size as 54pin TSOP
 Same 400x875mil, .65mm vs .80mm

 DIMM
184pin same size as 168pin
 Same 5.25”, same pin pitch (key filled)

 SO-DIMM
200pin slightly longer than 144pin
 73mm vs. 68mm, .65mm vs. .80mm

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From SDR to DDR
Signaling
Clocks
Pin Count
Data Strobe
Packages
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Pin Count Versus SDR
 One
DQS for 8 DQ (x8, x16 SD)
--- or -- One DQS for every 32 DQ (x32 SG)
 One /CK adjacent to every CK
 One VREF
 Additional VDDQ, VSS?

DQ/DM/DQS:VDDQ:VSS ratio of 4:1:1
 Total:
5-12 more pins
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Combined SDR/DDR
SDR








DDR
3.3V I/O supply
Single ended CLK
Echo CLK for reads
No write latency
CAS latency 2, 3
Series termination
Burst length 1, 2, 4, 8
No reference voltage








 Combined
2.5V I/O supply
Differential CK and CK
DQS for reads
Write latency one clock
CAS latency 2, 2.5, (3)
Series & parallel term’n
Burst length 2, 4, 8
Reference voltage VREF
SDR & DDR controller is a
reasonable way to minimize risks
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Hints for the Future
You’ll get the fastest designs if you:
 Don’t use command interrupts
 Don’t use autoprecharge
 Fixed burst length 4
 Programmable drive impedance

Weak and strong drivers are standard
 Unbroken
ground planes & islands
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Why Not Rambus?
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Compare DDR & Rambus
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DDR Versus Rambus
DIMM cost:
PCB cost:
Latency:
Peak BW:
Power:
DDR
Advantage Reason
 $10
 Die, Heat sinks,
+ royalties
dummy modules
 15%
 28 ±10% vs.
55 ±15%
 27%
 Packet protocol
 33%
 Frequency * width
 40%
 Frequency
Email me to get the white paper detailing this analysis
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Rambus Market Issues
 High

Poor fit for UMA graphics
 High

latency
power
Poor fit for mobile
 Costly

materials
Poor fit for cost sensitive systems
 Leaves
the $2500+ PC market as a fit
Insufficient volumes to create a market
 Other solutions needed anyway

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Summary
 DDR
is here today
Double the bandwidth
 Evolutionary design change over SDR
 Cheaper, faster, & cooler than Rambus
 Applies to all market segments

 Industry
Standards
Detailed complete data sheet & models
 Module designs on the web
 Visit http://www.jedec.org

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Call to Action
 Watch
all the market trends
 Let your memory vendor know about
your commitment to DDR
 Let the trade press know your choice
 Use smart engineering to push limits
 Join JEDEC and influence the future
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Thank You
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