Outline
High Level Design
1
Introduction
School of Computer Science and Electronic Engineering
University of Essex
UK
2
SystemC
Spring 2013
3
Handel C
Dongbing Gu
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
1 / 20
Introduction
High Level Design
Spring 2013
2 / 20
Introduction
Systems-on-chip (SoC) and large scale, distributed embedded systems
(DES) are designed at the system level in order to:
reduce design complexity by means of abstraction.
optimize the complete system before individual modules are designed or
assembled.
reduce the simulation turnaround time.
The trend in large scale systems is towards more software modules so
as to increase flexibility.
Software modules are also a feature of some smaller scale systems,
including those based on software acceleration, and/or
reconfigurability.
Therefore, high level design avoids committing the design (to
hardware or software) at too early a stage.
D. Gu (Univ. of Essex)
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
3 / 20
There are four main high level design trends:
Modeling language approach the modeling and design of larger
systems has, from the 80s, been dominated by HDLs
which can operate at various design levels including the
behavioral level, but the trend is towards C-like system
level design languages chiefly because of software
compatibility.
Toolkit approach The success of HDLs was due to a proliferation of
auxiliary tools, but co-design has used alternative
modeling tools, again because of the need to
incorporate software modules. Co-design supports
partitioning whereas partitioning is implicit in the
language approach.
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
4 / 20
Introduction
High level Design Language Issues
Data modeling approach can be used in conjunction with the other two
approaches or independently, e.g. dataflow diagrams, SDL.
This type of modeling is appropriate to data dominated
systems, e.g. in multimedia and telecommunications.
Reactive systems respond to asynchronous events, as in control dominated
systems, e.g. in robotics and avionics. There are reactive
languages such as Esterel, and graphical modeling methods
stemming from Finite State Machines.
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
5 / 20
SystemC - language model example
SystemC is an open source set of class libraries for modeling intended
as a standard language onto which synthesis tools can be grafted,
without manual translation to HDL.
High Level Design
Existing software languages will lack support for lower level design.
New languages may not have support for the integration of software
modules, simply because relevant legacy software is mostly written in
C.
A new language may lack a pool of programmers who are familiar
with it, thus pushing up training costs or wage bills.
VHDL features entity hierarchies. It is also supports replication.
Object-oriented languages also lend themselves to organization of
component hierarchies through inheritance.
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
6 / 20
SystemC
The design of Neon Graphics Accelerator (1999) is a good example of
the popularity of C/C++ with hardware designers: C++ templates
for bit-width specification, C mathematical libraries, a clock-cycle
simulator written in C and a C-to-Verilog translator, were used.
D. Gu (Univ. of Essex)
Existing languages may have features such as pointers that do not
exist in hardware and/or are difficult to synthesize.
Spring 2013
7 / 20
A library, rather than language extensions, avoids the need for
compilers. SystemC hides some C++ detail as many hardware
engineers are more familiar with C.
SystemC is strong on modeling and simulation but has limited
support for partitioning and test-benching.
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
8 / 20
SystemC Features
SystemC Concept
SystemC is based on the same reactive model as in HDL.
A reactive system consists of a set of non-terminating processes that
respond to external events.
SystemC uses multithreading to model hardware time-parallelism.
The SystemC class libraries are intended to:
Time parallelism is modeled either by co-routines (self-scheduling
threads) or schedueable threads.
allow the design to be simulated at two basic levels of refinement:
Asynchronous event-based and Clock synchronous.
support microprocessor core within SoC design in clock synchronous
mode.
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
In SystemC, a thread is declared with a list of signals to which it is
sensitive. A thread can “wait” on an event, or “watch” for an event.
All threads communicate through “port” interfaces. There are no
global or shared variables in SystemC hardware modeling because
data race conditions are avoided in hardware (i.e. no semaphores or
monitors).
9 / 20
SystemC Architecture
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
10 / 20
Handel C
C-like code compilation to hardware.
Modules group or contain the features of a hardware/software module.
Processes actually threads.
Based on ANSI-C with addition of inherent parallelism.
The hardware design is generalised directly from Handel-C program.
Ports interfaces by which modules are interconnected.
Outputs to Xilinx or Altera netlist.
Signals occur as the result of events, e.g. change of a variables value.
It is not HDL, but programming language.
Clocks synchronous signals.
Suitable for software engineers.
Software reuse
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
11 / 20
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
12 / 20
Handel-C and ANSI-C
Handel-C Implementation of Hardware
Expression evaluation = combinational logic operation
Requires zero clock cycles, but results in propagation delay through
corresponding combinational logic.
Example: a + b c
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
13 / 20
Handel-C Implementation of Hardware
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
14 / 20
Handel-C Parallel Construct - PAR
Handel-C blocks are by default sequential.
Assignment statement = register storage operation
par executes statements in parallel.
Requires 1 clock cycle.
par block completes when all statements complete.
Example: r = a + b c
Time for block is time for longest statement.
Can nest sequential blocks in par blocks.
x = 1; y = 2; z = 3; - 3 clock
cycles,
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
15 / 20
D. Gu (Univ. of Essex)
High Level Design
par x = 1; y = 2; z = 3; - 1
clock cycle
Spring 2013
16 / 20
Basic Data Type: Integer
Handel-C new types: Channel
The only fundamental type of variable in Handel-C.
Channels are used to communicate between, and synchronize, parallel
branches of code.
Variables are mapped to hardware registers.
one branch writes to the channel, the other reads from it.
communication can only occur when both branches are ready.
one item of data is then transferred.
Smaller integers = smaller hardware
Can be signed or unsigned: user determines integer bit-width.
Channels are declared using the keyword chan.
Type mismatches include integer size and sign: no automatic type
conversion.
Cannot declare and define a variable in one step: unsigned 6 a; a=45;
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
17 / 20
Inter-process Communication
channels have defined widths (in bits).
associated operators are used to read ( ?) and write ( !) channels.
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
18 / 20
Software Language Based Approach
chan int 4 link ; // define a 4−bit channel
int 4 r , w ; // variables are i n different code blocks
w = 3;
link ! w ; // v a r i a b l e w writes 3 t o link and w a i t s
link ? r ;
Some problems are better expressed as a software algorithm.
Software reference designs can be utilized.
Designs are often specified by a C/C++ executable specification.
Simplifies and delays hardware-software partitioning.
Software development techniques can be used.
Brings hardware and software teams closer together.
{
{
link ! w ; // write w t o ←link
link ? r ; // read link ←to r
}
}
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
19 / 20
D. Gu (Univ. of Essex)
High Level Design
Spring 2013
20 / 20