Address Decoding
Memory/IO
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = FFFFF
1
1
1
1
FFFFF
A0 – A19
1 Mbyte
memory
8088
D0 – D7
CS
CS= Chip Select.
If CS = 0 then the memory will be ON
If CS = 1 then the memory will be sleeping and all its pins will be Z
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = FFFFF
0
1
1
1
A19
FFFFF
A0 – A19
A0 – A18
8088
CS
7FFFF
512 KB
memory
D0 – D7
7FFFF
D0 – D7
00000
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
1
0
0
0
End Address = FFFFF
1
1
1
1
A19
FFFFF
A0 – A19
A0 – A18
8088
CS
7FFFF
512 KB
memory
D0 – D7
80000
D0 – D7
00000
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = 0FFFF
0
0
0
0
FFFFF
A16 – A19
8088
A0 – A19
Address
Decoding
CS
FFFF
A0 – A15
64 KB
memory
D0 – D7
D0 – D7
0000
0FFFF
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = 0FFFF
0
0
0
0
FFFFF
This memory should be
selected only when
A16 – A19
A16 = 0
A17 = 0
A18 = 0
A19 = 0
CS FFFF
A0 – A15
64 KB
memory
D0 – D7
0000
0FFFF
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = 0FFFF
0
0
0
1
FFFFF
This memory should be
selected only when
A16 – A19
A16 = 1
A17 = 0
A18 = 0
A19 = 0
CS FFFF
A0 – A15
1FFFF
64 KB
memory
D0 – D7
0000
10000
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = 0FFFF
0
0
1
0
FFFFF
This memory should be
selected only when
A16 – A19
A16 = 1
A17 = 0
A18 = 0
A19 = 0
CS FFFF
A0 – A15
2FFFF
20000
64 KB
memory
D0 – D7
0000
00000
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
11M locations
1
1
1
1
Starting Address = 00000
0
0
0
0
End Address = 0FFFF
0
0
1
1
FFFFF
This memory should be
selected only when
A16 – A19
A16 = 1
A17 = 0
A18 = 0
A19 = 0
3FFFF
CS FFFF
30000
A0 – A15
64 KB
memory
D0 – D7
0000
00000
Connections Between CPU and Memory
Control signals
8088
Memory
Data Bus
Address bus
 What are the control signals from the microprocessor to memory?
What are the control signal from memory to the microprocessor?
 Address and data signals should be buffered
— The use of buffers on address bus increases driving capability
— Bi-directional buffers are used to control the data transferring directions
on data bus
— D latches are used to de-multiplex signals on AD[7:0] (and A[19:16])
5-10
Timing Diagram of A Memory Operation
 Example: 8088 sends address 70C12 to memory in a memory read operation
assume that data 30H is read
T2
T1
T4
CLK
Addr[15:0]
D latch
8088
T3
ALE
A[15:8]
A[19:16]
Buffer
7H
A[15:8]
AD[7:0]
Memory
D latch
AD[7:0]
S3-S6
0CH
12H
30H
D[7:0]
DT/R
DEN
IO/M
WR
RD
Trans
-ceiver
Addr[19:16]
7H
Addr[15:8]
0CH
Addr[7:0]
12H
D[7:0]
30H
5-11
Memory Chips
• The number of address pins is related to the number of memory
locations .
– Common sizes today are 1K to 256M locations. (10 and 28 address pins
are present.)
• The data pins are typically bi-directional in read-write memories.
– The number of data pins is related to the size of the memory location .
– For example, an 8-bit wide (byte-wide) memory device has 8 data pins.
– Catalog listing of 1K X 8 indicate a byte addressable 8K memory.
• Each memory device has at least one chip select ( CS ) or chip enable (
CE ) or select ( S ) pin that enables the memory device.
• Each memory device has at least one control pin.
– For ROMs, an output enable ( OE ) or gate ( G ) is present.
• The OE pin enables and disables a set of tristate buffers.
– For RAMs, a read-write ( R/W ) or write enable ( WE ) and read enable
(OE ) are present.
• For dual control pin devices, it must be hold true that both are not 0 at the
same time.
5-12
Memory Address Decoding
• The processor can usually address a memory space that is
much larger than the memory space covered by an individual
memory chip.
• In order to splice a memory device into the address space of
the processor, decoding is necessary.
• For example, the 8088 issues 20-bit addresses for a total of
1MB of memory address space.
• However, the BIOS on a 2716 EPROM has only 2KB of memory
and 11 address pins.
• A decoder can be used to decode the additional 9 address pins
and allow the EPROM to be placed in any 2KB section of the
1MB address space.
5-13
Memory Address Decoding
5-14
Decoding Circuits
• NAND gate decoders are not often used.
• 3-to-8 Line Decoder (74LS138) is more common.
5-15
Memory Address Decoding
 Using Full memory addressing space
Addr[19:0]
FFFFF
Highest address
0011 0 111 1111 1111 1111
Lowest address
0011 0 000 0000 0000 0000
37FFF
32KB
30000
These 5 address lines
are not changed. They
set the base address
00000
Addr[14:0]
Addr[19]
Addr[18]
Addr[17]
Addr[16]
Addr[15]
IO/M
These 15 address lines select
one of the 215 (32768) locations
inside the RAMs
32KB
CS
Can we design a decoder such that the first address
of the 32KB memory is 37124H?
5-16
Memory Map Full address
decoding
A19=A18=...=A14=1
select the EPROM
A16, A15, A14 select
one EPROM chip
A19 = 1, A18 = 0, A17 = 0
activate the decoder
A0
... 256KB
A17 RAM
CS1’ chip
All the address lines used by the decoder or memory chip =>
each byte is uniquely addressed = full address decoding
A14
CS2
16KB
A15
EPROM
A16
FFFFF
A0-A13
A0-A13
A17
chip
FC000
A18
OE
A19
A14
A15
A16
A17
A18
A19
A
B
C
7
6
5
74LS138 4
3
E1
2
E2
1
E
0
CS10
CS9
CS8
CS7
CS6
CS5
CS4
CS3
16KB
16KB
16KB
16KB
EPROM
16KB
EPROM
16KB
16KB
EPROM
16KB
EPROM
chip
EPROM
chip
EPROM
EPROM
chip
EPROM
chip
chip
chip
chip
chip
OE
9FFFF
9C000
83FFF
80000
220 =
1,048,576
different
byte
addresses
= 1Mbyte
3FFFF
MRDC
The same Memory-map
A18
assignment
A0
A19
18
MWTC
A 256Kbyte = 2 RAM chip has
... 256KB
18 address lines, A0 - A17
MRDC
A17 RAM
chip
A18
A19, A18 assigned to 00 =>
CS1 WR RD
00000
A19
A18
=
0
CS active for every address
WR
A19 = 0 IO/M
8088 Memory Map
from 00000 to 3FFFF
RD
IO/M = 0
IO/M = 0 => Memory map
CS1  A19  A18  IO / M  A19  A18  IO / M
Memory Address Decoding
 Design a 1MB memory system consisting of multiple memory chips
— Solution 1:
256KB
CS
256KB
CS
256KB
CS
256KB
CS
Addr[17:0]
Addr[18]
2-to-4
decoder
Addr[19]
CS
IO/M
5-18
Memory Address Decoding
 Design a 1MB memory system consisting of multiple memory chips
— Solution 2:
256KB
CS
256KB
CS
256KB
CS
256KB
CS
Addr[19:2]
Addr[1]
2-to-4
decoder
Addr[0]
CS
IO/M
5-19
Memory Address Decoding
 Design a 1MB memory system consisting of multiple memory chips
— Solution 3:
256KB
CS
Addr[19:18]
Addr[16:7]
Addr[5:0]
Addr[17]
256KB
256KB
CS
CS
256KB
CS
2-to-4
decoder
Addr[6]
CS
IO/M
It is a bad design, but still works!
5-20
Memory Address Decoding
 Design a 1MB memory system consisting of multiple memory chips
— Solution 4:
256KB
CS
256KB
512KB
CS
CS
Addr[17:0]
Addr[18]
Addr[18]
Addr[19]
IO/M
Addr[18]
Addr[19]
IO/M
Addr[19]
IO/M
5-21
Memory Address Decoding
 Exercise Problem:
— A 64KB memory chip is used to build a memory system with the starting address of
7000H. A block of memory locations in the memory chip are damaged.
FFFFH
7FFFFH
733FFH
3317H
73317H
3210H
73210H
0000H
70000H
Replace this block
73200H
64KB
Damaged block
1M addressing space
1M addressing space
5-22
Memory Address Decoding
A[19]
A[18]
A[17]
A[16]
IO/M
A[15]
A[14]
A[13]
A[12]
A[11]
64KB
A[15:0]
CS
A[8:0]
512B
CS
A[10]
A[9]
5-23
Memory Address Decoding
 Exercise Problem:
— A 2MB memory chip with a damaged block (from 0DCF12H to 103745H) is used to
build a 1MB memory system for an 8088-based computer
1FFFFFH
1FFFFFH
512K
103745H
Use these
two
blocks
0FFFFFH
0DCF12H
07FFFFH
512K
000000H
180000H
000000H
Damaged block
A[19]
A[19:0]
A[20]
A[19:0]
CS
5-24
Memory Address Decoding
 Partial decoding
— Example:
 build a 32KB memory system by using four 8KB memory chips
 The starting address of the 32KB memory system is 30000H
Chip #4
Chip #3
Chip #2
Chip #1
36000H
34000H
32000H
30000H
0011 0 11 1 1111 1111 1111
0011 0 11 0 0000 0000 0000
high addr. of chip #4
0011 0 10 1 1111 1111 1111
0011 0 10 0 0000 0000 0000
high addr. of chip #3
0011 0 01 1 1111 1111 1111
0011 0 01 0 0000 0000 0000
high addr. of chip #2
0011 0 00 1 1111 1111 1111
0011 0 00 0 0000 0000 0000
high addr. of chip #1
Low addr. of chip #4
Low addr. of chip #3
Low addr. of chip #2
Low addr. of chip #1
5-25
Memory Address Decoding
— Implementation of partial decoding
8KB
CS
8KB
CS
8KB
CS
8KB
CS
Addr[12:0]
Addr[13]
2-to-4
decoder
Addr[14]
IO/M
 With the above decoding scheme, what happens if the processor accesses location
02117H, 32117H, and 9A117H?
 If two 16KB memory chips are used to implement the 32KB memory system, what
is the partial decoding circuit?
 What are the advantage and disadvantage of partial decoding circuits?
5-26
Some address lines not used by the decoder or memory
chip => mirror images = partial address decoding
Memory Map Partial address
decoding
A18=...=A14=1
select the EPROM
A16, A15, A14 select
one EPROM chip
A19 = 1, A17 = 0
activate the decoder
A0
...
A15
64KB
RAM
CS1’ chip
A14
A15
A16
A17
A18
A14
A15
A16
A17
A19
CS2
A0-A13
A0-A13
A
B
C
7
6
5
74LS138 4
3
E1
2
E2
1
E
0
CS10
CS9
CS8
CS7
CS6
CS5
CS4
CS3
16KB
EPROM
chip
OE
16KB
16KB
16KB
16KB
EPROM
16KB
EPROM
16KB
16KB
EPROM
16KB
EPROM
chip
EPROM
chip
EPROM
EPROM
chip
EPROM
chip
chip
chip
chip
chip
OE
FFFFF mirror
FC000 image
DFFFF
DC000
mirror
CF000 image
CC000
9FFFF
9C000 base
83FFF image
80000
7FFFF base
7C000 image
MRDC
The same Memory-map
A18
assignment
3FFFF
A0
A19
30000
64KB
MWTC
A 64Kbyte = 216 RAM chip has
2FFFF mirror
...
images
20000
16 address lines, A0 - A15
MRDC
A15 RAM
1FFFF
chip
10000
A18
0FFFF base
A19, A18 assigned to 00 =>
CS1
WR
RD
image
A19
00000
A18 = 0
CS active for every address
WR
A19 = 0 IO/M
8088 Memory Map
from 00000 to 3FFFF
RD
IO/M = 0
A16, A17 not used => four images for the same chip
IO/M = 0 => Memory map
Generating Wait States
 Wait states are inserted into memory read or write cycles if slow memories
are used in computer systems
Ready signal is used to indicate if wait states are needed
data
Address
memory
8088
Delay
circuit
decoder
Ready
clr
clr
D
Q
D
Ready
Q
clk
5-28
Generating Wait States (Timing)
CLK
Q1
Q2
Ready
One Wait State
Sel
clr
clr
D
Q
D
Ready
Q
clk
5-29