ppt

CALICE
-
ECAL silicon-tungsten
 Introduction with pictures
 Prototype design and construction
 R&D on the design of the full scale calorimeter
1
J-C. BRIENT (LLR)
Just to recall the reason of the choice
e+e–  W+W– at s = 800 GeV
After reconstruction
e+e–  W+W– at s = 800 GeV
Classified as charged pads
Simulation,visualisation
MOKKA, FANAL
Classified as photon’s pads
2
J-C. BRIENT (LLR)
Electron ID in jets
ALL VALUES in %
Photon ID in jets
ZH at 500 GeV
Z in  , H in jets
Jets at 91 GeV
Hadron MISID
Electron ID
Particle momentum
Photon energy
GeV
250 GeV
GeV
±
 →

→
and
ID
→
3
J-C. BRIENT (LLR)
Jet mass
Tau decays ID is essential for
 ID and polarisation measurement
 (250 GeV) →
Jet mass
< 0.2

→

→
Jet mass in
0.2-2
82%
17%
2%
90%
Looking along
the charged track
in the first 4 X0
charged pion
Photons from o
Looking along
the ch. track
in 5-12 X0
4
J-C. BRIENT (LLR)
CALICE
-
ECAL silicon-tungsten
 Introduction with pictures
 Prototype design and construction
 R&D on the design of the full scale calorimeter
5
J-C. BRIENT (LLR)
Prototypes overview
Global view
of the test beam setup
VME/PCI/…
ECAL general view
HCAL
2nd structure
3rd structure
(3×1.4mm of W plates) (2×1.4mm of W plates)
ECAL
Beam
monitoring
Movable table
VFE
1st structure
(1.4mm of W plates)
Detector slab
Silicon wafer
6
J-C. BRIENT (LLR)
Alveolus structures
Design and construction of a mould with all metallic pieces for the 3 different structures
Mould for alveolus structure 1.4
Structure 5 alveolus :(10 layers)
Detector slab
(here it is just a type H structure)
7
J-C. BRIENT (LLR)
Detector slab
Transverse view
Front End electronics
Shielding
PCB
Silicon wafer
(0.525 mm)
7.3 mm
PCB (8-10 layers)
Al. Shielding
( 2 - 2.5 mm)
Silicon wafer
(Cfi / W) structure type H
Composite structure
(0.15 mm / layer)
Tungsten
(1.4 mm, 2×1.4 or 3×1.4 mm)
8
J-C. BRIENT (LLR)
Detector schematic description
Amorphous silicon deposition
 Protection
 Capacitance (AC coupling)
2 2 2 2 2
62mm
10mm
6
2
10mm
62mm
Diode footprint
1 wafer
Diode bias
Sig. readout
Diode pinout
Aluminium sheet
PCB
Wafers
The aluminium sheet is the ground
9
J-C. BRIENT (LLR)
4” high resistivity wafers
-525 microns thick – 5Kcm
- tile side: 62.0 + 0.0
- 0.1 mm
ECAL prototype
silicon wafer description
- scribe line: 100 m
- scribe safety zone: 200 m
- guard ring width: cca 750 m
(cca 1.5 * wafer thickness)
First test production
with 25 wafers
24 good
Wafer book keeping
information
(<10nA leakage)
10
J-C. BRIENT (LLR)
Front End electronics
Electronic readout
CHIP FLC-PH1 developed at LAL
•18 charge inputs
•18 voltage outputs
•1 MUX voltage output
low noise
good linearity
large dynamic
1.6 nv/Hz
non-linearity ≲ 1%
650 mip
Custom-built
VME readout board (UK)
First prototype April 2003
Board based on PCI or even USB2.0
is also under study
11
J-C. BRIENT (LLR)
Responsibilities
ITEMS
LABORATORIES
- Tungsten production and test
- Mechanics assembly (Cfi,…)
ITEP, IHEP, LAL
LLR, LPC
- Silicon wafers production
- Amorphous silicon deposition,…
MSU (Moscow), IPASCR (Prague)
PICM, LLR
- VFE design and production
- ADC’s and DAQ
LAL, (LPC for large scale R&D)
IC, UCL, Manchester,
Cambridge , Birmingham
- Detector slab assembly
- Cosmics test on assembled device
LLR
LLR
12
J-C. BRIENT (LLR)
Meetings and Agenda
21th January 2003 , ORSAY (LAL)
meeting on ECAL prototype
- Technical meeting on
construction , test, beam def., …
End February 2003 , PALAISEAU (LLR)
meeting on Digital HCAL prototype
- responsibilities
- funding
- repartition of works
The goal is :
ECAL ready for a first debugging test beam
at the Summer-Fall 2004
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J-C. BRIENT (LLR)
CALICE
-
ECAL silicon-tungsten
 Introduction with pictures
 Prototype design and construction
 R&D on the design of the full scale calorimeter
14
J-C. BRIENT (LLR)
Other R&D
Cooling of the readout
For the electronic
readout inside the
detector and if needed
by the dissipation of
the VFE
In progress
at LLR
- Study with SPICE and SAMCEF
- Small prototype to validate the simulation
- First response for Amsterdam 2003
Impact of e.m. shower on the VFE
Under preparation
By the LAL group
Collaboration is welcome
Collaboration is welcome
- First study with GEANT4
- Possibility to use the beam H4 (CERN)
with 200 GeV electron in 2003
- First response at the end of 2003
15
J-C. BRIENT (LLR)
 Global
simulation of the device with SPICE (static as well as dynamic simulation)
 Local simulation by finite
obtains by SPICE)
elements using SAMCEF (using the condition at the limit
 Correlation and validation of the
 Simulation of a
simulations by a small prototype
“large scale" detector slab and its environment.
Cooling channel
Heat points
(VFE chip)
Thermal sensors
In progress
at LLR
External
connections
Structure type H
PCB 1mm thick
(with wafers)
J-C. BRIENT (LLR)
Radiator
aluminium plate
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R&D – 1st results SPICE/SAMCEF
SPICE
V = Temperature
I = Calor flux
T8
T7
SAMCEF
T6
Temperature distribution :
T5
T4
T1
T2
Results :
T5
T6
T3 …
Conditions at the
limits
Degree K
T1 T2
T3
T7
T4
T8
T3
T2
T1
Point numbers
J-C. BRIENT (LLR)
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Conclusion
 The prototype design is almost fixed
 The prototype construction will begin soon
 Ready for a first test beam in 2004
 The R&D on the large scale detector are in progress
In both case,
collaboration with US labs. is welcomed
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J-C. BRIENT (LLR)