Implementing a Full Adder
on the Atlys Demo Board
Jeremy Sandoval
University of Washington
April 30, 2013
1
Last Week
• Step-by-step instructions for implementing a four bit adder
using previously written VHDL code
• Involved:
•
•
•
•
Creating a new project in ISE Project Navigator
Adding source .vhd files and User Constraint File to project
Editing UCF to use the board’s input and output pins
Synthesizing, Implementing Design and Generating Programming
file
• Uploading .bit file to Atlys board via Digilent Adept
2
This Week
• Writing the VHDL code for a single full adder
• Inputs: A, B, carry_in
• Outputs: sum, and carry_out
• Writing a simple Test Bench
• Running a functional simulation
• Following the same steps for synthesizing, implementing, and
generating the programming file
• Testing on the Atlys board
3
What is a Full Adder?
• A full adder performs addition of binary numbers with a carry bit from another
adder
• A single full adder will add two 1-bit numbers, A and B, with a carry_in bit from a
previous adder
• Carry_in and Carry_out represent overflow
• 0+0+1 = 1 = 01𝑏
• 0+1+1 = 2 = 10𝑏  Sum can only represent 1 bit, carry_out represents next binary digit
• 1+1+1 = 3 = 11𝑏
A
Carry_out
B
1-bit Full Adder
Carry_in
4
Sum
Designing a Full Adder
• Before writing VHDL module, need to find the boolean algebra
expression for Sum and Carry_out
• To do this, start with the truth table:
Carry_in
A
B
Sum
Carry_out
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
• Fill all combinations of input
values
• Fill in output values by adding
together Carry_in + A + B
• Example:
1 + 1 + 0 gives Sum = 0 with
Carry_out (overflow) = 1
5
Getting the Boolean Algebra
Sum and Carry_out Expressions
• Boolean algebra:
• NOT = !, example: !A
• AND = *, example: AB
• OR = +, example: A + B
• When Sum = 1 write all input cases when this is true:
• Sum = 1 = !C_i!AB + !C_iA!B + C_i!A!B + C_iAB
• C_0 = 1 = !C_iAB + C_i!AB + C_iA!B + C_iAB
• Simplifies to:
• Sum
= Ci XOR (A XOR B)
• Carry_out = A AND B OR C_i AND (A XOR B)
6
Writing VHDL Code
• Entity declaration outines the I/O signals of the circuit
• Arcitecture body describes the operation of the circuit
• This is where the sum and carry_out expressions are defined
7
Writing the Test Bench
• Want to test operation of circuit before implementing on
hardware
• With a test bench, the circuit can be simulated to view the
input and output signal waveforms
• Check for timing errors etc…
• When adding a testbench source to the project, the ports
(Inputs and Outputs) are automatically added
• Only need to comment out the clock code and then add the
test cases
• Want to simulate all possible input values (like the truth table)
8
Obtaining Simulation Waveforms
9
Define I/O in User Constraint File
• With simulation showing
correct operation of the
circuit, next step is to
implement design onto
board
• General UCF contains all of
the onboard inputs and
outputs
• Change the Net names to
match project I/O
• Comment out the rest
• LED 0  Sum
• LED 1  carry_out
• Switch0  A
• Switch1  B
• Switch2  carry_in
10
Implement Design
• Synthesize, Implement
Design and Generate
Programming File
11
Load .bit into SPI Flash
12
Test on FPGA
From left most switch:
!Carry_in + !B + A =
0+0+1=1
21
20
13
Test on FPGA cont…
From left most switch:
!Carry_in + B + A =
0+1+1=1
21
20
14
Test on FPGA cont…
From left most switch:
Carry_in + B + A =
1+1+1=3
21
20
15