Final Testbench: tb_final_shp.sv
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Message size = 505 bytes → 9 blocks
MD5 = 64 rounds/block
SHA1 = 80 rounds/block
SHA256 = 64 rounds/block
#cycles for 1 round/cycle = 9 * (80 + 64 + 64) =
1872
• Most implementations require around 2000
cycles (extra cycles needed for overhead)
• Not possible to take less than 1872 cycles
without unfolding (i.e., doing more than 1
round per cycle)
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Last Quarter: Top Delay Results
Design 1:
• #ALUTs = 6123, #Registers = 1335, Area = 7458
• Fmax = 136.370 MHz, #Cycles = 1772
• Delay = 12.994 microsec, Area*Delay = 96.910 millisec*area
Design 2:
• #ALUTs = 3926, #Registers = 1863, Area = 5789
• Fmax = 105.230 MHz, #Cycles = 1380
• Delay = 13.114 microsec, Area*Delay = 75.918 millisec*area
Design 3:
• #ALUTs = 2150, #Registers = 1172, Area = 3322
• Fmax = 142.960 MHz, #Cycles = 1934
• Delay = 13.528 microsec, Area*Delay = 44.941 millisec*area
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Last Quarter: Top Area/Delay Results
Design 1:
• #ALUTs = 2150, #Registers = 1172, Area = 3322
• Fmax = 142.960 MHz, #Cycles = 1934
• Delay = 13.528 microsec, Area*Delay = 44.941 millisec*area
Design 2:
• #ALUTs = 2132, #Registers = 1165, Area = 3297
• Fmax = 141.700 MHz, #Cycles = 2003
• Delay = 14.135 microsec, Area*Delay = 46.605 millisec*area
Design 3:
• #ALUTs = 2582, #Registers = 1271, Area = 3853
• Fmax = 138.310 MHz, #Cycles = 1971
• Delay = 14.251 microsec, Area*Delay = 54.908 millisec*area
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Last Quarter: Median Results
• Median Delay = 21.222 microsec
• Median Area*Delay = 99.461 millisec*area
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This Quarter: Minimum Passing
• Delay ≤ 50 microsec
• Area*Delay ≤ 300 millisec*area
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Quartus Optimization Modes
• You can use different optimization modes for “Delay” results and
“Area*Delay” Results (see menu under Compiler Settings)
• However, “Performance” mode sometimes lead to worse
performance and “Area” mode sometimes lead to worse area.
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