EGR 2131 Unit 2
Boolean Algebra and Logic Gates



Read Mano & Ciletti, Chapter 2.
Homework #2 and Lab #2 due next
week.
Quiz next week.
Reversing the Order of Topics in
Chapter 2

The textbook’s Chapter 2 starts with
very theoretical material (on Boolean
algebra) and ends with very practical
material (on logic gates). We’ll
reverse that order.
Logic Gates

Logic gates are the building blocks in
digital circuits. Shown below is a
circuit containing ten logic gates.
Inputs and Outputs

This circuit has three inputs (labeled
A, B, C) and one output (labeled X).
The values at the inputs determine the
value at the output.
Three Ways of Describing a Circuit

To describe a circuit built up from logic
gates, we can:
1. Draw a schematic
diagram.
2.
Write a truth table.
3.
Write a Boolean
expression. X = (AB′(A+C))′+A′B(A+B′+C′)′
Truth Tables and Boolean
Expressions


A truth table
shows a circuit’s
output value for
every possible
combination of
input values.
A Boolean expression looks much
like an algebraic expression and uses
symbols with special meanings.
X = (AB′(A+C))′+A′B(A+B′+C′)′
The Inverter
A
X
The inverter performs the Boolean NOT operation. When the
input is LOW (0), the output is HIGH (1); when the input is
HIGH, the output is LOW.
Input
Output
A
X
0
1
1
0
The NOT operation (complement) is shown with a prime.
Thus, the Boolean expression for an inverter is X = A′.
(Some books use an overbar: X = A)
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The Inverter
A
X
Example waveforms:
A
X
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The AND Gate
A
X
A
B
B
&
X
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is
Inputs Output
A
B
X
0
0
1
1
0
1
0
1
0
0
0
1
The AND operation is usually shown with a dot between the
variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
AND Gate: A Practical Application

Many cars have an alarm that sounds
if a door is open while the key is in the
ignition:
Door
Open?
Key in
Ignition?
No
No
No
Yes
Yes
No
Yes
Yes
Sound the
Alarm?
The AND Gate
A
B
X
A
B
&
X
Example waveforms:
A
B
X
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The AND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count down mode. XLA1 is a logic analyzer with the
output of the AND gate connected to first (upper) line of the
analyzer. What signal do you expect to on this line?
The output (line 1) will be
HIGH only when all of the
inputs are HIGH.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The OR Gate
A
B
X
A
B
≥1
X
The OR gate produces a HIGH output if any input is HIGH;
if all inputs are LOW, the output is LOW. For a 2-input gate,
the truth table is
Inputs Output
A
B
X
0
0
1
1
0
1
0
1
0
1
1
1
The OR operation is shown with a plus sign (+) between the
variables. Thus, the OR operation is written as X = A + B.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
OR Gate: A Practical Application

Many cars have a “Door Ajar”
dashboard light that lights up if any
door on the car is open.
Driver Door
Open?
Passenger
Door Open?
No
No
No
Yes
Yes
No
Yes
Yes
Turn on the
“Door Ajar”
Light?
The OR Gate
A
B
X
A
B
≥1
X
Example waveforms:
A
B
X
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The OR Gate
A Multisim circuit is shown. XWG1 is a word generator set
to count down. XLA1 is a logic analyzer with the output
connected to first (top) line of the analyzer. The three 2-input OR gates act
as a single 4-input gate. What signal do you expect on the output line?
The output (line 1) will be
HIGH if any input is HIGH;
otherwise it will be LOW.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The NAND Gate
A
A
X
&
X
B
B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is
Inputs Output
A
B
X
0
0
1
1
0
1
0
1
1
1
1
0
The NAND operation is shown with a dot between the
variables and a prime applied to the entire expression. Thus,
the NAND operation is written as X = (A .B)′
Or, omitting the dot, X = (AB)′
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The NAND Gate
A
B
X
A
&
X
B
Example waveforms:
A
B
X
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The NAND Gate
A Multisim circuit is shown. XWG1 is a word generator set in
the count up mode. A four-channel oscilloscope monitors the
inputs and output. What output signal do you expect to see?
The output (channel D) will be
LOW only when all of the
inputs are HIGH.
Inputs
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The NOR Gate
A
B
X
A
B
≥1
X
The NOR gate produces a LOW output if any input is
HIGH; if all inputs are LOW, the output is HIGH. For a
2-input gate, the truth table is
Inputs
Output
A
B
X
0
0
1
1
0
1
0
1
1
0
0
0
The NOR operation is shown with a plus sign (+) between
the variables and a prime applied to the entire expression.
Thus, the NOR operation is written as X = (A + B)′.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The NOR Gate
A
B
X
A
B
≥1
X
Example waveforms:
A
B
X
The NOR operation will produce a LOW if any input is HIGH.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Enable/Disable Using AND Gate
14
Enable/Disable Using OR Gate
15
Integrated Circuits
Cutaway view of DIP (Dual-In-line Package)
chip:
Plastic
Chip
case
Pins
The TTL series, available as DIPs are popular
for laboratory experiments with logic.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Integrated Circuits
DIP chips and surface mount chips
Pin 1
Dual in-line package
Small outline IC (SOIC)
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Figure 3.50 Pin configuration diagrams for some common gate configurations.
Digital Fundamentals, Tenth Edition
Thomas L. Floyd
Copyright ©2009 by Pearson Higher Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Website for Datasheets



Many websites have datasheets for
7400-series logic chips.
The best site is Texas Instruments:
www.ti.com
Type the chip number (such as 7404)
in the Search box.

For some chips, the original part number is
obsolete and no longer available. In such
cases, inserting LS often works. Example:
74LS10.
Chip Densities
•Caution: These are not precise terms, and different
authors use them differently.
•Small scale integration (SSI): <=10 gates per chip.
•Medium-scale integration (MSI): 10 to 1000 gates per
chip.
•Large-scale integration (LSI): 1000 to 10,000 gates
per chip.
•Very large-scale integration (VLSI): 10,000 to 100,000
gates per chip.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example of an MSI Chip:
74181 Arithmetic Logic Unit
Fixed-Function Chips Versus
Programmable Chips



The chips in the 7400 series are called
fixed-function chips because the
gates are permanently configured in a
certain way when the chip is
manufactured.
Thirty to 50 years ago, such chips were
used in the design of new products.
Today, programmable chips have
replaced fixed-function chips in new
designs.
Fixed-Function Chips Versus
Programmable Chips (Cont’d.)

Advantages of programmable chips over
fixed-function chips include:
 Reduced complexity of circuit boards





Lower power requirements
Less board space
Simpler testing procedures
Higher reliability
Design flexibility: chip can be
reprogrammed to function differently.
Programmable Logic Software
All manufacturers of programmable chips provide software
to support their products. The process is illustrated in the
flowchart.
The first step is to enter
the logic design into
a computer. It is done
in one of two ways:
1) Schematic entry
2) Text entry using a
hardware description
language (HDL).
Design entry
Schematic
HDL
Synthesis
Timing
simulation
Functional
simulation
Implementation
Device
programming
(downloading)
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Programmable Logic Software
Design entry
Schematic
HDL
In schematic entry, the design is drawn on a computer screen by
placing components and connecting then with simulated wires. After
drawing the schematic, it can be reduced to a single block symbol:
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Choices in Quartus II



In Quartus II you can place gates either using
generic names (such as and2) or using the
number of a 74XX-series chip.
To use the latter, you must
Type
Sample
Chips
know the 74XX number
for the chip you want.
2-inout NAND 7400
Some examples are listed
2-input AND
7408
here.
2-input OR
7432
Recall that Wikipedia has
a complete list of 74XX
7411
3-input AND
chips (not all of which
are available in Quartus.)
Choices in Quartus II (Cont’d.)

Generic:

74XX:
Programmable Logic Software
Design entry
Schematic
HDL
•In text entry, the design is entered via a hardware
description language (HDL).
•Learning an HDL takes longer than learning to do
schematic entry. But for complex designs it can provide a
more powerful and simpler way to enter designs.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Some Popular Hardware Description
Languages

Open-standard HDLs



VHDL (IEEE 1076)
Verilog (IEEE 1364)
Proprietary HDLs



CUPL
ABEL (Advanced Boolean Expression
Language, now owned by Xilinx)
AHDL (Altera HDL)
A VHDL Sample
One way of writing VHDL programs is to use Boolean-type statements.
There are two parts to such a program: the entity and the architecture.
The entity portion describes the I/O. The architecture portion describes
the logic. Following is a short VHDL program showing the two parts.
entity Example is
port (B,C,D: in bit; X: out bit);
end entity Example;
architecture Behavior of Example is
begin
X <= (B or C) and D;
end architecture Behavior;
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Simulation
Functional
simulation
After entering the circuit, the circuit is tested in a
simulation. You can test the circuit with waveforms to
verify the operation.
The following shows the functional test of a counter
using a waveform editor:
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Device Programming
Device
programming
(downloading)
The final step is to send the programming file from the
computer to the target device and test the implementation.
Shown is an Altera DE2-115 board with an Altera programmable chip,
along with switches, LEDs and many other I/O devices for testing
your design after you’ve downloaded it to the chip.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Our Software and Equipment


Software: Altera’s Quartus II, version
13.0 sp1. (Free download, so you can
install it at home.)
Hardware: Altera Cyclone IV chip
mounted on Altera’s DE2-115
experimenter’s board. (Manual on
course website.)
Minimization


Minimization means taking a digital
circuit and reduce it to a simpler but
equivalent circuit.
Example: The two circuits show below are
equivalent to each other. (In other words,
whenever you give them both the same
inputs, they’ll produce the same output.)
Two Primary Methods

The two primary manual minimization
methods use:
Boolean algebra: a set of rules that let
us transform Boolean expressions into
equivalent Boolean expressions.
2. Karnaugh maps (also called K-maps):
similar to truth tables.
The Karnaugh-map method provides a stepby-step procedure. If you follow the steps
correctly, you’ll get the right answer. The
Boolean-algebra method requires more
ingenuity on your part, but may be quicker.
1.

Boolean Algebra



Boolean algebra is a set of rules first
laid out by George Boole (1815-1864)
for manipulating Boolean expressions.
The rules are similar to the rules of
regular algebra for manipulating
numeric expressions.
Our book lists these rules as:
 8 postulates
 11 theorems
Other books may list these differently
and may list more or fewer rules.
The Book’s Approach


Our textbook approaches this material
in a very abstract way that a
mathematician would love but that an
engineer may not need.
You can skim Sections 2.2 and 2.3 of
the book, and don’t worry if you don’t
fully grasp this material.
The Book’s Approach (Cont’d.)

The main items of importance from
Sections 2.2 and 2.3 are the truth
tables for operators ·, +, and ′, which
are the same as the ones we’ve already
seen for AND, OR, and NOT gates:
Operator Precedence

Another important item from Section
2.3 is what you probably know as
“order of operations” from your math
classes.




You learned in math classes that
multiplication has a higher precedence than
addition.
Example: 4 + 2 · 6 = 16, not 36.
You also learned that you can use
parentheses to override this normal order
Example: (4 + 2) · 6 = 36, not 16.
Operator Precedence (Cont’d.)

In Boolean algebra the precedence of
the three operators from highest to
lowest is:
1.
2.
3.

′ (NOT)
· (AND)
+ (OR)
Just as in your math classes, we can
use parentheses to override this order.
Operator Precedence: Example

Consider the expression
x + y′ · z



First we complement y.
Then we AND the result with z.
Then we OR the result with x. In gates:
x
y
z

How would it differ if the expression were
(x + y)′ · z
Table 2.1. Postulates and Theorems
of Boolean Algebra

Following slides will look at these more
closely, but in a different order from
their listing here.
Commutativity (Postulate 3)
The postulate of commutativity states that:
The order in which variables are ORed makes no
difference. (Postulate 3(a))
x+y=y+x
The order in which variables are ANDed makes no
difference. (Postulate 3(b))
xy = yx
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Associativity (Theorem 4)
The theorem of associativity states that:
When ORing more than two variables, the result is the
same regardless of the grouping of the variables.
(Theorem 4(a))
x + (y + z) = (x + y) + z
When ANDing more than two variables, the result is
the same regardless of the grouping of the variables.
(Theorem 4(b))
x(yz) = (xy)z
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Distributivity (Postulate 4)
The first half of the postulate of distributivity is the
factoring law. It works the same as in ordinary algebra:
A common variable can be factored from an expression.
(Postulate 4(a))
x(y+ z) = xy + xz
We can extend this to the FOIL (First-Outer-Inner-Last)
rule that you’ve learned in math classes:
(x + y)(z + w) = xz + xw + yz + yw
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Distributivity (Postulate 4) (Cont’d.)
The second half of the postulate of distributivity is our first
difference between Boolean algebra and ordinary algebra.
The following is true in Boolean algebra but not in regular
algebra:
x + yz = (x + y)(x + z)
The OR operation is distributive over the AND
operation. (Postulate 4(b))
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
More Postulates and Theorems

The following rules should make sense if
you think in terms of logic gates:
Postulate 2(a). x + 0 = x
Theorem 2(b). x . 0 = 0
Theorem 2(a). x + 1 = 1
Postulate 2(b). x . 1 = x
Theorem 1(a). x + x = x
Theorem 1(b). x . x = x
Postulate 5(a). x + x′ = 1
Postulate 5(b). x . x′ = 0
Theorem 3. (x′ )′ = x
Applying the Rules

In the postulates and theorems laws on
the previous slides, you can replace any
single variable (such as x) with any
expression. For example:
.
 Theorem 2(b) says that x 0 = 0


More generally, any expression ANDed with
0 is equal to 0:
(x + yz + u′w) . 0 = 0
Another example:

Theorem 1(a) says that x + x = x

So (xy′ + zw) + (xy′ + zw) = xy′ + zw
DeMorgan’s Theorems (Theorem 5)
Theorem 5(a)
The complement of OR’d variables is equal to
the AND of the complemented variables.
(x + y)′ = x′ . y′
Above it was written with two variables, but it
applies more generally too. For example:
(x+y+z+w)′ = x′ . y′ . z′ . w′
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
DeMorgan’s Theorems (Theorem 5) (Cont’d.)
Theorem 5(b)
The complement of AND’ed variables is equal to
the OR of the complemented variables.
(xy)′ = x′ + y′
Above it was written with two variables, but it
applies more generally too. For example:
(xyzw)′ = x′ + y′ + z′ + w′
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
DeMorgan’s Theorems
Apply DeMorgan’s theorem to rewrite the
expression with no parentheses: X = (C′ + D)′.
Applying DeMorgan’s theorem to the expression,
we can move the outermost prime inside the
parentheses and apply it to each term as long as
we also change the sign between the terms. This
results in X = C′′ . D′.
Deleting the double prime on C gives X = C . D′.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Boolean Analysis of Logic Circuits
Combinational logic circuits can be analyzed by writing
the expression for each gate and combining the
expressions according to the rules for Boolean algebra.
Apply Boolean algebra to derive the expression for X.
Write the expression for each gate:
(A + B)′
A
(A + B)′C
B
X = (A + B)′C + D
C
D
Applying DeMorgan’s theorem:
X = (A′B′)C + D = A′ B′ C + D
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Review: Three Ways of Describing
a Circuit

To describe a circuit built up from logic
gates, we can:
1. Draw a schematic
diagram.
2.
Write a truth table.
3.
Write a Boolean
expression. X = (AB′(A+C))′+A′B(A+B′+C′)′
Boolean Functions


When we draw a schematic diagram,
or write a truth table, or write a
Boolean expression, we’re specifying a
Boolean function, which is a
relationship between input variables
and an output variable.
Every Boolean function has exactly
one truth table, but has many possible
Boolean expressions or schematic
diagrams.
Boolean Functions (Cont’d.)

When we apply a rule of Boolean
algebra to a Boolean expression, we
end up with a new Boolean
expression. But the original
expression and the new expression
describe the same Boolean function.
Boolean Functions: Example

The following two Boolean expressions
describe the same Boolean function,
whose truth table is
x
y
F
0
0
0
 xy
0
1
0
 xyy
1
0
0
1

1
1
There are infinitely many other Boolean
expressions (and also infinitely many
different schematic diagrams) that
describe this same Boolean function.
Complement of a Function


Given a Boolean function F, the
function’s complement, which we
denote F′, is the function that would
result from passing F through an
inverter.
If we have the truth table for F, we
can easily write the truth table for
F′ by simply changing all 0s in the
output column to 1s, and vice
versa.
Complement of a Function
(Cont’d.)

If we have a Boolean expression for F,
we can write a Boolean expression for
F′ by:
1.
2.

Changing each AND to OR and vice
versa. But see the caution on the next
slide.
Complementing each literal.
When we do these two steps we’re
using the generalized DeMorgan’s
theorem, which is a combination of
Theorems 5(a) and 5(b).
Complement of a Function:
Caution



Recall that AND has higher precedence
than OR, and so we can omit parentheses
when writing an expression such as
x + y · z, which is equivalent to
x + (y · z).
But when complementing an expression,
you must be careful to keep the same
order of operations. For example, the
complement of x + y · z is
x′ · (y′ + z′), not x′ · y′ + z′
Advice: Before complementing an
expression, write parentheses around all
ANDs, such as in x + (y · z).
Standard and Canonical Forms


As noted, a Boolean function can be
expressed by many different Boolean
expressions.
Four forms of Boolean expressions
have been given special names:


Standard forms
 Sum-of-products form
 Product-of-sums form
Canonical forms
 Sum-of-minterms form
 Product-of-maxterms form
Terminology: “Sums” and “Products”
By analogy with ordinary arithmetic, we say that variables
that are ORed together form a sum term.
Also, we say that variables that are ANDed together form a
product term.
The expression (A+B′+C)(D+E) is the product of
two sum terms.
The expression AB′ + C′ + A′BD is the sum of
three product terms.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Standard Form #1: Sum-of-Products Form
A Boolean expression is in sum-of-products form (SOP)
when it’s written as the sum of one or more products.
Three examples of expressions in SOP form:
A′ B′ + A B
A B C′ + C′ D
AB +ABC′ + D
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Standard Form #2: Product-of-Sums Form
In product-of-sums form (POS), two or more sum terms
are ANDed, as in the following three examples:
(A + B)(A′ + C)
(A + B + C′)(B + D)
(A′ + B)(B+C)D
In either SOP form or POS form, a prime cannot apply to
more than one variable.
Of the two standard forms, SOP is the more widely used
form.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Nonstandard Forms
Many Boolean expressions are in neither SOP form nor
POS form.
Example 1: AB + C(A′D + BD′)
Example 2: A′((B + C′)′ + BC) + (AB + AB′)C
But every expression can be converted to SOP form (or to
POS form) by applying some or all of the following:
DeMorgan’s theorem, the distributive law, and the “doubleprime” theorem.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Canonical Forms



The two canonical forms are special
cases of the two standard forms. In
particular:
Sum-of-minterms form is a special
case of sum-of-products form in
which every product term is a
minterm.
Product-of-maxterms form is a
special case of product-of-sums form
in which every sum term is a
maxterm.
Minterms



A minterm is a special kind of product
term in which every input variable
appears (either primed or unprimed).
Example: Suppose we’re working on a
problem with three input variables x, y,
and z. Some minterms are:
 xyz
 xy′z′
On the other hand, x′y is a product
term but not a minterm, since z is
missing.
Shorthand Notation for Minterms


It’s useful to assign a number to each
minterm by replacing each unprimed
variable with a 1 and each primed
variable with a 0.
Example (assuming three input
variables x, y, z):
 The minterm xy′z′ corresponds to the
binary number 100, which is decimal
4, so we’ll call it m4.
 Note that we use lowercase m for
minterms.
Maxterms



A maxterm is a special kind of sum
term in which every input variable
appears (either primed or unprimed).
Example: Suppose we’re working on a
problem with three input variables x, y,
and z. Some maxterms are:
 x + y′ + z
 x′ + y′ + z′
On the other hand, x′ + z is a sum term
but not a maxterm, since y is missing.
Shorthand Notation for Maxterms


It’s useful to assign a number to each
maxterm by replacing each unprimed
variable with a 0 and each primed
variable with a 1.
Example (assuming three input
variables x, y, z):
 The maxterm x+y′+z′ corresponds to
the binary number 011, which is
decimal 3, so we’ll call it M3.
 Note that we use uppercase M for
maxterms.
Minterms, Maxterms, and Truth
Tables

When setting up a truth table, we list all
possible values of the input variables. So
each row in a truth table corresponds to
one minterm and one maxterm, as
shown in the book’s Table 2.3.
Writing the Sum-of-Minterms
Expression from a Truth Table




Given the truth table for a function, it’s
easy to write the sum-of-minterms
expression for that function.
Step 1. For each row in the truth with a 1
in the output column, list the
corresponding minterm of the input
variables.
Step 2. Form the OR of the minterms
from Step 1.
See example on next slide…
Example
Write the sum-of-minterms expression from this truth table.
A
B
C
X
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0


A′BC′ = m2
A′BC = m3

AB′C
= m5
Answer: X = A′BC′ + A′BC + AB′C
= m2 + m3 + m5
= ∑(2, 3, 5)
Math symbol ∑ means “sum.”
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Writing the Product-of-Maxterms
Expression from a Truth Table




Given the truth table for a function, it’s
easy to write the product-of-maxterms
expression for that function.
Step 1. For each row in the truth with a 0
in the output column, list the
corresponding maxterm of the input
variables.
Step 2. Form the AND of the maxterms
from Step 1.
See example on next slide…
Example
Write the product-of-maxterms expression from this truth table.
A
B
C
X
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
 A+B+C = M0
 A′+B+C = M4
 A′+B′+C = M6
Answer: X = (A+B+C)(A′+B+C)(A′+B′+C)
= M0 M 4 M 6
= ∏(0, 4, 6) Math symbol ∏ means “product.”
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Writing the Truth Table for any SOP Expression
Given an SOP expression, it’s easy to write the truth table.
Step 1. Based on the number of input variables, build the
truth table’s input columns.
Step 2. For each product term in the SOP expression, place
a 1 in the truth table’s output column for all rows that make
the product term a 1.
Step 3. After completing Step 2 for all product terms in the
SOP expression, place a 0 in the output column for all other
rows.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Logic Diagram from Sum-ofProducts Expression



Given an SOP expression, it’s easy to
draw the corresponding logic diagram,
which will consist of a group of AND
gates followed by an OR gate.
Example: F1 = y′ + x′yz′ + xy
Note: We’ll assume that inputs are available in both normal
and complemented forms, without the need for inverters.
Logic Diagram from Product-ofSums Expression


Given a POS expression, it’s easy to draw
the corresponding logic diagram, which
will consist of a group of OR gates
followed by an AND gate.
Example: F2 = x(y′ + z)(x′ + y + z′)
Two-Level Implementations



The logic diagrams that we get from SOP or
POS expressions are called two-level
implementations because there are (at
most) two gates between inputs and
outputs.
Non-standard expressions may yield logic
diagrams with more than two levels.
Example: F3 = AB + C(D + E)
Two-Level Implementations
(Cont’d.)



Recall that every Boolean expression can be
converted to SOP form (or to POS form) by
applying some or all of the following:
DeMorgan’s theorem, the distributive law,
and the “double-prime” theorem.
Therefore every Boolean expression can be
implemented using no more than two levels.
Example: Convert F3 = AB + C(D + E) to
SOP form and then draw the corresponding
two-level logic diagram.
How Many Logical Operations?

You already know how to perform
some logical operations on two input
bits, A and B. Examples:


X = AB
X = A+B


Question: How many possible logical
operations are there on two input bits?
How Many Logical Ops? (Continued)

A
B
0
0
0
1
1
0
1
1
Let’s list them all: