CHIN. PHYS. LETT. Vol. 32, No. 6 (2015) 068301
Set Programming Method and Performance Improvement of Phase Change
Random Access Memory Arrays *
FAN Xi(范茜)1,2,3 , CHEN Hou-Peng(陈后鹏)1,2** , WANG Qian(王倩)1,2 , WANG Yue-Qing(王月青)1,2,3 ,
LV Shi-Long(吕士龙)1,2 , LIU Yan(刘燕)1,2 , SONG Zhi-Tang(宋志棠)1,2 ,
FENG Gao-Ming(冯高明)4 , LIU Bo(刘波)1,2
1
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information
Technology, Chinese Academy of Sciences, Shanghai 200050
2
Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and
Information Technology, Chinese Academy of Sciences, Shanghai 200050
3
University of Chinese Academy of Sciences, Beijing 100049
4
United Laboratory, Semiconductor Manufacturing International Corporation, Shanghai 201203
(Received 21 October 2014)
A novel slow-down set waveform is proposed to improve the set performance and a 1 kb phase change random
access memory chip fabricated with a 130 nm CMOS technology is implemented to investigate the set performance
by different set programming strategies based on this new set pulse. The amplitude difference (𝐼1 − 𝐼2 ) of the set
pulse is proved to be a crucial parameter for set programming. We observe and analyze the cell characteristics
with different 𝐼1 − 𝐼2 by means of thermal simulations and high-resolution transmission electron microscopy,
which reveal that an incomplete set programming will occur when the proposed slow-down pulse is set with
an improperly high 𝐼1 − 𝐼2 . This will lead to an amorphous residue in the active region. We also discuss the
programming method to avoid the set performance degradations.
PACS: 83.10.Tv, 85.30.−z, 85.35.−p, 85.40.−e, 81.07.−b
Recently, tremendous efforts have been made towards enhancing the set properties of the phase change
random access memory (PCRAM) chip, especially focusing on improving the uniformity of set resistances
and avoiding set failures in memory arrays.[1−3] Considering that the conventional rectangular set pulse
will generate a large resistance fluctuation and thus
limit the write reliability, some non-conventional optimized shapes of set pulses such as a set-sweep programming pulse,[4] stair-case pulse,[5] and multiple
step-down pulse[6] have been proposed to achieve a
better resistance uniformity. However, to the best of
our knowledge, these previous works only lie in evaluating the performance improvement on the PCRAM
chip from the point of view of the chip characterization. The impact on the cell’s physical characteristics
and the causes of set performance degradations under
different pulse conditions, which are crucial to give a
deeper insight on the PCRAM programming technology, are still unexplored.
In this Letter, we propose a new waveform of set
pulse to improve the set performance of the PCRAM
arrays. A 1 kb mushroom-shaped PCRAM array of
cells based on a 130 nm CMOS technology is used to
present a systematic investigation on the set properties with different set strategies numerically and
experimentally by measuring set resistance distributions and observing cell characteristics through thermal simulations as well as high-resolution transmission
DOI: 10.1088/0256-307X/32/6/068301
electron microscopy (HRTEM). A 70-nm-diameter
tungsten (W) bottom-electrode contact (BEC) with
doped TiN fabricated above a 200 nm W plug is utilized as a heater. An 100-nm-thick Ge2 Sb2 Te5 chalcogenide film is deposited above the W heater. A TiN
adhesive layer is stacked upon the chalcogenide film,
followed by the deposition of a W top-electrode contact (TEC) with a 200 nm diameter.
The new slow-down set waveform is composed of
two single pulses with different amplitudes and durations. As shown in the insets of Fig. 1(a), the first
set pulse with high amplitude (𝐼1 ) and short duration (𝑇1 ) is used to quickly heat the phase change
material (PCM) above the melting temperature (𝑇m ,
∼893 K). Then the second current pulse with low amplitude (𝐼2 ) and long duration (𝑇2 ) will cool down the
PCM from 𝑇m and finally realize a crystallization process. Compared with a typical rectangular set pulse,
the slow-down set pulse has a larger falling edge in the
time domain, which means a more efficient sweeping
around the optimal current points of all the memory
cells. Figure 1(a) shows a comparison of the resistance distributions based on the typical set pulse and
our proposed set pulse. The typical set current of the
traditional rectangular set pulse is ∼0.8 mA,[7] and the
current amplitude 𝐼2 of the slow-down set pulse is set
to be the same as that of the traditional set pulse
for an accurate comparison. It can be noted that the
proposed set pulse makes the set resistances more uni-
* Supported by the Strategic Priority Research Program of Chinese Academy of Sciences under Grant No XDA09020402, the National Key Basic Research Program of China under Grant Nos 2013CBA01900, 2010CB934300, 2011CBA00607, and 2011CB932804,
the National Integrate Circuit Research Program of China under Grant No 2009ZX02023-003, the National Natural Science Foundation of China under Grant Nos 61176122, 61106001, 61261160500, and 61376006, and the Science and Technology Council of
Shanghai under Grant Nos 12nm0503701, 13DZ2295700, 12QA1403900, and 13ZR1447200.
** Corresponding author. Email: [email protected]
© 2015 Chinese Physical Society and IOP Publishing Ltd
068301-1
CHIN. PHYS. LETT. Vol. 32, No. 6 (2015) 068301
strategy, especially in high-density memory arrays and
multi-level programmable applications. Thus we will
analyze how the pulse amplitudes (𝐼1 , 𝐼2 ) affect the
physical cell characteristics in detail in the following.
400
0.96 mA
1.28 mA
(a)
Current（mA）
2
1.92 mA
I1
0.64
Reset
Time (ns) 100
200
Number of bits
form in the lower resistance region with a lower programming power. Moreover, as shown in Fig. 1(b), the
set performance is increased at the cost of set time.[8]
However, it is worth noting that the minimum set time
for the correct write operation is only 120 ns. Compared with other non-conventional optimized shapes
of set pulses, this novel slow-down pulse achieves less
set time than the set-sweep programming pulse (150 ns
set time)[4] and stair-case pulse (150 ns set time),[5]
which could be attributed to a fast heating of the
first set pulse and an efficient sweeping of the second
set pulse. The multiple step-down pulse (180 ns set
time)[6] characterized by writing pauses needs more
set time due to these pauses. All the above test results
prove that the slow-down pulse exhibits better performances than other set technologies, which is contributing to a properly optimized pulse shape.
40
560
2.88 mA
0
0.80 mA
400
0.96 mA
0.64 mA
(b)
Current (mA)
2
1.6
I2
Reset
200
Time (ns) 100
40
560
0.48 mA
600 (a)
Current (mA)
2
1.44
0.80
Slow-down set
Traditional set Slow- down set
0
103
400
Number of bits
Time (ns) 100
2000 ns
1000 ns
400
100
Tranditional set
200
0
600 (b)
600
560 ns
240 ns
200
40
2
1.44
0.80
80 ns
104
106
107
Reset
40
T2
40 ns
0
103
105
Fig. 2. Resistance distributions after being programmed
by slow-down pulses with different amplitudes (a) 𝐼1 and
(b) 𝐼2 . All the cells are initialized to reset state by a rectangular pulse of 2 mA, 100 ns. The durations of the two
pulses are 𝑇1 = 40 ns and 𝑇2 = 560 ns, respectively. Insets: the pulse schematic diagram used to program the
PCRAM array.
Reset
Current (mA)
Time (ns) 100
104
Resistance (W)
560
105
106
107
Resistance (W)
Fig. 1. (a) Resistance distributions of the 1 kb PCRAM
array based on the traditional set pulse and the proposed
set pulse. (b) Resistance distributions of the 1 kb PCRAM
array after being programmed by the slow-down set pulses
with different durations (𝑇2 ). All the cells were initialized
to reset state by a rectangular pulse of 2 mA, 100 ns. Insets: the pulse schematics used to program the PCRAM
array.
Figures 2(a) and 2(b) characterize the set resistance distributions of the PCRAM array programmed
by the slow-down current pulses with different pulse
amplitudes (𝐼1 , 𝐼2 ). As viewed from the chip circuit
design, the first and second set amplitude can be adjusted from 0.96 mA to 2.88 mA and from 0.48 mA to
0.96 mA, respectively. As a result, we choose two relatively intermediate values (1.6 mA, 0.6 mA) and make
one of these two parameters fixed while change another one in a certain range. All the cells are initialized to reset state by a rectangular pulse (2 mA,
100 ns), which will avoid resistance cumulative effects.
The set resistance is increased and the uniformity is
decreased with increasing 𝐼1 − 𝐼2 . Even though the
amplitudes (𝐼1 , 𝐼2 ) of the two pulses should be high
and low respectively for the demands of rapid heating
and low power consumption, an undesired set failure
will probably occur when the amplitude discrepancy
(𝐼1 − 𝐼2 ) is further increased. Therefore, it is an important issue to carefully choose the set programming
To explore PCRAM cell characteristics based on
different programming strategies, a two-dimensional
thermal analysis of the PCRAM device is performed
for simulating the temperature distribution during a
set operation.[9,10] The cell is programmed by three
different pulses with shape-A, shape-B and shape-C,
respectively. The amplitudes of the shape-B pulse and
shape-C pulse satisfy the conditions as (𝐼1𝑏 > 𝐼1a ,
𝐼2b = 𝐼2a ) and (𝐼1c = 𝐼1a , 𝐼2c < 𝐼2a ), respectively,
where 𝐼𝑖𝑗 denotes the amplitude of the 𝑖th pulse with
shape 𝑗. It should be noted that the set power offered
from the chip for crystallization is much lower than
that for the transition to the closed-packed hexagonal phase. Therefore, Ge2 Sb2 Te5 is only converted
into the face-centered cubic (fcc) phase in the actual
chip programming situation,[3,11] and only the phase
transition between the amorphous phase and the fcc
phase is discussed here. First, as shown in Fig. 3(a),
after being programmed by the first set pulse with
shape-A, the core area above the BEC quickly reaches
the melting point and then changes into the molten
state, while the surrounding area with less heat efficiency is heated above the crystallization temperature (𝑇c , ∼423 K).[12] Then, as shown in Fig. 3(b), the
whole active region of the PCRAM cell cools down
and maintains at the crystallization point for a period
of time during the second set pulse. As a result, the
crystalline area covers the top of the BEC, indicating
a complete crystallization process. Secondly, when the
PCM cell is programmed by a shape-B pulse with a
higher 𝐼1 , as shown in Fig. 3(c), a higher temperature
can be reached and results in a larger molten volume.
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CHIN. PHYS. LETT. Vol. 32, No. 6 (2015) 068301
Moreover, during the second set pulse, the area above
BEC gathers more heat while still being maintained
at a temperature above 𝑇m and thus a residual amorphous state appears at the end of the pulse, as shown
in Fig. 3(d). Finally, for the case of a shape-C pulse, as
shown in Fig. 3(e), the temperature distribution and
the melted area are identical to those for the shape-A
pulse after the first set pulse melts the PCM cell due
to the same current amplitude (𝐼1c = 𝐼1a ). During the
first set pulse, the surrounding area of the active region is heated to a temperature between 𝑇m and 𝑇c for
a period of time and changed into the crystalline state.
However, as shown in Fig. 3(f), the temperature under 𝐼2c is much lower than that desired to transfer the
molten state to the crystalline state, thus this melted
area ends at the amorphous state.
(a)
TiN
Current
Shape-A
(b)
Current
I1a
I2a
cells, there is a small dome-shaped area distinguished
from other sections of the active region, which can be
observed more clearly in Fig. 4(b). Figure 4(c) further shows an obvious boundary between the crystalline state and the amorphous state. Furthermore,
the majority of the active area is in the crystalline
state, which is characterized by the selected-area electron diffraction (SAED) image, as shown in Fig. 4(d).
These images prove that the dome-shaped area caused
by set pulses with high 𝐼1 −𝐼2 is the amorphous residue
located at the center above BEC, which exhibits a high
resistance and thus leads to a relatively higher resistance than the complete crystalline state as shown in
the above resistance distribution tests.
(b)
(a)
PCM
Shape-A
Shape-A
residues
Time
423 K
423 K
893 K
Complete
crystallization
PCM
BEC
BEC
(d)
(c)
(c)
600
700
Current
893 K
(K)
300
900
800
Shape-B
423 K
350
400
(d)
450
500
Current
I1b
I1b
550 571
(2 0 0)
Shape-B
(2 2 2)
Time
Time
d(2 0 0)=3.04 Å
893 K
423 K
893 K
423 K
Incomplete
2000
2500
2900
423 K
(K)
300 400
500
(f)
Current
893 K
600
700
Current
Shape-C
I1c
800
897
Shape-C
I1c
I2c
I2c
Time
Time
423 K
893 K
Incomplete
crystallization
(K)
300
423 K
400
500
600
700
800
893 K
(K)
300
900
320
340
360
(0 2 2)
Amorphous
crystallization
(e)
Fcc
Crystalline d(2 0 0)=3.04 Å
I2b
I2b
423 K 893 K
(K)
300 500 1000 1500
Amorphous
I1a
I2a
Time
423 K
(K)
300 400
500
TiN
380
400
Fig. 3. Thermal profiles of a PCRAM cell after the first
set pulse operation with (a) shape-A, (c) shape-B and
(e) shape-C and the second set pulse operation with (b)
shape-A, (d) shape-B and (f) shape-C, respectively. Contour lines are shown to denote the molten region (within
white lines) and the crystalline region (between white lines
and blue lines). Insets: the pulse schematic diagram used
to program the PCRAM cell.
To further investigate the effect on the cell characteristics caused by programming pulses with high
𝐼1 − 𝐼2 , we examined the cross-sections of two samples
programmed respectively by the set pulses with high
𝐼1 (1.92 mA) and low 𝐼2 (0.48 mA) through HRTEM
scanning (the resistances of these two cells are both
about 30 kΩ), as shown in Fig. 4(a). In both the
Fig. 4. HRTEM images (a, b) of the cross-section of the
PCRAM cells. (c) HRTEM image of the boundary between two states (the 𝑑-spacing value of (200) in fcc phase
was measured with 𝑑(200) = 3.04 Å, which agrees well
with that in Ref. [13]). (d) SAED pattern of the crystalline
phase.
As discussed above, the pulse amplitudes (𝐼1 , 𝐼2 )
are crucial for the set performance, which are decreased with increasing 𝐼1 − 𝐼2 . Through the thermal
simulations, one can note that the set pulse with high
𝐼1 − 𝐼2 will result in insufficient set energy and thus
an amorphous residue will be achieved at the end of
the set operation. In addition, based on the result of
HRTEM, the area with the highest temperature will
receive the largest affection from the high 𝐼1 − 𝐼2 as
this area demands the highest set power for crystallizing. Therefore, if the set performance is not superior
enough, it would be considerably feasible to reduce
the amplitude difference (𝐼1 − 𝐼2 ) for a more efficient
heating. An alternative approach is to increase the
crystallization time (𝑇2 ) for a more complete crystallization, while at the cost of a long write time (see
Fig. 1(b)).
In summary, a novel slow-down set pulse with less
set time than other optimized set technologies is proposed and analyzed. The distributions of the set resistance are investigated in a 1 kb PCRAM array pro-
068301-3
CHIN. PHYS. LETT. Vol. 32, No. 6 (2015) 068301
grammed by the new slow-down set pulse with different programming strategies. The amplitude difference
(𝐼1 − 𝐼2 ) of the set pulse is proved to be a significant
parameter for high-performance set programming and
a high 𝐼1 − 𝐼2 will lead to a set performance degradation. This can be explained such that the crystallization power with high 𝐼1 − 𝐼2 is not sufficient
to maintain the whole active region (especially for
the high-temperature area) at the crystallization point
for plenty of time, thus an amorphous residue in the
hottest area will be obtained at the end of the set operation. Therefore, to improve the set performance of
the PCRAM array, the current amplitudes (𝐼1 , 𝐼2 ) of
the set pulse should be properly chosen to ensure a
relatively low 𝐼1 − 𝐼2 and simultaneously satisfy the
demands on low-power operations.
We thank Li Xi, Chen Yifeng, Gong Yuefeng and
Ji Xinglong for the helpful discussions.
References
[1] Philipp J B, Ruf B, Ruster C, Andres D, Majewski P, Kund
M, Happ T D and Bergmann R 2008 Proc. -Annu. NonVolatile Mem. Technol. Symp. NVMTS p 1
[2] Kang D H, Lee J H, Kong J H, Ha D, Yu J, Um C Y, Park
J H, Yeung F, Kim J H, Park W I, Jeon Y J, Lee M K,
Park J H, Song Y J, Oh J H and Jeong H S 2008 Dig Tech.
Pap. Symp. VLSI Technol. p 98
[3] Chen Y, Song Z, Chen X, Liu B, Xu C, Feng G, Wang L,
Zhong M and Feng S 2010 Chin. Phys. Lett. 27 107302
[4] Bedeschi F, Boffmo C, Bonizzoni E, Resta C, Torelli G and
Zella D 2006 Proc. IEEE Int. Symp. Circuits Syst. p 967
[5] Bedeschi F Bonizzoni E, Casagrande G, Gastaldi R, Resta
C, Torelli G and Zella D 2005 IEEE international symposium on circuits and systems (Kobe, Japan) p 1270
[6] Oh H R, Cho B H, Cho W Y, Kang S, Choi B, Kim H J,
Kim K S, Kim D E, Kwak C K, Byun H G, Jeong G T,
Jeong H S and Kim K 2006 IEEE J. Solid-State Circuits
41 122
[7] Xu L, Chen X, Song Z, Chen Y, Liu B, Chen H, Yang Z,
Wu G, Cai D, Feng G and Li Y 2013 Jpn. J. Appl. Phys.
52 014101
[8] Cai D, Chen H, Wang Q, Chen Y, Song Z, Wu G and Feng
S 2012 IEEE Electron Device Lett. 33 1270
[9] Gong Y, Song Z, Ling Y, Liu Y and Feng S 2009 Chin.
Phys. Lett. 26 118101
[10] Gong Y, Ling Y, Song Z and Feng S 2009 Jpn. J. Appl.
Phys. 48 064505
[11] Feiedrich I, Weidenhof, Njoroge W, Franz P and Wuttig M
2000 J. Appl. Phys. 87 4130
[12] Faraclas A, Williams N, Gokirmak A and Silva H2011 IEEE
Electron Device Lett. 32 1737
[13] Fillot F, Loubriat S, Gergaud P and Maitrejean S 2011
Electrochem. Solid-State Lett. 14 H285
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