CHAPTER 1
ACTIVATION OF REMOTE DEVICES
1.1 INTRODUCTION
In general Pseudo Random Binary Sequences are used in

Telecommunications

Encryption

Simulations

Information Hiding

Bit Error Rate Testing

Bit Error Rate Measurement
Our project is based on activating a device in remote area using Pseudo Random
Sequence Generator.
1.2 DEVICE ACTIVATION
Infrared technology can enable users to locate and access
street signs, or other
navigation devices. However it involves certain limitations – Line of sight: transmitters
and receivers must be almost directly aligned to communicate, Blocked by common
materials: people, walls, plants, etc. can block transmission ,Short range: performance
drops off with longer distances.
Pseudo Random Sequence Generator provides an alternative solution to activate a device
in remote area. The given appliance is assigned a particular sequence(password). This is
then compared with the generated pseudo random sequence. Only if the two sequences
match the device will be activated. This can be used for security purposes in banks,
offices and homes (safes, lockers and security vault).It can also be used for general
purpose appliances like motors, fans, tube lights etc.
1
CHAPTER 2
PSEUDO RANDOM SEQUENCE GENERATOR
2.1 INTRODUCTION
A PRBS (Pseudo Random Binary Sequence) is a binary PN (Pseudo-Noise)
signal. The sequence of binary 1’s and 0’s exhibits certain randomness and
autocorrelation properties. A PRBS is random in a sense that the value of an aj
element is independent of the values of any of the other elements, similar to real
random sequences. It is called pseudo-random since the pattern will start to repeat
itself after N bits. Thus the nature of the cycle is as follows:
–
The sequence has a finite number of integers
–
The sequence gets traversed in a particular order
–
The sequence repeats if the period of the generator is exceeded
–
The integers need not be distinct; that is, they may repeat.
Figure 2.1: Illustration of Pseudo Random Number Cycle
Figure 2.1 describes the cycle of the PRBS pattern, N, always has a ½ duty cycle and is
dependent on the number of flip-flops, k, in the LFSR. Their relationship can be
described by the equation:
N = 2^k-1.
The PRBS contains every N-bit pattern (except all 0's).
Conventional PRBS generator circuit is based on linear feedback shift registers.
2
2.2 LINEAR FEEDBACK SHIFT REGISTER
LFSR is an n-bit shift register which pseudo-randomly scrolls between 2n-1 values, but
does it very quickly because there is minimal combinational logic involved. Once it
reaches its final state, it will traverse the sequence exactly as before.
2.2.1 INTRODUCTION
One of the two main parts of an LFSR is the shift register (the other being the feedback
function). A shift register is a device whose identifying function is to shift its contents
into adjacent positions within the register or, in the case of the position on the end, out of
the register. The position on the other end is left empty unless some new content is
shifted into the register.
The contents of a shift register are usually thought of as being binary, that is, ones and
zeroes. If a shift register contains the bit pattern 1101, a shift (to the right in this case)
would result in the contents being 0110; another shift yields 0011. After two more shifts,
things tend to get boring since the shift register will never contain anything other than
zeroes.
Two uses for a shift register are:
1) convert between parallel and serial data
2) delay a serial bit stream.
The conversion function can go either way -- fill the shift register positions all at once
(parallel) and then shift them out (serial) or shift the contents into the register bit by bit
(serial) and then read the contents after the register is full (parallel). The delay function
simply shifts the bits from one end of the shift register to the other, providing a delay
equal to the length of the shift register.
Figure 2.2: A 3 Bit Shift Register
3
Figure 2.2 depicts a 3 bit shift register consists of a chain of flip-flops connected in
cascade, with the output of one flip-flop connected to the input of the next flip-flop. All
flip-flops receive a common clock pulse which causes the shift from one stage to the
next.
SOME NOMENCLATURE:
Clocking: One of the inputs to a shift register is the clock; a shift occurs in the
register when this clock input changes state from one to zero (or from zero to one,
depending on the implementation). From this, the term "clocking" has arisen to mean
activating a shift of the register. Sometimes the register is said to be "strobed" to cause
the shift.
Shift direction: A shift register can shift its contents in either direction depending
on how the device is designed. (Some registers have extra inputs that dictate the direction
of the shift.) For the purposes of this discussion, the shift direction will always be from
left to right.
Output: During a shift, the bit on the far right end of the shift register is moved out of
the register. This end bit position is often referred to as the output bit. To confuse matters
a bit, the bits that are shifted out of the register are also often referred to as output bits. To
really muddy the waters, every bit in the shift register is considered to be output during a
serial to parallel conversion. Happily, the context in which the term "output" is used
generally clears things up.
Input: After a shift, the bit on the left end of the shift register is left empty unless a
new bit (one not contained in the original contents) is put into it. This bit is sometimes
referred to as the input bit. As with the output bit, there are several different references to
input that are clarified by context.
4
2.2.2 FEEDBACK ACTION
In an LFSR, the bits contained in selected positions in the shift register are combined in
some sort of function and the result is fed back into the register's input bit. By definition,
the selected bit values are collected before the register is clocked and the result of the
feedback function is inserted into the shift register during the shift, filling the position
that is emptied as a result of the shift.
Feedback around an LFSR's shift register comes from a selection of points (taps) in the
register chain and constitutes XORing these taps to provide tap(s) back into the register.
Register bits that do not need an input tap, operate as a standard shift register. It is this
feedback that causes the register to loop through repetitive sequences of pseudo-random
value. The choice of taps determines how many values there are in a given sequence
before the sequence repeats. The implemented LFSR uses a one-to-many structure, rather
than a many-to-one structure, since this structure always has the shortest clock-to-clock
delay path.
The feedback is done so as to make the system more stable and free from errors. Specific
taps are taken from the tapping points and then by using the XOR operation on them they
are feedback into the registers. The bit positions selected for use in the feedback function
are called "taps". The list of the taps is known as the "tap sequence". By convention, the
output bit of an LFSR that is n bits long is the nth bit; the input bit of an LFSR is bit 1.
2.2.3 TAPPING ACTION
An LFSR is one of a class of devices known as state machines. The contents of the
register, the bits tapped for the feedback function, and the output of the feedback function
together describe the state of the LFSR. With each shift, the LFSR moves to a new state.
(There is one exception to this -- when the contents of the register are all zeroes, the
LFSR will never change state.) For any given state, there can be only one succeeding
state. The state of an LFSR that is n bits long can be any one of 2^n different values. The
largest state space possible for such an LFSR will be 2^n - 1 (all possible values minus
the zero state). Because each state can have only once succeeding state, an LFSR with a
maximal length tap sequence will pass through every non-zero state once and only once
5
before repeating a state.One corollary to this behavior is the output bit stream. The period
of an LFSR is definedas the length of the stream before it repeats. The period, like the
state space, is tied to thetap sequence and the starting value. As a matter of fact, the
period is equal to the size ofthe state space. The longest period possible corresponds to
the largest possible state space, which is produced by a maximal length tap sequence.
2.3 PROPERTIES OF PRBS
Uncorrelated Sequences:
The sequences of random numbers should be serially uncorrelated
Long Period:
The generator should be of long period (ideally, the generator should not repeat;
practically, the repetition should occur only after the generation of a very large set of
random numbers).
Uniformity:
The sequence of random numbers should be uniform, and unbiased. That is, equal
fractions of random numbers should fall into equal ``areas'' in space. For example, if
random numbers on [0,1) are to be generated, it would be poor practice were more than
half to fall into [0, 0.1), presuming the sample size is sufficiently large.
Efficiency :
The generator should be efficient. Low overhead for massively parallel computations.
6
CHAPTER 3
GENERATION OF PSEUDO RANDOM SEQUENCE
3.1 INTRODUCTION
The generation of Pseudo Random Sequence is based on the principle of Linear Feedback
Shift Register which uses D Flip Flops - IC 7474 and EXOR- IC 7486.The outputs from
second and third flip flop are EXORed and fed back to the first flip flop.
3.2 IC 7474
3.2.1 INTRODUCTION
The D flip-flop is the most common flip-flop in use today. It is better known
as data or delay flip-flop (as its output Q looks like a delay of input D). The Q output
takes on the state of the D input at the moment of a positive edge at the clock pin (or
negative edge if the clock input is active low). It is called the D flip-flop for this reason,
since the output takes the value of the D input or data input, and delays it by one clock
cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold,
or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.
Figure 3.1: Pin Diagram of IC 7474
7
Figure 3.1 depicts the pin diagram of IC 7474 .Pin 7 is grounded and power supply is
given to pin 14.CLK indicates clock ,D is the input while Q is the output.
3.2.2 PIN CONFIGURATION
IC 7474 is a fourteen pin IC. The name and the function of the fourteen pins are
tabulated as follows,
PIN NUMBER
DESCRIPTION
1
Clear 1 Input
2
D1 Input
3
Clock 1 Input
4
Preset 1 Input
5
Q1 Output
6
Complement Q1 Output
7
Ground
8
Complement Q2 Output
9
Q2 Output
10
Preset 2 Input
11
Clock 2 Input
12
D2 Input
13
Clear 2 Input
14
Positive Supply
Table 3.1: Pin Configuration of IC 7474
Table 3.1 gives a detail description about each pin in the IC 7474.
8
3.3 IC 7486
3.3.1 INTRODUCTION
The EXOR gate (sometimes EOR gate, or XOR gate) is a digital logic gate that
implements an exclusive disjunction; that is, it behaves according to the truth table shown
below. A true output (1) results if one, and only one, of the inputs to the gate is true (1). If
both inputs are false (0) or both are true (1), a false output (0) results. A way to remember
XOR is "one or the other but not both". It represents the inequality function, i.e., the
output is HIGH (1) if the inputs are not alike otherwise the output is LOW (0).
Figure 3.2: Pin Diagram of IC 7486
Figure 3.2 depicts the pin diagram of IC 7486 .Pin 7 is grounded and power supply is
given to pin 14.A and B represents the pair of inputs -1 and 2 ; 4 and 5 ; 9 and 10 ; 12 and
13 , Y represents output – 3 ,6 ,8, 11 .
INPUT A
INPUT B
OUTPUT
0
0
0
0
1
1
1
0
1
1
1
0
Table 3.2: Truth Table for IC 7486
Table 3.2 lists the outputs for various combinations of inputs.
9
3.3.2 PIN CONFIGURATION
IC 7486 is a fourteen pin IC. The name and the function of the fourteen pins are
tabulated as follows,
PIN NUMBER
DESCRIPTION
1,2
Input
3
Output
4,5
Input
6
Output
7
Ground
8
Output
9,10
Input
11
Output
12,13
Input
14
VCC-Positive supply
+5V
Table 3.3: Pin configuration of IC 7486.
Table 3.3 gives a detail description about each pin in the IC 7486.
10
CHAPTER 4
HARDWARE IMPLEMENTATION
4.1 CIRCUIT DIAGRAM OF PRBS
A shift register is an n-bit register with provision for shifting its stored data by one
position at each clock pulse. The logical configuration of a shift register consists of a
chain of flip-flops connected in cascade, with the output of one flip-flop connected to the
input of the next flip-flop. All flip-flops receive a common clock pulse which causes the
shift from one stage to the next. The clock is given to the third pin of all three flip
flops.The outputs from second and third flip flops are XORed together and fed as a input
to the first flip flop.Since it is a 3-bit Pseudo random sequence generator ,it generates
sequences cycles between 0 and 7.
Figure 4.1: Circuit Diagram of PRBS
11
Figure 4.1 describes the circuit diagram of PRBS which uses D Flip Flops - IC 7474 and
EXOR- IC 7486.The outputs from second and third flip flop are EXORed and fed back to
the first flip flop.
4.2 EQUALITY DETECTOR ( IC 74HC688)
4.2.1 INTRODUCTION
This equality detector utilizes advanced silicon-gate CMOS technology to compare bit
for bit two 8-bit words and indicate whether or not they are equal .The P and Q output
indicates equality, when it is low A single active low enable is provided to facilitate
cascading of several packages and enable comparison of words greater than 8 bits. This
device is useful in Memory block decoding applications where Memory block enable
signals must be generated from computer address information .The Comparator combines
the low power consumption of CMOS but inputs are compatible with TTL logic levels
and the output can drive 10 low power Schottky equivalent loads. MM54HCT
MM74HCT devices are intended to Interface between TTL and NMOS components and
standard CMOS devices. These parts are also plug in replacements for LSTTL devices
and can be used to reduce power consumption in existing designs. All inputs are
protected from damage due to static discharge by Diodes to VCC and ground.
Figure 4.2: Pin Diagram of IC 74HC688
12
Figure 4.2 depicts the pin diagram of IC 74HC688 .Pin 10 is grounded and power supply
is given to pin 20.Inputs for comparision are given to P and Q. Pin 1 is enable and pin 19
is output.
4.2.2 PIN CONFIGURATION
IC 74HC688 is a twenty pin IC. The name and the function of the twenty pins are
tabulated as follows,
PIN NUMBER
DESCRIPTION
1
Enable input(Active low)
2,4,6,8,11,13,15,17
Word inputs
3,5,7,9,12,14,16,18
Word inputs
10
Ground
19
Output
20
Vcc – positive supply
Table 4.1: Pin Configuration of IC 74HC688
Table 4.1 gives a detail description about each pin in the IC 74HC688.
DATA(P,Q)
ENABLE(G)
OUTPUT(P`=Q`)
P=Q
L
L
P>Q
L
H
P<Q
L
H
X
H
H
Table 4.2:Truth Table for IC 74HC688
Table 4.2 describes the possible data combinations and the corresponding outputs for the
IC 74HC688.It can be observed that only as long as enable is low, comparison of inputs
takes place.
13
4.3 BLOCK DIAGRAM FOR COMPARISON
The input sequence for the given device is supplied to the equality detector using the
trainer kit. The other input to the detector is the generated pseudo random sequence.
Since the IC 74HC688 has an active low output, this is further given to a NOT gate IC
7404. The output of the NOT gate is given to the LED. Here the LED is used to represent
a device. The LED glows only when the two sequences are matched. Thus the PRBS
generator in combination with the equality detector can be used to activate any appliance.
The block diagram representing this is illustrated in the figure below:
Figure 4.3: Block diagram for comparison
Figure 4.3 illustrates PRBS generator in combination with the equality detector that can
be used to activate LED.
14
CHAPTER 5
SNAPSHOT
A digital trainer kit has been used to supply an input sequence, clock, power supply,
ground and enable to the dot board.
15
CHAPTER 6
CONCLUSION
A 3-bit PRBS is realized by shifting the input through the D-flip flops and feeding back
the outputs of some flip-flops known as taps again into the first flip-flop after passing
them through an XOR gate. The second and third taps are used to obtain the pseudo
random sequences. The sequence generated is then compared with the input given
through the trainer kit using equality detector. Initially when the reset is kept at high the
output of the equality detector remains high always and hence the LED does not glow.
However as soon as the reset is made low the equality detector starts comparing the input
sequence and the generated sequence. When the sequences match, the device can be
activated.
16
REFERENCES
[1].Digital Design (4th Edition) by M. Morris Mano, Michael D. Ciletti Prentice Hall; 4
edition.
[2].http://wn.com/Pseudorandom_generator.
[3].www.wikipedia.com
[4].http://mfukar.posterous.com/linear-feedback-shift-registers-as-prbs-gene.
[5].The Art of Electronics, 2nd Edition, Horowitz and Hill,1989.
[6].www.egr.uh.edu/courses/ece/...files/D1_01_PRBS_generation.pdf.
17