Lab 6
Program Counter and
Program ROM
Mano & Kime
Sections 7-1 – 7-6
SW(1:8)
Program
Counter
Lab6
pload
clr
clk
PC
‘1’
pinc
ldg
P
LD(1:8)
Prom
M
y
M
clr
clk
ireg
d
msel(1:0)
c
b
tin
pinc
debounce
tload
digload
fcode(5:0)
clr
clk
T
iload
Pcontrol
pload
clr
clr
clk
N
clk
cclk
led
a
Funit1
fcode(5:0)
clr
clk
clr cclk
IBUFG
T
b
T
bn
nload
Nreg
T
clk
clkdiv
tload
Treg
nload
M
mclk
a
mux4
icode
BTN4
N
iload
y
DigDisplay
digload
A(1:4)
AtoG(6:0)
Program Counter, PC
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity PC is
port (
d: in STD_LOGIC_VECTOR (15 downto 0);
clr: in STD_LOGIC;
clk: in STD_LOGIC;
inc: in STD_LOGIC;
pload: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (15 downto 0)
);
end PC;
architecture PC_arch of PC is
signal COUNT: STD_LOGIC_VECTOR (15 downto 0);
begin
process (clk, clr)
begin
if clr = '1' then
COUNT <= "0000000000000000";
elsif clk'event and clk='1' then
if pload = '0' then
if inc = '1' then
COUNT <= COUNT + 1;
end if;
else
COUNT <= d;
end if;
end if;
q <= COUNT;
end process;
end PC_arch;
SW(1:8)
Lab6
Program
ROM
pload
clr
clk
PC
‘1’
pinc
LD(1:8)
Prom
M
y
M
clr
clk
ireg
d
msel(1:0)
c
b
debounce
tload
clr
clk
T
iload
Pcontrol
pload
clr
clr
clk
N
clk
cclk
led
a
Funit1
fcode(5:0)
clr
clk
clr cclk
IBUFG
T
b
T
bn
nload
Nreg
T
clk
clkdiv
tload
Treg
nload
M
mclk
a
mux4
tin
pinc
digload
fcode(5:0)
N
iload
icode
BTN4
ldg
P
y
DigDisplay
digload
A(1:4)
AtoG(6:0)
package opcodes is
subtype opcode is std_logic_vector(15
-- Register instructions
constant nop:
opcode :=
constant dup:
opcode :=
constant swap:
opcode :=
-- Function unit instructions
constant plus:
opcode :=
constant minus:
opcode :=
constant plus1:
opcode :=
constant minus1:
opcode :=
constant invert:
opcode :=
constant andd:
opcode :=
constant orr:
opcode :=
constant xorr:
opcode :=
constant twotimes:
opcode :=
constant u2slash:
opcode :=
constant twoslash:
opcode :=
constant rshift:
opcode :=
constant lshift:
opcode :=
constant ones:
opcode :=
constant zeros:
opcode :=
downto 0);
--WHYP WORDS
X"0000"; -- NOP
X"0001"; -- DUP
X"0002"; -- SWAP
X"0010";
X"0011";
X"0012";
X"0013";
X"0014";
X"0015";
X"0016";
X"0017";
X"0018";
X"0019";
X"001A";
X"001B";
X"001C";
X"0020";
X"0021";
----------------
+
1+
1INVERT
AND
OR
XOR
2*
U2/
2/
RSHIFT
LSHIFT
TRUE
FALSE
constant zeroequal:
constant zeroless:
constant ugt:
constant ult:
constant eq:
constant ugte:
constant ulte:
constant neq:
constant gt:
constant lt:
constant gte:
constant lte:
-- I/O instructions
constant sfetch:
constant digstore:
opcode
opcode
opcode
opcode
opcode
opcode
opcode
opcode
opcode
opcode
opcode
opcode
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
:=
X"0022";
X"0023";
X"0024";
X"0025";
X"0026";
X"0027";
X"0028";
X"0029";
X"002A";
X"002B";
X"002C";
X"002D";
opcode := X"0037";
opcode := X"0038";
-- Transfer instructions
constant lit:
opcode
constant jmp:
opcode
constant jz:
opcode
constant jb4HI:
opcode
constant jb4LO:
opcode
end opcodes;
:=
:=
:=
:=
:=
X"0100";
X"0101";
X"0102";
X"010D";
X"0109";
-------------
0=
0<
U>
U<
=
U>=
U<=
<>
>
<
>=
<=
-- S@
-- DIG!
-----
LIT
AGAIN, ELSE
IF, UNTIL
waitB4
\ WHYP program to multiply switch settings by 10
HEX
: MAIN ( -- )
BEGIN
waitBTN4
S@
DIG!
waitBTN4
2*
DUP
2*
2*
+
DIG!
AGAIN ;
\
\
\
\
\
\
\
\
\
\
wait to push BTN4
3B
n
3B
n
3B wait to push BTN4
76
2n
76 76
2n 2n
76 EC
2n 4n
76 1D8
2n 8n
24E
10n
24E
Compilation of waitBTN4
waitBTN4
0000
JB4HI, X"0000",
-- X"00" wait for BTN4 up
0002
JB4LO, X"0002",
-- X"02" wait for BTN4
Note:
BTN4 is ‘0’ or LO when not pressed
BTN4 is ‘1’ or HI when pressed
Program ROM, Prom6
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.opcodes.all;
entity Prom6 is
port (
addr: in STD_LOGIC_VECTOR (15 downto 0);
M: out STD_LOGIC_VECTOR (15 downto 0)
);
end Prom6;
architecture Prom6_arch of Prom6 is
subtype tword is std_logic_vector(15 downto 0);
type rom_array is array (0 to 18) of tword;
constant rom: rom_array := (
JB4HI, X"0000",
-- X"00" wait for BTN4 up
JB4LO, X"0002",
-- X"02" wait for BTN4
SFETCH,
-- X"04" push switches
digstore,
-- X"05" display
JB4HI, X"0006",
-- X"06" wait for BTN4 up
JB4LO, X"0008",
-- X"08" wait for BTN4
twotimes,
-- X"0A" 2*
DUP,
-- X"0B" DUP
twotimes,
-- X"0C" 2*
twotimes,
-- X"0D" 2*
plus,
-- X"0E" +
digstore,
-- X"0F" display
JMP, X"0000",
-- X"10" GOTO 0
X"0000"
-- X"12"
);
begin
process(addr)
variable j: integer;
begin
j := conv_integer(addr);
M <= rom(j);
end process;
end Prom6_arch;
SW(1:8)
Lab6
pload
clr
clk
PC
‘1’
pinc
ldg
P
LD(1:8)
Prom
M
y
M
clr
clk
ireg
d
msel(1:0)
c
b
tin
pinc
debounce
tload
digload
fcode(5:0)
clr
clk
T
iload
Pcontrol
pload
clr
clr
clk
N
clk
cclk
a
Funit1
fcode(5:0)
clr
clk
clr cclk
IBUFG
T
b
T
bn
nload
Nreg
T
clk
clkdiv
tload
Treg
nload
M
mclk
a
mux4
icode
BTN4
N
iload
y
DigDisplay
digload
Digit
Display
led
A(1:4)
AtoG(6:0)
dig7seg.vhd
dig7seg
dig1(3:0)
a
dig2(3:0)
b
dig3(3:0)
c
dig4(3:0)
d
Mux4g
y
y1
seg7dec
AtoG(6:0)
sel
Acode
q1(1:0)
bnbuf
Asel(1:0)
A(1:4)
clr
cclk
clk
q
ctr2bit
anode(1:4)
Aen(1:4)
A(1:4)
digdisplay.vhd
digdisplay
digload
dig7seg
load
T1(15:12)
T1(11:8)
T(15:0)
reg
T1(7:4)
T1(3:0)
clk
a
b
Mux4g
y
y1
seg7dec
c
d
clr
sel
Acode
clk
bnbuf
q1(1:0)
Asel(1:0)
A(1:4)
clr
cclk
AtoG(6:0)
clk
Aen(1:4)
q
ctr2bit
“1111”
A(1:4)