ECE3030 Physical Foundations of Computer Engineering, Fall 2015
Homework 11 Solutions
1) (30 pts.) You are given a 65nm n-type transistor with a threshold voltage of VTN = 0.2V,
a transconductance of k’ = 750 microamps/V2 and a W/L of 1.5. Assuming that the
transistor is fully on (i.e., VG = VDD), you find the effective resistance for the transistor
assuming a power supply voltage of VDD = 1.2V. For Id, you use the following equations:
𝐼𝑙𝑖𝑛 =
𝑊
1
𝑘′ [(𝑉𝐺𝑆 − 𝑉𝑇𝑁 )𝑉𝐷𝑆 − 𝑉𝐷𝑆 2 ]
𝐿
2
𝐼𝑠𝑎𝑡 =
𝑊 1
𝑘′ (𝑉 − 𝑉𝑇𝑁 )2
𝐿 2 𝐺𝑠
As described in the solution to homework 8, the final effective resistance for VGS = VDD
is found to be the following:
𝑅𝑡 =
𝑅𝑙𝑖𝑛 + 𝑅𝑠𝑎𝑡 1.19 + 1.96
=
kΩ = 1.58 kΩ
2
2
Finally, the speed-power product is defined as clock cycle time multiplied by power.
Clock cycle time is the inverse of the clock frequency.
NOTE: for full credit, clearly identify your answer to each question below (e.g., part a
has two questions and part b has three) as well as show the correct units (e.g., Amps).
Prelude Q1:
Note 1: The transistor is operating always in the saturation region.
Note 2: We are in the dynamic regime.
Note 3: Static energy is related to sub-threshold currents and leakage currents.
Note 4: Discussion is in the framework of RC model which provides information about
the dynamic behavior but not about the static one.
Speed-power product is defined as
𝑆𝑃 =
1
𝑃
𝑓
where f is the operation frequency of the transistor (CLK signal). As we neglect static
power, power in this calculation is purely dynamic.
The dynamic power can be written as
𝑃𝑑 =
𝐸𝑑
1
1
= 𝑓𝐸𝑑 = 𝑓(𝐸𝑑,𝑓 + 𝐸𝑑,𝑟 ) = 𝑓 ( 𝐶𝑉𝐷𝐷 2 + 𝐶𝑉𝐷𝐷 2 ) = 𝑓𝐶𝑉𝐷𝐷 2
𝑡
2
2
where 𝐸𝑑 is the enegy stored in the capacitor.
Speed-power product can be written by including the specific equation for dynamic power
as
𝑆𝑃 =
1
1
𝑃 = 𝑓𝐶𝑉𝐷𝐷 2 = 𝐶𝑉𝐷𝐷 2
𝑓
𝑓
Note that the this expression is independent of frequency and resistance of the transistor.
a) (5 pts.) Assuming a load capacitance of 0.9 fF and VGS = VDD = 1.2 V, what is the
maximum speed of this transistor? For speed (clock cycle time), use resistance
multiplied by capacitance (RC) to estimate the clock cycle time (do not worry about
rise time versus fall time, etc. – just simply assume that the effective resistance times
the load capacitance yields a result in seconds which is the clock cycle time). What is
the rate of energy consumption (i.e., power) for this transistor?
Clock cycle time
𝜏 = 𝑅𝑡 𝐶𝐿 = (1.58 kΩ)(0.90 fF) = 1.4 ps
Frequency associated to the clock cycle time
𝑓 = 1/𝜏 = 714.3 GHz
Power
𝑃𝑑 = 𝑓𝐶𝑉𝐷𝐷 2 = (714.3 GHz)(0.90 fF)(1.2 V)2 = 925.7 μW
Or
𝑃𝑑 =
𝑉𝐷𝐷 2 (1.2 V)2
=
= 911.4 μW
𝑅𝑡
1.58 kΩ
Differences in power calculations come from round-off. Error is in the order of 1.6 %  though.
b) (10 pts.) Assume a load capacitance of 0.9 fF and VGS = VDD = 1.1 V. What is the
speed of this transistor? What is the power of this transistor? What is the speedpower
product for this transistor?
Please note that Ilin and Isat change as VGS changes. This causes a change in Rt.
Rt needs to be recalculated as in previous HWs. After the calculation this value is
approximately 1.76 k𝛺 for this new condition.
Clock cycle time
𝜏 = 𝑅𝑡 𝐶𝐿 = (1.76 kΩ)(0.90 fF) = 1.6 ps
Frequency associated to the clock cycle time
𝑓 = 1/𝜏 = 631.3 GHz
Power
𝑃𝑑 = 𝑓𝐶𝑉𝐷𝐷 2 = (631.3 GHz)(0.90 fF)(1.1 V)2 = 687.5 μW
Or
𝑃𝑑 =
𝑉𝐷𝐷 2 (1.1 V)2
=
= 687.5 μW
𝑅𝑡
1.76 kΩ
Speed-power product can be calculated as
𝑆𝑃 = 𝐶𝑉𝐷𝐷 2 = (0.9 ∗ 10−15 )(1.1)2
𝑆𝑃 = 1.089 ∗ 10−15 J
c) (15 pts.) Assuming a load capacitance of 0.9 fF, plot two graphs – one for speed and
the second for power – for this transistor over a range of voltages from 0.7 V to 1.2 V.
Please have VDD on the x-axis in increments of 0.1 V, and have speed (in seconds)
or power on the y-axis with an appropriate range of values and increments in terms of
tick-marks (dashes) on the graph.
You are required to properly label the graph with the correct units. What can you say
about the speed, power and speedpower product as the voltage used to represent ‘1’
ranges from 0.7 to 1.2 V?
While speed (Fig. 1.1) increases (i.e. shorter times), what is positive for applications
in processing of information, by increasing the Vdd, as expected, the power is also
increased (Fig. 1.2). This is not desirable in current applications where life-time of
batteries might be a constraint. The speed-power product increases in a quadractic
fashion as a function of Vdd (Fig. 1.3).
-12
5
Speed (s) VS Vdd (V)
x 10
Speed
4.5
4
3.5
Speed (s)
3
2.5
2
1.5
1
0.5
0
0.5
0.6
0.7
0.8
0.9
1
Vdd (V)
1.1
1.2
Fig. 1.1. Speed as a function of Vdd
1.3
1.4
1.5
-3
1
Power (W) VS Vdd (V)
x 10
Power
0.9
0.8
0.7
Power (W)
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.6
0.7
0.8
0.9
1
Vdd (V)
1.1
1.2
1.3
1.4
1.5
Fig. 1.2. Power as a function of Vdd
-15
Speed-Power (J) VS Vdd (V)
x 10
Speed-Power
Speed-Power (J)
1
0.5
0
0.5
0.6
0.7
0.8
0.9
1
Vdd (V)
1.1
1.2
1.3
Fig. 1.3. Speed-Power product as a function of Vdd
1.4
1.5
clear all
clc
close all
C = 0.9E-15;
Vtn = 0.2;
Vdd = [0.7 0.8 0.9 1.0 1.1 1.2];
Vds=Vdd;
Vgs = Vds;
VDsat = Vds-Vtn;
WoverL=1.5;
k=750E-6;
coeff=WoverL*k;
Vlin = VDsat./2;
Ilin = coeff*(3/8)*VDsat.^2;
Rlin = Vlin./Ilin;
Vsat = 0.5*(VDsat+Vdd);
Isat = coeff*0.5*(VDsat).^2;
Rsat = Vsat./Isat;
Rtot = 0.5*(Rlin+Rsat);
Tau = Rtot*C;
f = 1./Tau
Pdyna = f.*C.*(Vdd).^2;
Pelec = ((Vdd).^2)./Rtot;
SpeedPower = C.*(Vdd).^2
figure
plot(Vdd,Tau,'*--')
title('Speed (s) VS Vdd (V)')
legend('Speed')
axis([0.5,1.5,0E-12,5E-12])
xlabel('Vdd (V)')
ylabel('Speed (s)')
figure
plot(Vdd,Pdyna,'o--')
title('Power (W) VS Vdd (V)')
axis([0.5,1.5,0E-6,1000E-6])
legend('Power')
xlabel('Vdd (V)')
ylabel('Power (W)')
figure
plot(Vdd,SpeedPower,'+--')
title('Speed-Power (J) VS Vdd (V)')
axis([0.5,1.5,0E-15,1.5E-15])
legend('Speed-Power')
xlabel('Vdd (V)')
ylabel('Speed-Power (J)')
2) (5 pts.) You are given this combinational logic network with gate delays as shown:
What delay value for gate A puts it on the critical delay path?
(a) the maximum delay including the gate A in the path can be written as
8 ps  delay A  7 ps  delay A  15 ps
where the delay for gate A has been assumed as a variable.
(b) the maximum delay of the circuit can be calculated as
7 ps  8 ps  5 ps  6 ps  26 ps
To put gate A on the same critical delay path as the circuit,
delayA  15 ps  26 ps  delay A  11 ps
Therefore, the minimum value to put gate A on the critical delay path is 11ps.
3) (5 pts.) List all the differences between a wire and a transmission line.
In the context of our class, wire is a short cable compared to a transmission line which is
a very long cable. Whereas a wire can be seen as only two lumped elements (resistance
and capacitance) which depend on the material properties and its geometry, a transmission
line requires three lumpled elements (resistors, capacitors and inductors) distributed along
the actual distance that a signal traversing the trasmission line needs to travel. As
transmission lines have inductances, additional transient effects are introduced during
signal propagation including effects on neighboring transmission lines and wires.
4) (15 pts.) The Elmore delay equation for interconnect (long wires) given in lecture is the
following: 𝛿𝐸 = ∑1≤𝑖≤𝑛 𝑐𝑖 ∑1≤𝑗≤𝑖 𝑟𝑗 . For the following interconnect, give the final delay
equation using only addition and multiplication but no parentheses, e.g. 𝛿𝐸 = 𝑐1 𝑟1 + 𝑐1 𝑟2 ,
is an answer in acceptable format but 𝛿𝐸 = 𝑐1 (𝑟1 + 𝑟2 ) uses parentheses and so will
receive zero credit if given as an answer.
As indicated in the formula, we need to define the value of n for the specific interconnect. For
this case, n = 4. Therefore, we can rewrite the Elmore delay equation as
𝑛=4
𝑖
𝛿𝐸 = ∑ 𝑐𝑖 (∑ 𝑟𝑗 ) = 𝑐1 (𝑟1 ) + 𝑐2 (𝑟1 + 𝑟2 ) + 𝑐3 (𝑟1 + 𝑟2 + 𝑟3 ) + 𝑐4 (𝑟1 + 𝑟2 + 𝑟3 + 𝑟4 )
𝑖=1
𝑗=1
𝛿𝐸 = 𝑐1 𝑟1 + 𝑐2 𝑟1 + 𝑐2 𝑟2 + 𝑐3 𝑟1 + 𝑐3 𝑟2 + 𝑐3 𝑟3 + 𝑐4 𝑟1 + 𝑐4 𝑟2 + 𝑐4 𝑟3 + 𝑐4 𝑟4
Conceptual Hint: For this circuit, each capacitor is charged by the preceding resistances.
Incoming signal is transmitted through resistance 𝑟1 along the transmission line and the output
signal is taken in the point between resistance 𝑟4 and capacitor 𝑐4 .
5) (10 pts.) Assuming each gate’s output has a delay of one, finish the timing diagram:
Remember that
out1 = i1
XOR i2
out2 = out1 NOR i3
Table 5.1 and Table 5.2 presents the truth table for the gates in the circuit.
Table 5.1. Truth table for XOR.
i1
i2
0
0
1
1
0
1
0
1
out1=
i1 XOR i2
0
1
1
0
Table 5.2. Truth table for NOR.
out1
i3
0
0
1
1
0
1
0
1
out2=
i1 NOR i2
1
0
0
0
Figure 5.1. Complete timming diagram.
Observe that you need to wait for two time units after the last transition of any inputs to make
sure that out2 (the critical path of the whole system) calculates the correct ouput. If we read
the outputs before these two units of time, we might capture incorrect values!
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