PCI Local Bus
Specification
Revision 2.2
December 18, 1998
Revision 2.2
REVISION
REVISION HISTORY
DATE
1.0
Original issue
6/22/92
2.0
Incorporated connector and expansion board specification
4/30/93
2.1
Incorporated clarifications and added 66 MHz chapter
6/1/95
2.2
Incorporated ECNs and improved readability
12/18/98
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Copyright © 1992, 1993, 1995, 1998 PCI Special Interest Group
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Revision 2.2
Contents
Chapter 1 Introduction
1.1. Specification Contents............................................................................................................ 1
1.2. Motivation .............................................................................................................................. 1
1.3. PCI Local Bus Applications ................................................................................................... 2
1.4. PCI Local Bus Overview........................................................................................................ 3
1.5. PCI Local Bus Features and Benefits ..................................................................................... 4
1.6. Administration ........................................................................................................................ 6
Chapter 2 Signal Definition
2.1. Signal Type Definition ........................................................................................................... 8
2.2. Pin Functional Groups ............................................................................................................ 8
2.2.1. System Pins ..................................................................................................................... 8
2.2.2. Address and Data Pins..................................................................................................... 9
2.2.3. Interface Control Pins.................................................................................................... 10
2.2.4. Arbitration Pins (Bus Masters Only) ............................................................................. 11
2.2.5. Error Reporting Pins...................................................................................................... 12
2.2.6. Interrupt Pins (Optional) ............................................................................................... 13
2.2.7. Additional Signals ......................................................................................................... 15
2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17
2.2.9. JTAG/Boundary Scan Pins (Optional) .......................................................................... 18
2.3. Sideband Signals .................................................................................................................. 19
2.4. Central Resource Functions.................................................................................................. 19
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Chapter 3 Bus Operation
3.1. Bus Commands..................................................................................................................... 21
3.1.1. Command Definition ..................................................................................................... 21
3.1.2. Command Usage Rules ................................................................................................. 23
3.2. PCI Protocol Fundamentals .................................................................................................. 26
3.2.1. Basic Transfer Control .................................................................................................. 26
3.2.2. Addressing ..................................................................................................................... 27
3.2.2.1. I/O Space Decoding................................................................................................ 28
3.2.2.2. Memory Space Decoding ....................................................................................... 28
3.2.2.3. Configuration Space Decoding............................................................................... 30
3.2.3. Byte Lane and Byte Enable Usage ................................................................................ 38
3.2.4. Bus Driving and Turnaround......................................................................................... 39
3.2.5. Transaction Ordering and Posting ................................................................................. 40
3.2.5.1. Transaction Ordering and Posting for Simple Devices .......................................... 41
3.2.5.2. Transaction Ordering and Posting for Bridges ....................................................... 42
3.2.6. Combining, Merging, and Collapsing ........................................................................... 44
3.3. Bus Transactions .................................................................................................................. 46
3.3.1. Read Transaction ........................................................................................................... 47
3.3.2. Write Transaction .......................................................................................................... 48
3.3.3. Transaction Termination ............................................................................................... 49
3.3.3.1. Master Initiated Termination .................................................................................. 49
3.3.3.2. Target Initiated Termination .................................................................................. 52
3.3.3.3. Delayed Transactions ............................................................................................. 61
3.4. Arbitration ............................................................................................................................ 68
3.4.1. Arbitration Signaling Protocol ...................................................................................... 70
3.4.2. Fast Back-to-Back Transactions.................................................................................... 72
3.4.3. Arbitration Parking ........................................................................................................ 74
3.5. Latency ................................................................................................................................. 75
3.5.1. Target Latency............................................................................................................... 75
3.5.1.1. Target Initial Latency ............................................................................................. 75
3.5.1.2. Target Subsequent Latency .................................................................................... 77
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3.5.2. Master Data Latency...................................................................................................... 78
3.5.3. Memory Write Maximum Completion Time Limit ...................................................... 78
3.5.4. Arbitration Latency ....................................................................................................... 79
3.5.4.1. Bandwidth and Latency Considerations ................................................................. 80
3.5.4.2. Determining Arbitration Latency ........................................................................... 82
3.5.4.3. Determining Buffer Requirements ......................................................................... 87
3.6. Other Bus Operations ........................................................................................................... 88
3.6.1. Device Selection ............................................................................................................ 88
3.6.2. Special Cycle ................................................................................................................. 90
3.6.3. Address/Data Stepping .................................................................................................. 91
3.6.4. Interrupt Acknowledge .................................................................................................. 93
3.7. Error Functions ..................................................................................................................... 93
3.7.1. Parity Generation........................................................................................................... 94
3.7.2. Parity Checking ............................................................................................................. 95
3.7.3. Address Parity Errors .................................................................................................... 95
3.7.4. Error Reporting.............................................................................................................. 95
3.7.4.1. Data Parity Error Signaling on PERR# .................................................................. 96
3.7.4.2. Other Error Signaling on SERR# ........................................................................... 97
3.7.4.3. Master Data Parity Error Status Bit........................................................................ 98
3.7.4.4. Detected Parity Error Status Bit ............................................................................. 98
3.7.5. Delayed Transactions and Data Parity Errors ............................................................... 98
3.7.6. Error Recovery .............................................................................................................. 99
3.8. 64-Bit Bus Extension.......................................................................................................... 100
3.8.1. Determining Bus Width During System Initialization ................................................ 104
3.9. 64-bit Addressing ............................................................................................................... 105
3.10. Special Design Considerations ......................................................................................... 108
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Chapter 4 Electrical Specification
4.1. Overview ............................................................................................................................ 113
4.1.1. 5V to 3.3V Transition Road Map ................................................................................ 113
4.1.2. Dynamic vs. Static Drive Specification ...................................................................... 115
4.2. Component Specification ................................................................................................... 115
4.2.1. 5V Signaling Environment .......................................................................................... 117
4.2.1.1. DC Specifications ................................................................................................. 117
4.2.1.2. AC Specifications ................................................................................................. 118
4.2.1.3. Maximum AC Ratings and Device Protection ..................................................... 120
4.2.2. 3.3V Signaling Environment ....................................................................................... 122
4.2.2.1. DC Specifications ................................................................................................. 122
4.2.2.2. AC Specifications ................................................................................................. 123
4.2.2.3. Maximum AC Ratings and Device Protection ..................................................... 125
4.2.3. Timing Specification ................................................................................................... 126
4.2.3.1. Clock Specification .............................................................................................. 126
4.2.3.2. Timing Parameters................................................................................................ 128
4.2.3.3. Measurement and Test Conditions ....................................................................... 129
4.2.4. Indeterminate Inputs and Metastability ....................................................................... 130
4.2.5. Vendor Provided Specification.................................................................................... 131
4.2.6. Pinout Recommendation ............................................................................................. 131
4.3. System (Motherboard) Specification.................................................................................. 132
4.3.1. Clock Skew.................................................................................................................. 132
4.3.2. Reset ............................................................................................................................ 133
4.3.3. Pull-ups........................................................................................................................ 136
4.3.4. Power ........................................................................................................................... 137
4.3.4.1. Power Requirements............................................................................................. 137
4.3.4.2. Sequencing............................................................................................................ 137
4.3.4.3. Decoupling............................................................................................................ 138
4.3.5. System Timing Budget ................................................................................................ 138
4.3.6. Physical Requirements ................................................................................................ 141
4.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards ............... 141
4.3.6.2. Motherboard Impedance....................................................................................... 141
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4.3.7. Connector Pin Assignments ........................................................................................ 142
4.4. Expansion Board Specification .......................................................................................... 146
4.4.1. Board Pin Assignment ................................................................................................. 146
4.4.2. Power Requirements.................................................................................................... 150
4.4.2.1. Decoupling............................................................................................................ 150
4.4.2.2. Power Consumption ............................................................................................. 150
4.4.3. Physical Requirements ................................................................................................ 151
4.4.3.1. Trace Length Limits ............................................................................................. 151
4.4.3.2. Routing Recommendations for Four-Layer Expansion Boards ........................... 152
4.4.3.3. Impedance............................................................................................................. 152
4.4.3.4. Signal Loading...................................................................................................... 152
Chapter 5 Mechanical Specification
5.1. Overview ............................................................................................................................ 153
5.2. Expansion Card Physical Dimensions and Tolerances ...................................................... 154
5.2.1. Connector Physical Description .................................................................................. 168
5.2.1.1. Connector Physical Requirements........................................................................ 176
5.2.1.2. Connector Performance Specification .................................................................. 177
5.2.2. Planar Implementation ................................................................................................ 178
Chapter 6 Configuration Space
6.1. Configuration Space Organization ..................................................................................... 190
6.2. Configuration Space Functions .......................................................................................... 192
6.2.1. Device Identification ................................................................................................... 192
6.2.2. Device Control............................................................................................................. 193
6.2.3. Device Status ............................................................................................................... 196
6.2.4. Miscellaneous Registers .............................................................................................. 198
6.2.5. Base Addresses ............................................................................................................ 201
6.2.5.1. Address Maps ....................................................................................................... 201
6.2.5.2. Expansion ROM Base Address Register .............................................................. 204
6.3. PCI Expansion ROMs ........................................................................................................ 205
6.3.1. PCI Expansion ROM Contents.................................................................................... 206
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6.3.1.1. PCI Expansion ROM Header Format ................................................................... 206
6.3.1.2. PCI Data Structure Format ................................................................................... 207
6.3.2. Power-on Self Test (POST) Code ............................................................................... 209
6.3.3. PC-compatible Expansion ROMs................................................................................ 209
6.3.3.1. ROM Header Extensions ...................................................................................... 209
6.4. Vital Product Data ............................................................................................................... 212
6.5. Device Drivers.................................................................................................................... 212
6.6. System Reset ...................................................................................................................... 213
6.7. Capabilities List.................................................................................................................. 213
6.8. Message Signaled Interrupts .............................................................................................. 214
6.8.1. Message Capability Structure....................................................................................... 214
6.8.1.1. Capability ID ........................................................................................................ 215
6.8.1.2. Next Pointer .......................................................................................................... 215
6.8.1.3. Message Control ................................................................................................... 215
6.8.1.4. Message Address .................................................................................................. 217
6.8.1.5. Message Upper Address (Optional) ..................................................................... 217
6.8.1.6. Message Data........................................................................................................ 218
6.8.2. MSI Operation .............................................................................................................. 218
6.8.2.1. MSI Transaction Termination .............................................................................. 220
6.8.2.2. MSI Transaction Reception and Ordering Requirements .................................... 220
Chapter 7 66 Mhz PCI Specification
7.1. Introduction ........................................................................................................................ 221
7.2. Scope .................................................................................................................................. 221
7.3. Device Implementation Considerations ............................................................................. 222
7.3.1. Configuration Space .................................................................................................... 222
7.4. Agent Architecture ............................................................................................................. 222
7.5. Protocol............................................................................................................................... 222
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition .............................................................. 222
7.5.2. Latency ........................................................................................................................ 223
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7.6. Electrical Specification....................................................................................................... 223
7.6.1. Overview ..................................................................................................................... 223
7.6.2. Transition Roadmap to 66 MHz PCI........................................................................... 224
7.6.3. Signaling Environment ................................................................................................ 224
7.6.3.1. DC Specifications ................................................................................................. 225
7.6.3.2. AC Specifications ................................................................................................. 225
7.6.3.3. Maximum AC Ratings and Device Protection ..................................................... 226
7.6.4. Timing Specification ................................................................................................... 226
7.6.4.1. Clock Specification .............................................................................................. 226
7.6.4.2. Timing Parameters................................................................................................ 228
7.6.4.3. Measurement and Test Conditions ....................................................................... 229
7.6.5. Vendor Provided Specification ................................................................................... 231
7.6.6. Recommendations ....................................................................................................... 231
7.6.6.1. Pinout Recommendations ..................................................................................... 231
7.6.6.2. Clocking Recommendations................................................................................. 231
7.7. System (Planar) Specification ............................................................................................ 232
7.7.1. Clock Uncertainty........................................................................................................ 232
7.7.2. Reset ............................................................................................................................ 233
7.7.3. Pullups ......................................................................................................................... 233
7.7.4. Power ........................................................................................................................... 233
7.7.4.1. Power Requirements............................................................................................. 233
7.7.4.2. Sequencing............................................................................................................ 233
7.7.4.3. Decoupling............................................................................................................ 233
7.7.5. System Timing Budget ................................................................................................ 233
7.7.6. Physical Requirements ................................................................................................ 236
7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards .......................... 236
7.7.6.2. Planar Impedance ................................................................................................. 236
7.7.7. Connector Pin Assignments ........................................................................................ 236
7.8. Expansion Board Specifications......................................................................................... 237
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Appendix A Special Cycle Messages .......................................239
Appendix B State Machines ......................................................241
Appendix C Operating Rules.....................................................251
Appendix D Class Codes...........................................................257
Appendix E System Transaction Ordering...............................267
Appendix F Exclusive Accesses...............................................279
Appendix G I/O Space Address Decoding for
Legacy Devices ....................................................285
Appendix H Capability IDs..........................................................287
Appendix I Vital Product Data ...................................................289
Glossary .......................................................................................297
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Figures
Figure 1-1: PCI Local Bus Applications .................................................................................... 2
Figure 1-2: PCI System Block Diagram..................................................................................... 3
Figure 2-1: PCI Pin List ............................................................................................................. 7
Figure 3-1: Address Phase Formats of Configuration Transactions ........................................ 31
Figure 3-2: Layout of CONFIG_ADDRESS Register ............................................................. 32
Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions
Address Phase....................................................................................................... 33
Figure 3-4: Configuration Read ............................................................................................... 38
Figure 3-5: Basic Read Operation ............................................................................................ 47
Figure 3-6: Basic Write Operation ........................................................................................... 48
Figure 3-7: Master Initiated Termination ................................................................................. 50
Figure 3-8: Master-Abort Termination .................................................................................... 51
Figure 3-9: Retry ...................................................................................................................... 55
Figure 3-10: Disconnect With Data.......................................................................................... 56
Figure 3-11: Master Completion Termination ......................................................................... 57
Figure 3-12: Disconnect-1 Without Data Termination ............................................................ 58
Figure 3-13: Disconnect-2 Without Data Termination ............................................................ 58
Figure 3-14: Target-Abort ........................................................................................................ 59
Figure 3-15: Basic Arbitration ................................................................................................. 70
Figure 3-16: Arbitration for Back-to-Back Access .................................................................. 74
Figure 3-17: DEVSEL# Assertion........................................................................................... 89
Figure 3-18: Address Stepping ................................................................................................. 92
Figure 3-19: Interrupt Acknowledge Cycle.............................................................................. 93
Figure 3-20: Parity Operation................................................................................................... 94
Figure 3-21: 64-bit Read Request With 64-bit Transfer ........................................................ 103
Figure 3-22: 64-bit Write Request With 32-bit Transfer ....................................................... 104
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Figure 3-23. 64-Bit Dual Address Read Cycle....................................................................... 107
Figure 4-1: PCI Board Connectors ......................................................................................... 114
Figure 4-2: V/I Curves for 5V Signaling................................................................................ 120
Figure 4-3: Maximum AC Waveforms for 5V Signaling ...................................................... 121
Figure 4-4: V/I Curves for 3.3V Signaling............................................................................. 124
Figure 4-5: Maximum AC Waveforms for 3.3V Signaling ................................................... 125
Figure 4-6: Clock Waveforms ................................................................................................ 126
Figure 4-7: Output Timing Measurement Conditions ............................................................ 129
Figure 4-8: Input Timing Measurement Conditions .............................................................. 129
Figure 4-9: Suggested Pinout for PQFP PCI Component ...................................................... 132
Figure 4-10: Clock Skew Diagram......................................................................................... 133
Figure 4-11: Reset Timing...................................................................................................... 135
Figure 4-12: Measurement of T prop, 5 Volt Signaling .......................................................... 140
Figure 5-1: PCI Raw Card (5V) ............................................................................................. 155
Figure 5-2: PCI Raw Card (3.3V and Universal) ................................................................... 155
Figure 5-3: PCI Raw Variable Height Short Card (5V, 32-bit) ............................................. 156
Figure 5-4: PCI Raw Variable Height Short Card (3.3V, 32-bit) .......................................... 156
Figure 5-5: PCI Raw Variable Height Short Card (5V, 64-bit) ............................................. 157
Figure 5-6: PCI Raw Variable Height Short Card (3.3V, 64-bit) .......................................... 158
Figure 5-7: PCI Card Edge Connector Bevel ......................................................................... 159
Figure 5-8: ISA Assembly (5V) ............................................................................................. 160
Figure 5-9: ISA Assembly (3.3V and Universal) ................................................................... 160
Figure 5-10: MC Assembly (5V) ........................................................................................... 161
Figure 5-11: MC Assembly (3.3V) ........................................................................................ 161
Figure 5-12: ISA Bracket ....................................................................................................... 162
Figure 5-13: ISA Retainer ...................................................................................................... 163
Figure 5-14: I/O Window Height ........................................................................................... 164
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Figure 5-15: Adapter Installation With Large I/O Connector ................................................ 165
Figure 5-16: MC Bracket Brace ............................................................................................. 166
Figure 5-17: MC Bracket........................................................................................................ 167
Figure 5-18: MC Bracket Details ........................................................................................... 168
Figure 5-19: 32-bit Connector ................................................................................................ 169
Figure 5-20: 5V/32-bit Connector Layout Recommendation ................................................ 169
Figure 5-21: 3.3V/32-bit Connector Layout Recommendation ............................................. 170
Figure 5-22: 5V/64-bit Connector .......................................................................................... 170
Figure 5-23: 5V/64-bit Connector Layout Recommendation ................................................ 170
Figure 5-24: 3.3V/64-bit Connector ....................................................................................... 171
Figure 5-25: 3.3V/64-bit Connector Layout Recommendation ............................................. 171
Figure 5-26: 5V/32-bit Card Edge Connector Dimensions and Tolerances .......................... 172
Figure 5-27: 5V/64-bit Card Edge Connector Dimensions and Tolerances .......................... 172
Figure 5-28: 3.3V/32-bit Card Edge Connector Dimensions and Tolerances ....................... 173
Figure 5-29: 3.3V/64-bit Card Edge Connector Dimensions and Tolerances ....................... 173
Figure 5-30: Universal 32-bit Card Edge Connector Dimensions and Tolerances ................ 174
Figure 5-31: Universal 64-bit Card Edge Connector Dimensions and Tolerances ................ 175
Figure 5-32: PCI Card Edge Connector Contacts .................................................................. 176
Figure 5-33: PCI Connector Location on Planar Relative to Datum
on the ISA Connector ....................................................................................... 179
Figure 5-34: PCI Connector Location on Planar Relative to Datum
on the EISA Connector..................................................................................... 179
Figure 5-35: PCI Connector Location on Planar Relative to Datum
on the MC Connector ....................................................................................... 180
Figure 5-36: 32-bit PCI Riser Connector ............................................................................... 181
Figure 5-37: 32-bit/5V Riser Connector Footprint ................................................................ 182
Figure 5-38: 32-bit/3.3V Riser Connector Footprint ............................................................. 183
Figure 5-39: 64-bit/5V Riser Connector ............................................................................... 184
Figure 5-40: 64-bit/5V Riser Connector Footprint ................................................................ 185
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Revision 2.2
Figure 5-41: 64-bit/3.3V Riser Connector ............................................................................ 186
Figure 5-42: 64-bit/3.3V Riser Connector Footprint.............................................................. 187
Figure 6-1: Type 00h Configuration Space Header ............................................................... 191
Figure 6-2: Command Register Layout .................................................................................. 193
Figure 6-3: Status Register Layout......................................................................................... 196
Figure 6-4: BIST Register Layout .......................................................................................... 199
Figure 6-5: Base Address Register for Memory .................................................................... 202
Figure 6-6: Base Address Register for I/O ............................................................................. 202
Figure 6-7: Expansion ROM Base Address Register Layout................................................. 205
Figure 6-8: PCI Expansion ROM Structure ........................................................................... 206
Figure 6-9: Typical Image Layout.......................................................................................... 211
Figure 6-10: Example Capabilities List.................................................................................. 213
Figure 6-11: Message Signaled Interrupt Capability Structure .............................................. 214
Figure 7-1: 33 MHz PCI vs. 66 MHz PCI Timing ................................................................. 224
Figure 7-2: 3.3V Clock Waveform......................................................................................... 226
Figure 7-3: Output Timing Measurement Conditions ............................................................ 229
Figure 7-4: Input Timing Measurement Conditions .............................................................. 229
Figure 7-5: Tval(max) Rising Edge........................................................................................ 230
Figure 7-6: Tval(max) Falling Edge....................................................................................... 230
Figure 7-7: Tval (min) and Slew Rate.................................................................................... 231
Figure 7-8: Recommended Clock Routing............................................................................. 232
Figure 7-9: Clock Skew Diagram........................................................................................... 233
Figure 7-10: Measurement of T prop ...................................................................................... 235
Figure D-1: Programming Interface Byte Layout for IDE Controller Class Code ................ 258
Figure E-1: Example Producer - Consumer Model ................................................................ 269
Figure E-2: Example System with PCI-to-PCI Bridges ......................................................... 276
Figure F-1: Starting an Exclusive Access .............................................................................. 282
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Revision 2.2
Figure F-2: Continuing an Exclusive Access ......................................................................... 283
Figure F-3: Accessing a Locked Agent .................................................................................. 284
Figure I-1: VPD Capability Structure .................................................................................... 289
Figure I-2: Small Resource Data Type Tag Bit Definitions................................................... 290
Figure I-3: Large Resource Data Type Tag Bit Definitions................................................... 291
Figure I-4: Resource Data Type Flags for a Typical VPD ..................................................... 291
Figure I-5: VPD Format ......................................................................................................... 292
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Preface
Specification Supersedes Earlier Documents
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Incorporation of Engineering Change Requests (ECRs)
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ECR
Description
New Capabilities
Changes to configuration structure to define additional
capabilities of a PCI function
Sub ID
Subsystem vendor configuration space changed from optional to
required for most classes of devices
PME#
Describes wake-up function and assigns (previously reserved) pin
on PCI bus
MECH ECN# 1
Bracket mounting for EMI reduction
MECH ECN# 2
Increase size of I/O window to enable new connectors
MECH ECN# 3
I/O connector volume to enable add-in card insertion
MECH ECN# 4
Riser connector-add-in card interface
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ECR
xviii
Description
MECH ECN# 5
Tighten critical tolerance to improve add-in card seating
MECH ECN# 6
Mechanical errata (wrong datum ref), components free areas
Posted Memory
Writes
Clarified requirements for posted memory writes to prevent
situations which may lead to a deadlock
Tprop
Clarifies measurement and determination of Tprop times for
33/66 MHz
RST# TIMING
New timing requirements between RST# and the first transaction
on the bus and the first access to a device
VPD (Revised)
Provides alternate access method to vital product data
3.3 V Aux
Specifies a standard source of power for power management
wake event logic
Max Retry Time
Devices cannot Retry a memory write request for longer than
10 µs
Msg Interrupt
Method by which an I/O controller can deliver message based
interrupt
Spread Spectrum
Clocking
Adds spread spectrum clocking (SSC) to the specification
Revision 2.2
Document Conventions
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asserted, deasserted
The terms asserted and deasserted refer to the
globally visible state of the signal on the clock edge,
not to signal transitions.
edge, clock edge
The terms edge and clock edge refer to the rising edge
of the clock. On the rising edge of the clock is the
only time signals have any significance on the PCI
bus.
#
A # symbol at the end of a signal name indicates that
the signal’s asserted state occurs when it is at a low
voltage. The absence of a # symbol indicates that the
signal is asserted at a high voltage.
reserved
The contents or undefined states or information are
not defined at this time. Using any reserved area in
the PCI specification is not permitted. All areas of
the PCI specification can only be changed according
to the by-laws of the PCI Special Interest Group. Any
use of the reserved areas of the PCI specification will
result in a product that is not PCI-compliant. The
functionality of any such product cannot be
guaranteed in this or any future revision of the PCI
specification.
signal names
Signal names are indicated with this bold font.
signal range
A signal name followed by a range enclosed in
brackets, for example AD[31::00], represents a range
of logically related signals. The first number in the
range indicates the most significant bit (msb) and the
last number indicates the least significant bit (lsb).
implementation notes
Implementation notes are enclosed in a box. They are
not part of the PCI specification and are included for
clarification and illustration only.
xix
Revision 2.2
xx
Revision 2.2
Chapter 1
Introduction
1.1. Specification Contents
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1.2. Motivation
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1
Revision 2.2
1.3. PCI Local Bus Applications
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2
Revision 2.2
1.4. PCI Local Bus Overview
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3
Revision 2.2
1.5. PCI Local Bus Features and Benefits
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•
Transparent upgrade from 32-bit data path at 33 MHz
(132 MB/s peak) to 64-bit data path at 33 MHz
(264 MB/s peak) and from 32-bit data path at 66 MHz
(264 MB/s peak) to 64-bit data path at 66 MHz
(528 MB/s peak).
•
Variable length linear and cacheline wrap mode bursting
for both read and writes improves write dependent
graphics performance.
•
Low latency random accesses (60-ns write access latency
for 33 MHz PCI or 30-ns for 66 MHz PCI to slave
registers from master parked on bus).
•
Capable of full concurrency with processor/memory
subsystem.
•
Synchronous bus with operation up to 33 MHz or 66 MHz.
•
Hidden (overlapped) central arbitration.
•
Optimized for direct silicon (component) interconnection;
i.e., no glue logic. Electrical/driver (i.e., total load) and
frequency specifications are met with standard ASIC
technologies and other typical processes.
•
Multiplexed architecture reduces pin count (47 signals for
target; 49 for master) and package size of PCI components
or provides for additional functions to be built into a
particular package size.
•
Single PCI add-in card works in ISA-, EISA-, or
MC-based systems (with minimal change to existing
chassis designs), reducing inventory cost and end user
confusion.
Ease of Use
•
Enables full auto configuration support of PCI Local Bus
add-in boards and components. PCI devices contain
registers with the device information required for
configuration.
Longevity
•
Processor independent. Supports multiple families of
processors as well as future generations of processors (by
bridges or by direct integration).
•
Support for 64-bit addressing.
•
Both 5-volt and 3.3-volt signaling environments are
specified. Voltage migration path enables smooth industry
transition from 5 volts to 3.3 volts.
High Performance
Low Cost
4
Revision 2.2
•
Small form factor add-in boards.
•
Present signals allow power supplies to be optimized for
the expected system usage by monitoring add-in boards
that could surpass the maximum power budgeted by the
system.
•
Over 2000 hours of electrical SPICE simulation with
hardware model validation.
•
Forward and backward compatibility of 32-bit and 64-bit
add-in boards and components.
•
Forward and backward compatibility with 33 MHz and
66 MHz add-in boards and components.
•
Increased reliability and interoperability of add-in cards by
comprehending the loading and frequency requirements of
the local bus at the component level, eliminating buffers
and glue logic.
•
MC-style expansion connectors.
•
Full multi-master capability allowing any PCI master peerto-peer access to any PCI master/target.
•
A shared slot accommodates either a standard ISA, EISA,
or MC board or a PCI add-in board (refer to Chapter 5,
"Mechanical Specification" for connector layout details).
Data Integrity
•
Provides parity on both data and address and allows
implementation of robust client platforms.
Software
Compatibility
•
PCI components can be fully compatible with existing
driver and applications software. Device drivers can be
portable across various classes of platforms.
Interoperability/
Reliability
Flexibility
5
Revision 2.2
1.6. Administration
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6
Revision 2.2
Chapter 2
Signal Definition
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Optional Pins
Required Pins
Address
& Data
Interface
Control
AD[31::00]
AD[63::32]
C/BE[3::0]#
C/BE[7::4]#
PAR
PAR64
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
Error
Reporting
PERR#
SERR#
Arbitration
REQ#
GNT#
System
CLK
RST#
(masters only)
PCI
COMPLIANT
DEVICE
64-Bit
Extension
REQ64#
ACK64#
LOCK#
INTA#
INTB#
INTC#
INTD#
TDI
TDO
TCK
TMS
TRST#
Interface
Control
Interrupts
JTAG
(IEEE 1149.1)
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1
The minimum number of pins for a planar-only device is 45 for a target-only and 47 for a master (PERR#
and SERR# are optional for planar-only applications). Systems must support all signals defined for the
connector. This includes individual REQ# and GNT# signals for each connector. The PRSNT[1::2]#
pins are not device signals and, therefore, are not included in Figure 2-1, but are required to be connected on
add-in cards.
7
Revision 2.2
2.1. Signal Type Definition
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in
Input is a standard input-only signal.
out
Totem Pole Output is a standard active driver.
t/s
Tri-State is a bi-directional, tri-state input/output pin.
s/t/s
Sustained Tri-State is an active low tri-state signal owned and driven
by one and only one agent at a time. The agent that drives an s/t/s pin
low must drive it high for at least one clock before letting it float. A
new agent cannot start driving a s/t/s signal any sooner than one clock
after the previous owner tri-states it. A pullup is required to sustain
the inactive state until another agent drives it and must be provided by
the central resource.
o/d
Open Drain allows multiple devices to share as a wire-OR. A pull-up
is required to sustain the inactive state until another agent drives it and
must be provided by the central resource.
2.2. Pin Functional Groups
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2.2.1. System Pins
CLK
8
in
Clock provides timing for all transactions on PCI and is an
input to every PCI device. All other PCI signals, except
RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on
the rising edge of CLK and all other timing parameters are
defined with respect to this edge. PCI operates up to 33 MHz
(refer to Chapter 4) or 66 MHz (refer to Chapter 7) and, in
general, the minimum frequency is DC (0 Hz); however,
component-specific permissions are described in Chapter 4
(refer to Section 4.2.3.1.).
Revision 2.2
RST#
in
Reset is used to bring PCI-specific registers, sequencers, and
signals to a consistent state. What effect RST# has on a
device beyond the PCI sequencer is beyond the scope of this
specification, except for reset states of required PCI
configuration registers. A device that can wake the system
while in a powered down bus state has additional
requirements related to RST#. Refer to the PCI Power
Management Interface Specification for details. Anytime
RST# is asserted, all PCI output signals must be driven to
their benign state. In general, this means they must be
asynchronously tri-stated. REQ# and GNT# must both be tristated (they cannot be driven low or high during reset). To
prevent AD, C/BE#, and PAR signals from floating during
reset, the central resource may drive these lines during reset
(bus parking) but only to a logic low level; they may not be
driven high. Refer to Section 3.8.1. for special requirements
for AD[63::32], C/BE[7::4]#, and PAR64 when they are
not connected (as in a 64-bit card installed in a 32-bit
connector).
RST# may be asynchronous to CLK when asserted or
deasserted. Although asynchronous, deassertion is guaranteed
to be a clean, bounce-free edge. Except for configuration
accesses, only devices that are required to boot the system
will respond after reset.
2.2.2. Address and Data Pins
AD[31::00]
t/s
Address and Data are multiplexed on the same PCI pins. A
bus transaction consists of an address 2 phase followed by one
or more data phases. PCI supports both read and write bursts.
The address phase is the first clock cycle in which FRAME#
is asserted. During the address phase, AD[31::00] contain a
physical address (32 bits). For I/O, this is a byte address; for
configuration and memory, it is a DWORD address. During
data phases, AD[07::00] contain the least significant byte
(lsb) and AD[31::24] contain the most significant byte (msb).
Write data is stable and valid when IRDY# is asserted; read
data is stable and valid when TRDY# is asserted. Data is
transferred during those clocks where both IRDY# and
TRDY# are asserted.
2
The DAC uses two address phases to transfer a 64-bit address.
9
Revision 2.2
C/BE[3::0]#
t/s
Bus Command and Byte Enables are multiplexed on the same
PCI pins. During the address phase of a transaction,
C/BE[3::0]# define the bus command (refer to Section 3.1.
for bus command definitions). During the data phase,
C/BE[3::0]# are used as Byte Enables. The Byte Enables are
valid for the entire data phase and determine which byte lanes
carry meaningful data. C/BE[0]# applies to byte 0 (lsb) and
C/BE[3]# applies to byte 3 (msb).
PAR
t/s
Parity is even3 parity across AD[31::00] and C/BE[3::0]#.
Parity generation is required by all PCI agents. PAR is stable
and valid one clock after each address phase. For data phases,
PAR is stable and valid one clock after either IRDY# is
asserted on a write transaction or TRDY# is asserted on a read
transaction. Once PAR is valid, it remains valid until one
clock after the completion of the current data phase. (PAR
has the same timing as AD[31::00], but it is delayed by one
clock.) The master drives PAR for address and write data
phases; the target drives PAR for read data phases.
2.2.3. Interface Control Pins
3
FRAME#
s/t/s
Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME# is asserted to
indicate a bus transaction is beginning. While FRAME# is
asserted, data transfers continue. When FRAME# is
deasserted, the transaction is in the final data phase or has
completed.
IRDY#
s/t/s
Initiator Ready indicates the initiating agent’s (bus master’s)
ability to complete the current data phase of the transaction.
IRDY# is used in conjunction with TRDY#. A data phase is
completed on any clock both IRDY# and TRDY# are
asserted. During a write, IRDY# indicates that valid data is
present on AD[31::00]. During a read, it indicates the master
is prepared to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together.
TRDY#
s/t/s
Target Ready indicates the target agent’s (selected device’s)
ability to complete the current data phase of the transaction.
TRDY# is used in conjunction with IRDY#. A data phase is
completed on any clock both TRDY# and IRDY# are
asserted. During a read, TRDY# indicates that valid data is
present on AD[31::00]. During a write, it indicates the target
is prepared to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together.
STOP#
s/t/s
Stop indicates the current target is requesting the master to
stop the current transaction.
The number of "1"s on AD[31::00], C/BE[3::0]#, and PAR equals an even number.
10
Revision 2.2
LOCK#
s/t/s
Lock indicates an atomic operation to a bridge that may
require multiple transactions to complete. When LOCK# is
asserted, non-exclusive transactions may proceed to a bridge
that is not currently locked. A grant to start a transaction on
PCI does not guarantee control of LOCK#. Control of
LOCK# is obtained under its own protocol in conjunction
with GNT#. It is possible for different agents to use PCI
while a single master retains ownership of LOCK#. Locked
transactions may be initiated only by host bridges, PCI-to-PCI
bridges, and expansion bus bridges. Refer to Appendix F for
details on the requirements of LOCK#.
IDSEL
in
Initialization Device Select is used as a chip select during
configuration read and write transactions.
DEVSEL#
s/t/s
Device Select, when actively driven, indicates the driving
device has decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether any device
on the bus has been selected.
2.2.4. Arbitration Pins (Bus Masters Only)
REQ#
t/s
Request indicates to the arbiter that this agent desires use of
the bus. This is a point-to-point signal. Every master has its
own REQ# which must be tri-stated while RST# is asserted.
GNT#
t/s
Grant indicates to the agent that access to the bus has been
granted. This is a point-to-point signal. Every master has its
own GNT# which must be ignored while RST# is asserted.
:KLOHRST#LVDVVHUWHGWKHDUELWHUPXVWLJQRUHDOOREQ#OLQHVVLQFHWKH\DUHWULVWDWHG
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LVGHDVVHUWHG$PDVWHUPXVWLJQRUHLWVGNT#ZKLOHRST#LVDVVHUWHGREQ#DQG
GNT#DUHWULVWDWHVLJQDOVGXHWRSRZHUVHTXHQFLQJUHTXLUHPHQWVLQWKHFDVHZKHUHWKH
EXVDUELWHULVSRZHUHGE\DGLIIHUHQWVXSSO\YROWDJHWKDQWKHEXVPDVWHUGHYLFH
4
REQ# is an input to the arbiter, and GNT# is an output.
11
Revision 2.2
2.2.5. Error Reporting Pins
7KHHUURUUHSRUWLQJSLQVDUHUHTXLUHGE\DOOGHYLFHVDQGPD\EHDVVHUWHGZKHQHQDEOHG
5
PERR#
s/t/s
Parity Error is only for the reporting of data parity errors
during all PCI transactions except a Special Cycle. The
PERR# pin is sustained tri-state and must be driven active
by the agent receiving data (when enabled) two clocks
following the data when a data parity error is detected. The
minimum duration of PERR# is one clock for each data
phase that a data parity error is detected. (If sequential data
phases each have a data parity error, the PERR# signal will
be asserted for more than a single clock.) PERR# must be
driven high for one clock before being tri-stated as with all
sustained tri-state signals. Refer to Section 3.7.4.1. for more
details.
SERR#
o/d
System Error is for reporting address parity errors, data parity
errors on the Special Cycle command, or any other system
error where the result will be catastrophic. If an agent does
not want a non-maskable interrupt (NMI) to be generated, a
different reporting mechanism is required. SERR# is pure
open drain and is actively driven for a single PCI clock by the
agent reporting the error. The assertion of SERR# is
synchronous to the clock and meets the setup and hold times
of all bused signals. However, the restoring of SERR# to the
deasserted state is accomplished by a weak pullup (same
value as used for s/t/s) which is provided by the central
resource not by the signaling agent. This pullup may take two
to three clock periods to fully restore SERR#. The agent that
reports SERR# to the operating system does so anytime
SERR# is asserted.
Some planar devices are granted exceptions (refer to Section 3.7.2. for details).
12
Revision 2.2
2.2.6. Interrupt Pins (Optional)
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OLQHVKDYHQRPHDQLQJ
INTA#
o/d
Interrupt A is used to request an interrupt.
INTB#
o/d
Interrupt B is used to request an interrupt and only has
meaning on a multi-function device.
INTC#
o/d
Interrupt C is used to request an interrupt and only has
meaning on a multi-function device.
INTD#
o/d
Interrupt D is used to request an interrupt and only has
meaning on a multi-function device.
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7KHV\VWHPGHVLJQHUPXVWLQVXUHWKDWHDFKINTx#VLJQDOIURPHDFKFRQQHFWRULV
FRQQHFWHGWRDQLQSXWRQWKHLQWHUUXSWFRQWUROOHU7KLVPHDQVWKHGHYLFHGULYHUPD\QRW
PDNHDQ\DVVXPSWLRQVDERXWLQWHUUXSWVKDULQJ$OO3&,GHYLFHGULYHUVPXVWEHDEOHWR
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PXOWLIXQFWLRQSDFNDJH
6
When several independent functions are integrated into a single device, it will be referred to as a multifunction device. Each function on a multi-function device has its own configuration space.
13
Revision 2.2
Implementation Note: Interrupt Routing
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INTA# RI'HYLFH1XPEHULVFRQQHFWHGWRIRQYRQWKHPRWKHUERDUGINTA#RI
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IROORZLQJHTXDWLRQFDQEHXVHGWRGHWHUPLQHWRZKLFKINTx#VLJQDORQWKHPRWKHUERDUG
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, ,QWHUUXSW1XPEHUINTA# INTB# INTC# DQGINTD# 14
Device Number
on Motherboard
Interrupt Pin on
Device
Interrupt Pin on
Motherboard
0, 4, 8, 12,
16, 20, 24, 28
INTA#
INTB#
INTC#
INTD#
IRQW
IRQX
IRQY
IRQZ
1, 5, 9, 13,
17, 21, 25, 29
INTA#
INTB#
INTC#
INTD#
IRQX
IRQY
IRQZ
IRQW
2, 6, 10, 14,
18, 22, 26, 30
INTA#
INTB#
INTC#
INTD#
IRQY
IRQZ
IRQW
IRQX
3, 7, 11, 15,
19, 23, 27, 31
INTA#
INTB#
INTC#
INTD#
IRQZ
IRQW
IRQX
IRQY
Revision 2.2
2.2.7. Additional Signals
PRSNT[1:2]#
in
The Present signals are not signals for a device, but are
provided by an add-in board. The Present signals indicate to
the motherboard whether an add-in board is physically
present in the slot and, if one is present, the total power
requirements of the board. These signals are required for
add-in boards but are optional for motherboards. Refer to
Section 4.4.1. for more details.
Implementation Note: PRSNT# Pins
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LQGLFDWHWRWKHPRWKHUERDUGWKDWDERDUGLVSK\VLFDOO\LQWKHFRQQHFWRU7KHVLJQDOOHYHO
RIPRSNT1#DQGPRSNT2#LQIRUPWKHPRWKHUERDUGRIWKHSRZHUUHTXLUHPHQWVRIWKH
DGGLQERDUG7KHDGGLQERDUGPD\VLPSO\WLHPRSNT1#DQGRUPRSNT2#WRJURXQG
WRVLJQDOWKHDSSURSULDWHSRZHUUHTXLUHPHQWVRIWKHERDUG5HIHUWR6HFWLRQIRU
GHWDLOV7KHPRWKHUERDUGSURYLGHVSXOOXSVRQWKHVHVLJQDOVWRLQGLFDWHZKHQQRERDUG
LVFXUUHQWO\SUHVHQW
CLKRUN#
in, o/d,
s/t/s
Clock running is an optional signal used as an input for a
device to determine the status of CLK and an open drain
output used by the device to request starting or speeding up
CLK.
CLKRUN# is a sustained tri-state signal used by the
central resource to request permission to stop or slow CLK.
The central resource is responsible for maintaining
CLKRUN# in the asserted state when CLK is running and
deasserts CLKRUN# to request permission to stop or slow
CLK. The central resource must provide the pullup for
CLKRUN#.
Implementation Note: CLKRUN#
CLKRUN#LVDQRSWLRQDOVLJQDOXVHGLQWKH3&,PRELOHHQYLURQPHQWDQGQRWGHILQHGIRU
WKHFRQQHFWRU'HWDLOVRIWKHCLKRUN#SURWRFRODQGRWKHUPRELOHGHVLJQ
FRQVLGHUDWLRQVDUHGLVFXVVHGLQWKH3&,0RELOH'HVLJQ*XLGH
15
Revision 2.2
M66EN
in
The 66MHZ_ENABLE pin indicates to a device whether the
bus segment is operating at 66 or 33 MHz. Refer to
Section 7.5.1. for details of this signal’s operation.
PME#
o/d
The Power Management Event signal is an optional signal
that can be used by a device to request a change in the
device or system power state. The assertion and
deassertion of PME# is asynchronous to CLK. This signal
has additional electrical requirements over and above
standard open drain signals that allow it to be shared
between devices which are powered off and those which
are powered on. In general, this signal is bused between all
PCI connectors in a system, although certain
implementations may choose to pass separate buffered
copies of the signal to the system logic.
Devices must be enabled by software before asserting this
signal. Once asserted, the device must continue to drive
the signal low until software explicitly clears the condition
in the device.
The use of this pin is specified in the PCI Bus Power
Management Interface Specification. The system vendor
must provide a pull-up on this signal, if it allows the signal
to be used. System vendors that do not use this signal are
not required to bus it between connectors or provide pullups on those pins.
3.3Vaux
in
An optional 3.3 volt auxiliary power source delivers power
to the PCI add-in card for generation of power management
events when the main power to the card has been turned off
by software.
The use of this pin is specified in the PCI Bus Power
Management Interface Specification.
A system or add-in card that does not support PCI bus
power management must treat the 3.3Vaux pin as reserved.
Implementation Note: PME# and 3.3Vaux
PME# DQG3.3VauxDUHRSWLRQDOVLJQDOVGHILQHGE\WKH3&,%XV3RZHU0DQDJHPHQW
,QWHUIDFH6SHFLILFDWLRQ'HWDLOVRIWKHVHVLJQDOVFDQEHIRXQGLQWKDWGRFXPHQW
16
Revision 2.2
2.2.8. 64-Bit Bus Extension Pins (Optional)
7KHELWH[WHQVLRQSLQVDUHFROOHFWLYHO\RSWLRQDO7KDWLVLIWKHELWH[WHQVLRQLV
XVHGDOOWKHSLQVLQWKLVVHFWLRQDUHUHTXLUHG
AD[63::32]
t/s
Address and Data are multiplexed on the same pins and
provide 32 additional bits. During an address phase (when
using the DAC command and when REQ64# is asserted), the
upper 32-bits of a 64-bit address are transferred; otherwise,
these bits are reserved7 but are stable and indeterminate.
During a data phase, an additional 32-bits of data are
transferred when a 64-bit transaction has been negotiated by
the assertion of REQ64# and ACK64#.
C/BE[7::4]#
t/s
Bus Command and Byte Enables are multiplexed on the same
pins. During an address phase (when using the DAC
command and when REQ64# is asserted), the actual bus
command is transferred on C/BE[7::4]#; otherwise, these bits
are reserved and indeterminate. During a data phase,
C/BE[7::4]# are Byte Enables indicating which byte lanes
carry meaningful data when a 64-bit transaction has been
negotiated by the assertion of REQ64# and ACK64#.
C/BE[4]# applies to byte 4 and C/BE[7]# applies to byte 7.
REQ64#
s/t/s
Request 64-bit Transfer, when asserted by the current bus
master, indicates it desires to transfer data using 64 bits.
REQ64# also has the same timing as FRAME#. REQ64#
also has meaning at the end of reset as described in Section
3.8.1.
ACK64#
s/t/s
Acknowledge 64-bit Transfer, when actively driven by the
device that has positively decoded its address as the target of
the current access, indicates the target is willing to transfer
data using 64 bits. ACK64# has the same timing as
DEVSEL#.
PAR64
t/s
Parity Upper DWORD is the even8 parity bit that protects
AD[63::32] and C/BE[7::4]#. PAR64 must be valid one
clock after each address phase on any transaction in which
REQ64# is asserted.
PAR64 is stable and valid for 64-bit data phases one clock
after either IRDY# is asserted on a write transaction or
TRDY# is asserted on a read transaction. (PAR64 has the
same timing as AD[63::32] but delayed by one clock.) The
master drives PAR64 for address and write data phases; the
target drives PAR64 for read data phases.
7 Reserved means reserved for future use by the PCI SIG Steering Committee. Reserved bits must not be
used by any device.
8
The number of “1”s on AD[63::32], C/BE[7::4]#, and PAR64 equals an even number.
17
Revision 2.2
2.2.9. JTAG/Boundary Scan Pins (Optional)
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TCK
in
Test Clock is used to clock state information and test data into
and out of the device during operation of the TAP.
TDI
in
Test Data Input is used to serially shift test data and test
instructions into the device during TAP operation.
TDO
out
Test Output is used to serially shift test data and test
instructions out of the device during TAP operation.
TMS
in
Test Mode Select is used to control the state of the TAP
controller in the device.
TRST#
in
Test Reset provides an asynchronous initialization of the TAP
controller. This signal is optional in IEEE Standard 1149.1.
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18
Revision 2.2
2.3. Sideband Signals
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2.4. Central Resource Functions
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19
Revision 2.2
20
Revision 2.2
Chapter 3
Bus Operation
3.1. Bus Commands
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3.1.1. Command Definition
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Command Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
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Revision 2.2
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22
Revision 2.2
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3.1.2. Command Usage Rules
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Revision 2.2
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Revision 2.2
3.2. PCI Protocol Fundamentals
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3.2.1. Basic Transfer Control
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The only exceptions are 567,17$,17%,17& and ,17'which are discussed in
Sections 2.2.1. and 2.2.6.
9
10
3$5 and 3$5 are treated like an $' line delayed by one clock.
11
The notion of qualifying $' and ,'6(/ signals is fully defined in Section 3.6.3.
12
Note: The address phase consists of two clocks when the command is the Dual Address Cycle (DAC).
26
Revision 2.2
2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLOWKH
FXUUHQWGDWDSKDVHFRPSOHWHVUHJDUGOHVVRIWKHVWDWHRITRDY#2QFHDWDUJHWKDV
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PD\QRWWUDQVIHUGHSHQGLQJRQWKHVWDWHRITRDY#
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3.2.2. Addressing
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Implementation Note: Device Address Space
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27
Revision 2.2
3.2.2.1. I/O Space Decoding
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PDVWHUWKDWLQLWLDWHVDQ,2WUDQVDFWLRQLVUHTXLUHGWRHQVXUHWKDWAD[1::0]LQGLFDWHWKH
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3.2.2.2. Memory Space Decoding
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28
Revision 2.2
7DEOHOLVWVWKHEXUVWRUGHULQJUHTXHVWHGE\WKHPDVWHUGXULQJ0HPRU\FRPPDQGVDV
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Burst Order
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Reserved (disconnect after first data phase)13
Cacheline Wrap mode
Reserved (disconnect after first data phase)
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VDPHFDFKHOLQH,WFRQWLQXHVXQWLOWKHUHVWRIWKHOLQHKDVEHHQWUDQVIHUUHG)RUH[DPSOH
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13
This encoded value is reserved and cannot be assigned any “new” meaning for new designs. New
designs (master or targets) cannot use this encoding. Note that in an earlier version of this specification, this
encoding had meaning and there are masters that generate it and some targets may allow the transaction to
continue past the initial data phase.
29
Revision 2.2
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3.2.2.3.1. Configuration Commands (Type 0 and Type 1)
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30
Revision 2.2
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:25'UHJLVWHUVDUHQRWDIIHFWHGEHFDXVHWKHLUWUDQVDFWLRQVZLOOSDVVWKURXJKWKHKRVW
EULGJHXQFKDQJHG
14
In versions 2.0 and 2.1 of this specification, two mechanisms were defined. However, only one
mechanism (Configuration Mechanism #1) was allowed for new designs and the other (Configuration
Mechanism #2) was included for reference.
32
Revision 2.2
:KHQDKRVWEULGJHVHHVDQ,2DFFHVVWKDWIDOOVLQVLGHWKH':25'EHJLQQLQJDW
&21),*B'$7$DGGUHVVLWFKHFNVWKH(QDEOHELWDQGWKH%XV1XPEHULQWKH
&21),*B$''5(66UHJLVWHU,I(QDEOHELWLVVHWDQGWKH%XV1XPEHUPDWFKHVWKH
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WUDQVODWLRQPXVWEHGRQH
7KHUHDUHWZRW\SHVRIWUDQVODWLRQWKDWWDNHSODFH7KHILUVW7\SHLVDWUDQVODWLRQ
ZKHUHWKHGHYLFHEHLQJDGGUHVVHGLVRQWKH3&,EXVFRQQHFWHGWRWKHKRVWEULGJH7KH
VHFRQG7\SHRFFXUVZKHQWKHGHYLFHLVRQDQRWKHUEXVVRPHZKHUHEHKLQGWKLVEULGJH
)RU7\SHWUDQVODWLRQVVHH)LJXUHWKHKRVWEULGJHGRHVDGHFRGHRIWKH'HYLFH
1XPEHUILHOGWRDVVHUWWKHDSSURSULDWHIDSELOLQH DQGSHUIRUPVDFRQILJXUDWLRQ
WUDQVDFWLRQRQWKH3&,EXVZKHUHAD[1::0] %LWVRI&21),*B$''5(66
DUHFRSLHGWRAD[10::8]RQWKH3&,EXVDVDQHQFRGHGYDOXHZKLFKLVXVHGE\
FRPSRQHQWVWKDWFRQWDLQPXOWLSOHIXQFWLRQVAD[7::2]DUHDOVRFRSLHGIURPWKH
&21),*B$''5(66UHJLVWHU)LJXUHVKRZVWKHWUDQVODWLRQIURPWKH
&21),*B$''5(66UHJLVWHUWRADOLQHVRQWKH3&,EXV
Reserved
CONFIG_ADDRESS
PCI AD BUS
Bus
Number
Device
Number
Function
Number
Register
Number
Only One "1"
00
00
)LJXUH+RVW%ULGJH7UDQVODWLRQIRU7\SH&RQILJXUDWLRQ7UDQVDFWLRQV$GGUHVV3KDVH
)RU7\SHWUDQVODWLRQVWKHKRVWEULGJHGLUHFWO\FRSLHVWKHFRQWHQWVRIWKH
&21),*B$''5(66UHJLVWHUH[FOXGLQJELWVDQGRQWRWKH3&,ADOLQHVGXULQJWKH
DGGUHVVSKDVHRIDFRQILJXUDWLRQWUDQVDFWLRQPDNLQJVXUHWKDWAD[1::0]LV
,QERWK7\SHDQG7\SHWUDQVODWLRQVE\WHHQDEOHVIRUWKHGDWDWUDQVIHUVPXVWEH
GLUHFWO\FRSLHGIURPWKHSURFHVVRUEXV
15
If the Device Number field selects an IDSEL line that the bridge does not implement, the bridge must
complete the processor access normally, dropping the data on writes and returning all ones on reads. The
bridge may optionally implement this requirement by performing a Type 0 configuration access with no
IDSEL asserted. This will terminate with Master-Abort which drops write data and returns all ones on
reads.
33
Revision 2.2
Implementation Note: Bus Numbers Registers and Peer Host
Bridges
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LQWRFRQILJXUDWLRQWUDQVDFWLRQVLVVLPSOH,IWKH%XV1XPEHULQWKH&21),*B$''5(66
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)RUKRVWEULGJHVWKDWVXSSRUWSHHUKRVWEXVHVRQHSHHUEULGJHW\SLFDOO\LVGHVLJQDWHGWR
DOZD\VDFNQRZOHGJHDFFHVVHVWRWKH&21),*B$''5(66UHJLVWHU2WKHUSHHUEULGJHV
ZRXOGVQRRSWKHGDWDZULWWHQWRWKLVUHJLVWHU$FFHVVHVWRWKH&21),*B'$7$UHJLVWHU
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WUDQVODWLRQ2QHUHJLVWHU%XV1XPEHUVSHFLILHVWKHEXVQXPEHURIWKH3&,EXVGLUHFWO\
EHKLQGWKHEULGJHDQGWKHRWKHUUHJLVWHU6XERUGLQDWH%XV1XPEHUVSHFLILHVWKHQXPEHU
RIWKHODVWKLHUDUFKLFDOEXVEHKLQGWKHEULGJH$3&,WR3&,EULGJHUHTXLUHVDQ
DGGLWLRQDOUHJLVWHUZKLFKLVLWV3ULPDU\%XV1XPEHU6\VWHPFRQILJXUDWLRQVRIWZDUHLV
UHVSRQVLEOHIRULQLWLDOL]LQJWKHVHUHJLVWHUVWRDSSURSULDWHYDOXHV7KHKRVWEULGJH
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1XPEHUUHJLVWHUDQGOHVVWKDQRUHTXDOWRWKH6XERUGLQDWH%XV1XPEHUUHJLVWHUD7\SH
FRQILJXUDWLRQWUDQVDFWLRQLVXVHG,IWKH%XV1XPEHULQ&21),*B$''5(66LVOHVV
WKDQWKH%XV1XPEHUUHJLVWHURUJUHDWHUWKDQWKH6XERUGLQDWH%XV1XPEHUUHJLVWHUWKH
FRQILJXUDWLRQWUDQVDFWLRQLVDGGUHVVLQJDEXVWKDWLVQRWLPSOHPHQWHGRULVEHKLQGVRPH
RWKHUKRVWEULGJHDQGLVLJQRUHG
3.2.2.3.3. Software Generation of Special Cycles
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EXV7KLVZLOOWHUPLQDWHZLWKD0DVWHU$ERUWDQGWKHSURFHVVRUZLOOKDYHDOO
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34
Revision 2.2
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3.2.2.3.4. Selection of a Device’s Configuration Space
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GRQHH[WHUQDOO\DQGWREHVLJQDOHGWRWKHGHYLFHYLDLQLWLDOL]DWLRQGHYLFHVHOHFWRU
IDSELZKLFKIXQFWLRQVDVDFODVVLFDO³FKLSVHOHFW´VLJQDO(DFKGHYLFHKDVLWVRZQ
IDSELLQSXWH[FHSWIRUKRVWEXVEULGJHVZKLFKDUHSHUPLWWHGWRLPSOHPHQWWKHLU
LQLWLDOL]DWLRQGHYLFHVHOHFWLRQLQWHUQDOO\
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GLIIHUHQWLDWHGE\DQHQFRGLQJLQWKH&RQILJXUDWLRQ6SDFHKHDGHU7KHILUVWW\SHVLQJOH
IXQFWLRQGHYLFHLVGHILQHGIRUEDFNZDUGFRPSDWLELOLW\DQGRQO\XVHVLWVIDSELSLQDQG
AD[1::0]WRGHWHUPLQHZKHWKHURUQRWWRUHVSRQG
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• DFRQILJXUDWLRQFRPPDQGLVGHFRGHG
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7KHVHFRQGW\SHRIGHYLFHPXOWLIXQFWLRQGHYLFHGHFRGHVWKH)XQFWLRQ1XPEHUILHOG
AD[10::08]WRVHOHFWRQHRIHLJKWSRVVLEOHIXQFWLRQVRQWKHGHYLFHZKHQGHWHUPLQLQJ
ZKHWKHURUQRWWRUHVSRQG0XOWLIXQFWLRQGHYLFHVDUHUHTXLUHGWRGRDIXOOGHFRGHRQ
AD[10::08]DQGRQO\UHVSRQGWRWKHFRQILJXUDWLRQF\FOHLIWKH\KDYHLPSOHPHQWHGWKH
&RQILJXUDWLRQ6SDFHUHJLVWHUVIRUWKHVHOHFWHGIXQFWLRQ7KH\PXVWQRWUHVSRQG0DVWHU
$ERUWWHUPLQDWLRQWRXQLPSOHPHQWHGIXQFWLRQQXPEHUV7KH\DUHDOVRUHTXLUHGWR
DOZD\VLPSOHPHQWIXQFWLRQLQWKHGHYLFH,PSOHPHQWLQJRWKHUIXQFWLRQVLVRSWLRQDODQG
PD\EHDVVLJQHGLQDQ\RUGHULHDWZRIXQFWLRQGHYLFHPXVWUHVSRQGWRIXQFWLRQEXW
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IXQFWLRQVWKURXJKDQGWKURXJKDUHQRWWKHGHYLFHZRXOGDVVHUWDEVSEL#IRUD
FRQILJXUDWLRQWUDQVDFWLRQLQZKLFKIDSELLVDVVHUWHGDQGAD[1::0]DUHDQG
AD[10::08]PDWFKHVRUAD[31::11]DUHLJQRUHGE\DPXOWLIXQFWLRQGHYLFH
GXULQJDQDFFHVVRILWVFRQILJXUDWLRQUHJLVWHUV
7KHRUGHULQZKLFKFRQILJXUDWLRQVRIWZDUHSUREHVGHYLFHVUHVLGLQJRQDEXVVHJPHQWLV
QRWVSHFLILHG7\SLFDOO\FRQILJXUDWLRQVRIWZDUHHLWKHUVWDUWVZLWK'HYLFH1XPEHUDQG
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35
Revision 2.2
WKDW'HYLFH1XPEHUZLOOEHFKHFNHG,IDPXOWLIXQFWLRQGHYLFHLVGHWHFWHGLHELWLQ
WKH+HDGHU7\SHUHJLVWHURIIXQFWLRQLVWKHQDOOUHPDLQLQJ)XQFWLRQ1XPEHUVZLOO
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HQDEOHVWRGHWHUPLQHZKLFKE\WHVZLWKLQWKHDGGUHVVHG':25'DUHEHLQJDFFHVVHG$
IXQFWLRQPXVWQRWUHVWULFWWKHVL]HRIWKHDFFHVVLWVXSSRUWVLQ&RQILJXUDWLRQ6SDFH7KH
FRQILJXUDWLRQFRPPDQGVOLNHRWKHUFRPPDQGVDOORZGDWDWREHDFFHVVHGXVLQJDQ\
FRPELQDWLRQRIE\WHVLQFOXGLQJDE\WHZRUG':25'RUQRQFRQWLJXRXVE\WHVDQG
PXOWLSOHGDWDSKDVHVLQDEXUVW7KHWDUJHWLVUHTXLUHGWRKDQGOHDQ\FRPELQDWLRQRIE\WH
HQDEOHV+RZHYHULWLVQRWUHTXLUHGWRKDQGOHDFRQILJXUDWLRQWUDQVDFWLRQWKDWFRQVLVWVRI
PXOWLSOHGDWDSKDVHV,IDFRQILJXUDWLRQWUDQVDFWLRQFRQVLVWVRIPRUHWKDQDVLQJOHGDWD
SKDVHWKHWDUJHWLVSHUPLWWHGWRWHUPLQDWHWKHUHTXHVWZLWK'LVFRQQHFW7KLVLVQRW
VXIILFLHQWFDXVHIRUWKHWDUJHWWRWHUPLQDWHWKHWUDQVDFWLRQZLWK7DUJHW$ERUWVLQFHWKLVLV
QRWDQHUURUFRQGLWLRQ
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RQO\DGGUHVVLQJPRGHDOORZHGVLQFHAD[1::0]FRQYH\FRQILJXUDWLRQWUDQVDFWLRQW\SH
DQGQRWDEXUVWDGGUHVVLQJPRGHOLNH0HPRU\DFFHVVHV7KHLPSOLHGDGGUHVVRIHDFK
VXEVHTXHQWGDWDSKDVHLVRQH':25'ODUJHUWKDQWKHSUHYLRXVGDWDSKDVH)RUH[DPSOH
DWUDQVDFWLRQVWDUWVZLWKAD[7::2] HTXDOWR[[EWKHVHTXHQFHRIDEXUVWZRXOG
EH[[E[[E[[E[[EZKHUH[[LQGLFDWHZKHWKHUWKH
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1RWH7KH3&,WR3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQUHVWULFWV7\SHFRQILJXUDWLRQ
WUDQVDFWLRQVWKDWDUHFRQYHUWHGLQWRDWUDQVDFWLRQWKDWXVHVD6SHFLDO&\FOHFRPPDQGWRD
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3.2.2.3.5. System Generation of IDSEL
([DFWO\KRZWKHIDSELSLQLVGULYHQLVOHIWWRWKHGLVFUHWLRQRIWKHKRVWPHPRU\EULGJH
RUV\VWHPGHVLJQHU7KLVVLJQDOKDVEHHQGHVLJQHGWRDOORZLWVFRQQHFWLRQWRRQHRIWKH
XSSHUDGGUHVVOLQHVZKLFKDUHQRWRWKHUZLVHXVHGLQDFRQILJXUDWLRQDFFHVV
+RZHYHUWKHUHLVQRVSHFLILHGZD\RIGHWHUPLQLQJIDSELIURPWKHXSSHUDGGUHVV
ELWV7KHUHIRUHWKHIDSELSLQPXVWEHVXSSRUWHGE\DOOWDUJHWV'HYLFHVPXVWQRWPDNH
DQLQWHUQDOFRQQHFWLRQEHWZHHQDQADOLQHDQGDQLQWHUQDOIDSELVLJQDOLQRUGHUWRVDYH
DSLQ7KHRQO\H[FHSWLRQLVWKHKRVWEULGJHVLQFHLWGHILQHVKRZIDSELVDUHPDSSHG
IDSELJHQHUDWLRQEHKLQGD3&,WR3&,EULGJHLVVSHFLILHGLQWKH3&,WR3&,%ULGJH
$UFKLWHFWXUH6SHFLILFDWLRQ
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FRPSDWLEOHV\VWHPDQGWKHJHQHUDWLRQRIDQIDSELLVQRWVSHFLILHG7KHUHIRUH%,26
PXVWVFDQDOOGHYLFHQXPEHUVWRHQVXUHDOOFRPSRQHQWVDUHORFDWHG1RWH7KH
KDUGZDUHWKDWFRQYHUWVWKHGHYLFHQXPEHUWRDQIDSELLVUHTXLUHGWRHQVXUHWKDWRQO\D
VLQJOHXQLTXHIDSELOLQHLVDVVHUWHGIRUHDFKGHYLFHQXPEHU&RQILJXUDWLRQWUDQVDFWLRQV
WKDWDUHQRWFODLPHGE\DGHYLFHDUHWHUPLQDWHGZLWK0DVWHU$ERUW7KHPDVWHUWKDW
LQLWLDWHGWKLVWUDQVDFWLRQVHWVWKHUHFHLYHG0DVWHU$ERUWELWLQWKH6WDWXVUHJLVWHU
36
Revision 2.2
Implementation Note: System Generation of IDSEL
+RZDV\VWHPJHQHUDWHVIDSELLVV\VWHPVSHFLILFKRZHYHULIQRRWKHUPDSSLQJLV
UHTXLUHGWKHIROORZLQJH[DPSOHPD\EHXVHG7KHIDSELVLJQDODVVRFLDWHGZLWK'HYLFH
1XPEHULVFRQQHFWHGWRAD[16]IDSELRI'HYLFH1XPEHULVFRQQHFWHGWRAD[17]
DQGVRIRUWKXQWLOIDSELRI'HYLFH1XPEHULVFRQQHFWHGWRAD[31])RU'HYLFH
1XPEHUVWKHKRVWEULGJHVKRXOGH[HFXWHWKHWUDQVDFWLRQEXWQRWDVVHUWDQ\RIWKH
AD[31::16]OLQHVEXWDOORZWKHDFFHVVWREHWHUPLQDWHGZLWK0DVWHU$ERUW
7ZHQW\RQHGLIIHUHQWGHYLFHVFDQEHXQLTXHO\VHOHFWHGIRUFRQILJXUDWLRQDFFHVVHVE\
FRQQHFWLQJDGLIIHUHQWDGGUHVVOLQHWRHDFKGHYLFHDQGDVVHUWLQJRQHRIWKHAD[31::11]
OLQHVDWDWLPH7KHLVVXHZLWKFRQQHFWLQJRQHRIWKHXSSHUADOLQHVWRIDSELLVDQ
DGGLWLRQDOORDGRQWKHADOLQH7KLVFDQEHPLWLJDWHGE\UHVLVWLYHO\FRXSOLQJIDSELWR
WKHDSSURSULDWHADOLQH7KLVGRHVKRZHYHUFUHDWHDYHU\VORZVOHZUDWHRQIDSEL
FDXVLQJLWWREHLQDQLQYDOLGORJLFVWDWHPRVWRIWKHWLPHDVVKRZQLQ)LJXUHZLWKWKH
;;;;PDUNV+RZHYHUVLQFHLWLVRQO\XVHGRQWKHDGGUHVVSKDVHRID7\SH
FRQILJXUDWLRQWUDQVDFWLRQWKHDGGUHVVEXVFDQEHSUHGULYHQDIHZFORFNVEHIRUH
FRAME# WKXVJXDUDQWHHLQJIDSELWREHVWDEOHZKHQLWQHHGVWREHVDPSOHG3UH
GULYLQJWKHDGGUHVVEXVLVHTXLYDOHQWWRDGGUHVVVWHSSLQJDVGLVFXVVHGLQ6HFWLRQ
1RWHWKDWLIUHVLVWLYHFRXSOLQJLVXVHGWKHEULGJHWKDWJHQHUDWHVWKHFRQILJXUDWLRQ
WUDQVDFWLRQLVUHTXLUHGWRXVHDGGUHVVVWHSSLQJRUHQVXUHWKDWWKHFORFNSHULRGLV
VXIILFLHQWO\ORQJWRDOORZIDSELWREHFRPHVWDEOHEHIRUHLQLWLDWLQJWKHFRQILJXUDWLRQ
WUDQVDFWLRQ)RUDOORWKHUF\FOHVIDSELLVXQGHILQHGDQGPD\EHDWDQRQGHWHUPLQLVWLF
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16
The number of clocks the address bus should be pre-driven is determined from the RC time constant on
IDSEL.
37
Revision 2.2
CLK
1
2
3
4
5
6
FRAME#
AD
ADDRESS
DATA
IDSEL
C/BE#
CFG-RD
BE#'s
IRDY#
TRDY#
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3.2.3. Byte Lane and Byte Enable Usage
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GHYLFHWKDWLVDFFHVVHGZLWKDELWUHTXHVWFRXOGWUDQVIHUWKHORZHUELWVDQGUHTXLUH
WKHPDVWHUWRPRYHWKHXSSHUELWVRIWKHELWDFFHVVGRZQWRWKHORZHUE\WHODQHWR
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WKHFKDUDFWHULVWLFVRIWKHWDUJHWGHYLFHDQGRQO\LVVXHVDSSURSULDWHOHQJWKDFFHVVHV
7KHEXVSURWRFROUHTXLUHVDXWRPDWLFEXVVL]LQJLIDPDVWHUUHTXHVWVDELWGDWDWUDQVIHU
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Revision 2.2
3.3.3.2. Target Initiated Termination
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master, or there is a conflict for a internal resource.
Retry is a special case of Disconnect without data being transferred on
the initial data phase.
The target signals Retry by asserting STOP# and not asserting
TRDY# on the initial data phase of the transaction (STOP# cannot be
asserted during the turn-around cycle between the address phase and
first data phase of a read transaction). When the target uses Retry, no
data is transferred.
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refers to termination requested with or after data was transferred on
the initial data phase because the target is unable to respond within the
target subsequent latency requirement and, therefore, is temporarily
unable to continue bursting. This might be because the burst crosses a
resource boundary or a resource conflict occurs. Data may or may not
transfer on the data phase where Disconnect is signaled. Notice that
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data phase, and no data transfers. If data is transferred with or before
the target terminates the transaction, it is a Disconnect. This may also
occur on the initial data phase because the target is not capable of
doing a burst.
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TRDY# and STOP# together. This termination is used when the
target is only willing to complete the current data phase and no more.
Disconnect without data may be signaled on any subsequent data
phase (meaning data was transferred on the previous data phase) by
deasserting TRDY# and asserting STOP#.
52
Revision 2.2
Target-Abort
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request. Although it may cause a fatal error for the application
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byte in this range. Since the target cannot complete the request, the
target terminates the request with Target-Abort.
Once the target has claimed an access by asserting DEVSEL#, it can
signal Target-Abort on any subsequent clock. The target signals
Target-Abort by deasserting DEVSEL# and asserting STOP# at the
same time.
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54
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Revision 2.2
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68
Revision 2.2
Implementation Note: System Arbitration Algorithm
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69
Revision 2.2
3.4.1. Arbitration Signaling Protocol
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Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win
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70
Revision 2.2
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71
Revision 2.2
3.4.2. Fast Back-to-Back Transactions
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The second type of fast back-to-back support places the burden of no contention on all
potential targets. The Fast Back-to-Back Capable bit in the Status register may be
hardwired to a logical one (high) if, and, only if, the device, while acting as a bus target,
meets the following two requirements:
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It is recommended that this be done by returning the target state machine (refer to Appendix B) from the
B_BUSY state to the IDLE state as soon as FRAME# is deasserted and the device’s decode time has been
met (a miss occurs) or when DEVSEL# is asserted by another target and not waiting for a bus Idle state
(IRDY# deasserted).
72
Revision 2.2
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3.5.4.1. Bandwidth and Latency Considerations
In PCI systems, there is a tradeoff between the desire to achieve low latency and the
desire to achieve high bandwidth (throughput). High throughput is achieved by allowing
devices to use long burst transfers. Low latency is achieved by reducing the maximum
burst transfer length. The following discussion is provided (for a 32-bit bus) to illustrate
this tradeoff.
A given PCI bus master introduces latency on PCI each time it uses the PCI bus to do a
transaction. This latency is a function of the behavior of both the master and the target
device during the transaction as well as the state of the master’s GNT# signal. The bus
command used, transaction burst length, master data latency for each data phase, and the
Latency Timer are the primary parameters which control the master’s behavior. The bus
command used, target latency, and target subsequent latency are the primary parameters
which control the target’s behavior.
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A master is required to assert its IRDY# within eight clocks for any given data phase
(initial and subsequent). For the first data phase, a target is required to assert its TRDY#
or STOP# within 16 clocks from the assertion of FRAME# (unless the access hits a
modified cacheline in which case 32 clocks are allowed for host bus bridges). For all
subsequent data phases in a burst transfer, the target must assert its TRDY# or STOP#
within eight clocks. If the effects of the Latency Timer are ignored, it is a
straightforward exercise to develop equations for the worst case latencies that a PCI bus
master can introduce from these specification requirements.
latency_max (clocks) = 32 + 8 * (n-1)
if a modified cacheline is hit
(for a host bus bridge only)
or
= 16 + 8 * (n-1)
if not a modified cacheline
where n is the total number of data transfers in the transaction
However, it is more useful to consider transactions that exhibit typical behavior. PCI is
designed so that data transfers between a bus master and a target occur as register to
register transfers. Therefore, bus masters typically do not insert wait states since they
only request transactions when they are prepared to transfer data. Targets typically have
an initial access latency less than the 16 (32 for modified cacheline hit for host bus
bridge) clock maximum allowed. Once targets begin transferring data (complete their
first data phase), they are typically able to sustain burst transfers at full rate (one clock
per data phase) until the transaction is either completed by the master or the target’s
buffers are filled or are temporarily empty. The target can use the target Disconnect
protocol to terminate the burst transaction early when its buffers fill or temporarily
empty during the transaction. Using these more realistic considerations, the worst case
latency equations can be modified to give a typical latency (assuming that the target’s
initial data phase latency is eight clocks) again ignoring the effects of the Latency Timer.
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Data
Phases
Bytes
Transferred
Total
Clocks
Latency Timer
(clocks)
Bandwidth
(MB/s)
Latency
(ms)
8
32
16
14
60
.48
16
64
24
22
80
.72
32
128
40
38
96
1.20
64
256
72
70
107
2.16
Data Phases
Number of data phases completed during transaction
Bytes Transferred
Total number of bytes transferred during transaction (assuming
32-bit transfers)
Total Clocks
Total number of clocks used to complete the transfer
total_clocks
Latency Timer
= 8 + (n-1) + 1 (Idle time on bus)
Latency Timer value in clocks such that the Latency Timer
expires in next to last data phase
latency_timer = total_clocks - 2
Bandwidth
Calculated bandwidth in MB/s
bandwidth = bytes_transferred / (total clocks * 30 ns)
Latency
Latency in microseconds introduced by transaction
latency = total clocks * 30 ns
Table 3-4 clearly shows that as the burst length increases, the amount of data transferred
increases. Note: The amount of data doubles between each row in the table, while the
latency increases by less than double. The amount of data transferred between the first
row and the last row increases by a factor of 8, while the latency increases by a factor of
4.5. The longer the transaction (more data phases), the more efficiently the bus is being
used. However, this increase in efficiency comes at the expense of larger buffers.
3.5.4.2. Determining Arbitration Latency
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Table 3-5 lists the requirements of each device in the target system and how many
transactions each device must complete to sustain its bandwidth requirements within
10 µs time slices.
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The last column indicates how many different transactions that are required to move
the data. This assumes that the entire transfer cannot be completed as a single
transaction.
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Bandwidth
(MB/s)
Bytes/10 ms
Time Used
(ms)
Number of
Transactions
per Slice
Notes
Graphics
50
500
6.15
10
1
LAN
4
40
0.54
1
2
Disk
5
50
0.63
1
3
ISA bridge
4
40
0.78
2
4
PCI-to PCI
bridge
9
90
1.17
2
5
Total
72
720
9.27
16
Device
Notes:
86
1.
Graphics is a combination of host bus bridge and frame grabber writing data to the frame buffer.
The host moves 300 bytes using five transactions with 15 data phases each, assuming eight
clocks of target initial latency. The frame grabber moves 200 bytes using five transactions with
10 data phases each, assuming eight clocks of target initial latency.
2.
The LAN uses a single transaction with 10 data phases with eight clocks of target initial latency.
3.
The disk uses a single transaction with 13 data phases with eight clocks of target initial latency.
4.
The ISA bridge uses two transactions with five data phases each with eight clocks of target initial
latency.
5.
The PCI-to-PCI bridge uses two transactions. One transaction is similar to the LAN and the
second is similar to the disk requirements.
Revision 2.2
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Bandwidth
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Bytes/10 ms
Time Used
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Number of
Transactions
per Slice
Notes
Host
writing to
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buffer
40
400
4.2
5
1
Frame
grabber
20
200
3.7
5
2
Device
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The host uses five transactions with 20 data phases each, assuming eight clocks of target initial
latency.
2.
The frame grabber uses five transactions with 10 data phases each, assuming eight clocks of
target initial latency.
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output buffer of the device) rather than the signal received from the device input
buffer. For example, if logic internal to a device continuously monitors the state of
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when the device is not the current bus master, and it must use the internally
generated FRAME# when the device is the current bus master.
112
Revision 2.2
Chapter 4
Electrical Specification
4.1. Overview
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113
Revision 2.2
"5 volt" Board
I/O buffers powered on
5 volt rail
"3.3 volt" Board
I/O buffers powered on
3.3 volt rail
Dual Voltage Signaling Board
I/O buffers powered on
connector dependent rail
"5 volt" Connector
"3.3 volt" Connector
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27
While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and
expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI component
of this type is used on the Universal board, its I/O buffers may optionally be connected to the 3.3V rail
rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O"
designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V rail
with a simple diode must never be used in the 5V signaling environment.") Since the effective operation of
these high clamp diodes may be critical to both signal quality and device reliability, the designer must
provide enough extra "I/O" designated power pins on a component to handle the current spikes associated
with the 5V maximum AC waveforms (Section 4.2.1.3.).
114
Revision 2.2
4.1.2. Dynamic vs. Static Drive Specification
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28
It may be desirable to perform some production tests at bare silicon pads. Such tests may have different
parameters than those specified here and must be correlated back to this specification.
115
Revision 2.2
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116
Revision 2.2
4.2.1. 5V Signaling Environment
4.2.1.1. DC Specifications
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7DEOH'&6SHFLILFDWLRQVIRU96LJQDOLQJ
Symbol
Parameter
Vcc
Condition
Min
Max
Units
Supply Voltage
4.75
5.25
V
Vih
Input High Voltage
2.0
Vcc+0.5
V
Vil
Input Low Voltage
-0.5
0.8
V
Iih
Input High Leakage
Current
Vin = 2.7
70
µA
1
Iil
Input Low Leakage
Current
Vin = 0.5
-70
µA
1
Voh
Output High Voltage
Iout = -2 mA
Vol
Output Low Voltage
Iout = 3 mA, 6 mA
Cin
Input Pin Capacitance
Cclk
CLK Pin Capacitance
CIDSEL
2.4
Notes
V
0.55
V
2
10
pF
3
12
pF
IDSEL Pin Capacitance
8
pF
4
Lpin
Pin Inductance
20
nH
5
IOff
PME# input leakage
1
µA
6
5
Vo ≤ 5.25 V
Vcc off or floating
–
NOTES:
1.
Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2.
Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have
6 mA; the latter include, FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, INTA#,
INTB#, INTC#, INTD#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.
3.
Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to
motherboard-only devices up to 16 pF, in order to accommodate PGA packaging. This means, in general,
that components for expansion boards need to use alternatives to ceramic PGA packaging (i.e., PQFP,
SGA, etc.).
4.
Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
5.
This is a recommendation, not an absolute requirement. The actual value should be provided with the
component data sheet.
6.
This input leakage is the maximum allowable leakage into the PME# open drain driver when power is
removed from Vcc of the component. This assumes that no event has occurred to cause the device to
attempt to assert PME#.
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117
Revision 2.2
4.2.1.2. AC Specifications
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Symbol
Parameter
Condition
Min
Ioh(AC)
Switching
0<Vout<1.4
1.4<Vout<2.4
Current High
Iol(AC)
Max
Units
Notes
-44
mA
1
-44+(Vout-1.4)/0.024
mA
1, 2
3.1<Vout<Vcc
Eqt’n A
(Test Point)
Vout = 3.1
-142
Switching
Vout > 2.2
2.2>Vout>0.55
Current Low
1, 3
mA
3
95
mA
1
Vout/0.023
mA
1
0.71>Vout>0
Eqt’n B
1, 3
(Test Point)
Vout = 0.71
206
Icl
Low Clamp
Current
-5 < Vin ≤ -1
-25+(Vin+1)/0.015
slewr
Output Rise Slew
Rate
0.4V to 2.4V load
1
5
V / ns
4
slewf
Output Fall Slew
Rate
2.4V to 0.4V load
1
5
V / ns
4
mA
3
mA
NOTES:
118
1.
Refer to the V/I curves in Figure 4-2. Switching current characteristics for REQ# and GNT# are permitted
to be one half of that specified here; i.e., half size output drivers may be used on these signals. This
specification does not apply to CLK and RST# which are system outputs. "Switching Current High"
specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain
outputs.
2.
Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC
drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is
intended to allow for an optional N-channel pull-up.
3.
Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations
defining these maximums (A and B) are provided with the respective diagrams in Figure 4-3. The
equation-defined maximums should be met by design. In order to facilitate component testing, a
maximum current test point is defined for each side of the output driver.
Revision 2.2
4.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range. The specified load (diagram below) is optional;
i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI
Local Bus Specification . However, adherence to both maximum and minimum parameters is required (the
maximum is not simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster
edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this
specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew
rate does not apply to open drain outputs.
pin
1/2 in. max.
output
buffer
Vcc
1K Ω
10 pF
1K Ω
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119
Revision 2.2
Pull Up
Pull Down
Vcc
test
point
AC drive
point
Voltage
Voltage
Vcc
2.4
2.2
DC
drive point
1.4
DC drive
point
0.55
AC drive
point
-2
-44
Current (mA)
-176
test
point
3, 6
95
Current (mA)
380
Equation A:
Equation B:
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4.2.1.3. Maximum AC Ratings and Device Protection
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120
Revision 2.2
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Overvoltage Waveform
Voltage Source Impedance
R = 55 Ω
11 nSec
(min)
+ 11 v
11 v, p-to-p
(minimum)
5v. supply
R
V
4 nSec
(max)
Input
Buffer
Evaluation
Setup
0v
62.5 nSec
(16 MHz)
+ 5.25 v
10.75 v, p-to-p
(minimum)
Undervoltage Waveform
Voltage Source Impedance
R = 25 Ω
- 5.5 v
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29
Waveforms based on worst case (strongest) driver, maximum and minimum system configurations, with
no internal clamp diodes.
30
It is possible to use alternative clamps, such as a diode stack to the 3.3V rail or a circuit to ground, if it
can be insured that the I/O pin will never be clamped below the 5V level.
121
Revision 2.2
4.2.2. 3.3V Signaling Environment
4.2.2.1. DC Specifications
7DEOHVXPPDUL]HVWKH'&VSHFLILFDWLRQVIRU9VLJQDOLQJ
7DEOH'&6SHFLILFDWLRQVIRU96LJQDOLQJ
Symbol
Parameter
Vcc
Condition
Min
Max
Units
Supply Voltage
3.0
3.6
V
Vih
Input High Voltage
0.5Vcc
Vcc + 0.5
V
Vil
Input Low Voltage
-0.5
0.3Vcc
V
Vipu
Input Pull-up Voltage
0.7Vcc
Iil
Input Leakage Current
0 < Vin < Vcc
Voh
Output High Voltage
Iout = -500 µA
Vol
Output Low Voltage
Iout = 1500 µA
Cin
Input Pin Capacitance
Cclk
CLK Pin Capacitance
CIDSEL
+10
0.9Vcc
Notes
V
1
µA
2
V
0.1Vcc
V
10
pF
12
pF
IDSEL Pin Capacitance
8
pF
4
Lpin
Pin Inductance
20
nH
5
IOff
PME# input leakage
1
µA
6
5
Vo ≤ 3.6 V
Vcc off or
floating
–
3
NOTES:
1.
This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors
are calculated to pull a floated network. Applications sensitive to static power utilization must assure that
the input buffer is conducting minimum current at this input voltage.
2.
Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
3.
Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted to
motherboard-only devices up to 16 pF in order to accommodate PGA packaging. This would mean in
general that components for expansion boards need to use alternatives to ceramic PGA packaging; i.e.,
PQFP, SGA, etc.
4.
Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
5.
This is a recommendation, not an absolute requirement. The actual value should be provided with the
component data sheet.
6.
This input leakage is the maximum allowable leakage into the PME# open drain driver when power is
removed from Vccof the component. This assumes that no event has occurred to cause the device to
attempt to assert PME#.
5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUAD[63::32]C/BE[7::4]#DQG
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122
Revision 2.2
4.2.2.2. AC Specifications
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Symbol Parameter
Ioh(AC)
Switching
Current High
(Test Point)
Iol(AC)
Switching
Current Low
Condition
Min
0<Vout<0.3Vcc
0.3Vcc<Vout<0.9Vcc
Max
Units
Notes
-12Vcc
mA
1
-17.1(Vcc-Vout)
mA
1
0.7Vcc<Vout<Vcc
Eqt’n C
Vout = 0.7Vcc
-32Vcc
1, 2
mA
2
Vcc>Vout>0.6Vcc
16Vcc
mA
1
0.6Vcc>Vout>0.1Vcc
26.7Vout
mA
1
0.18Vcc>Vout>0
Eqt’n D
1, 2
(Test Point)
Vout = 0.18Vcc
38Vcc
Icl
Low Clamp
Current
-3<Vin ≤ -1
-25+(Vin+1)/0.015
mA
Ich
High Clamp
Current
Vcc+4>Vin ≥ Vcc+1
25+(Vin-Vcc-1)/0.015
mA
slewr
Output Rise Slew
Rate
0.2Vcc - 0.6Vcc load
1
4
V/ns
3
slewf
Output Fall Slew
Rate
0.6Vcc - 0.2Vccl load
1
4
V/ns
3
mA
2
NOTES:
1.
Refer to the V/I curves in Figure 4-4. Switching current characteristics for REQ# and GNT# are permitted
to be one half of that specified here; i.e., half size output drivers may be used on these signals. This
specification does not apply to CLK and RST# which are system outputs. "Switching Current High"
specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain
outputs.
2.
Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations
defining these maximums (C and D) are provided with the respective diagrams in Figure 4-5. The
equation-defined maximums should be met by design. In order to facilitate component testing, a
maximum current test point is defined for each side of the output driver.
3.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range. The specified load (diagram below) is optional;
i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI
Local Bus Specification . However, adherence to both maximum and minimum parameters is required (the
maximum is not simply a guideline). Rise slew rate does not apply to open drain outputs.
pin
1/2 in. max.
output
buffer
Vcc
1K Ω
10 pF
1K Ω
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123
Revision 2.2
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Pull Down
Pull Up
Vcc
Voltage
0.9
Vcc
AC drive
point
Voltage
Vcc
test
point
0.6
Vcc
DC
drive point
0.5 Vcc
DC drive
point
0.3
Vcc
0.1
Vcc
AC drive
point
-0.5
-12
Current (mA)
-48
(TXDWLRQ&
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test
point
1.5
16
Current (mA)
64
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124
Revision 2.2
4.2.2.3. Maximum AC Ratings and Device Protection
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Overvoltage Waveform
Voltage Source Impedance
R = 29 Ω
11 nSec
(min)
+ 7.1 v
7.1 v, p-to-p
(minimum)
3.3v. supply
R
V
4 nSec
(max)
Input
Buffer
Evaluation
Setup
0v
62.5 nSec
(16 MHz)
+ 3.6 v
7.1 v, p-to-p
(minimum)
- 3.5 v
Undervoltage Waveform
Voltage Source Impedance
R = 28 Ω
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125
Revision 2.2
4.2.3. Timing Specification
4.2.3.1. Clock Specification
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5 volt Clock
2.4 v
2.0 v
2 v, p-to-p
(minimum)
1.5 v
0.8 v
0.4 v
T_cyc
T_high
3.3 volt Clock
0.6 Vcc
T_low
0.5 Vcc
0.4 Vcc, p-to-p
(minimum)
0.4 Vcc
0.3 Vcc
0.2 Vcc
)LJXUH&ORFN:DYHIRUPV
126
Revision 2.2
7DEOH&ORFNDQG5HVHW6SHFLILFDWLRQV
Symbol
Parameter
Min
Max
Units
Notes
∞
ns
1
Tcyc
CLK Cycle Time
30
Thigh
CLK High Time
11
ns
Tlow
CLK Low Time
11
ns
-
CLK Slew Rate
1
4
V/ns
2
-
RST# Slew Rate
50
-
mV/ns
3
NOTES:
1.
In general, all PCI components must work with any clock frequency between
nominal DC and 33 MHz. Device operational parameters at frequencies under
16 MHz may be guaranteed by design rather than by testing. The clock
frequency may be changed at any time during the operation of the system so
long as the clock edges remain "clean" (monotonic) and the minimum cycle
and high and low times are not violated. For example, the use of spread
spectrum techniques to reduce EMI emissions is included in this requirement.
Refer to Section 7.6.41. for the spread spectrum requirements for 66 MHz.
The clock may only be stopped in a low state. A variance on this specification
is allowed for components designed for use on the system motherboard only.
These components may operate at any single fixed frequency up to 33 MHz
and may enforce a policy of no frequency changes.
2.
Rise and fall times are specified in terms of the edge rate measured in V/ns.
This slew rate must be met across the minimum peak-to-peak portion of the
clock waveform as shown in Figure 4-6.
3.
The minimum RST# slew rate applies only to the rising (deassertion) edge of
the reset signal and ensures that system noise cannot render an otherwise
monotonic signal to appear to bounce in the switching range. RST#
waveforms and timing are discussed in Section 4.3.2.
127
Revision 2.2
4.2.3.2. Timing Parameters
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Symbol
Parameter
Min
Max
Units
Notes
Tval
CLK to Signal Valid Delay - bused signals
2
11
ns
1, 2, 3
Tval(ptp)
CLK to Signal Valid Delay - point to point
2
12
ns
1, 2, 3
Ton
Float to Active Delay
2
ns
1, 7
Toff
Active to Float Delay
ns
1, 7
Tsu
Input Setup Time to CLK - bused signals
7
ns
3, 4, 8
Tsu(ptp)
Input Setup Time to CLK - point to point
10, 12
ns
3, 4
28
Th
Input Hold Time from CLK
0
ns
4
Trst
Reset active time after power stable
1
ms
5
Trst-clk
Reset active time after CLK STABLE
100
µs
5
Trst-off
Reset Active to Output Float delay
ns
5, 6,7
40
Trrsu
REQ64# to RST# Setup time
10*Tcyc
Trrh
RST# to REQ64# Hold time
0
ns
50
25
Trhfa
RST# High to First configuration Access
2
Trhff
RST# High to First FRAME# assertion
5
ns
clocks
clocks
NOTES:
1.
See the timing measurement conditions in Figure 4-7.
2.
For parts compliant to the 5V signaling environment:
Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF
equivalent load. Actual test capacitance may vary, but results must be correlated to these
specifications. Note that faster buffers may exhibit some ring back when attached to a 50 pF lump
load which should be of no consequence as long as the output buffers are in full compliance with
slew rate and V/I curve specifications.
For parts compliant to the 3.3V signaling environment:
Minimum times are evaluated with same load used for slew rate measurement (as shown in
Table 4-4, note 3); maximum times are evaluated with the following load circuits, for high-going
and low-going edges respectively.
Tval(max) Rising Edge
pin
Tval(max) Falling Edge
1/2 in. max.
1/2 in. max.
output
buffer
25 Ω
Vcc
10 pF
25 Ω
10 pF
128
3.
REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bused signals. GNT# has a setup of 10; REQ# has a setup of 12. All other signals are bused.
4.
See the timing measurement conditions in Figure 4-8.
5.
CLK is stable when it meets the requirements in Section 4.2.3.1. RST# is asserted and deasserted
asynchronously with respect to CLK. Refer to Section 4.3.2. for more information.
Revision 2.2
6.
All output drivers must be asynchronously floated when RST# is active. Refer to Section 3.10.2. for
special requirements for AD[63::32], C/BE[7::4]#, and PAR64 when they are not connected (as in a 64-bit
expansion board installed in a 32-bit connector).
7.
For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
8.
Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals
at the same time. Refer to Section 3.10., item 9, for additional details.
4.2.3.3. Measurement and Test Conditions
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V_th
CLK
V_test
V_tl
T_val
OUTPUT
DELAY
V_test (5v. signaling)
V_trise, V_tfall (3.3v. signaling)
output current
leakage current
Tri-State
OUTPUT
T_on
T_off
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V_th
CLK
V_test
V_tl
T_su
T_h
V_th
INPUT
V_test
inputs
valid
V_test
V_max
V_tl
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129
Revision 2.2
7DEOH0HDVXUH&RQGLWLRQ3DUDPHWHUV
Symbol
5V Signaling
3.3V Signaling
Units
Vth
2.4
0.6Vcc
V (Note)
Vtl
0.4
0.2Vcc
V (Note)
Vtest
1.5
0.4Vcc
V
Vtrise
n/a
0.285Vcc
V
Vtfall
n/a
0.615Vcc
V
Vmax
2.0
0.4Vcc
V (Note)
Input Signal
Edge Rate
1 V / ns
NOTE:
The input test for the 5V environment is done with 400 mV of overdrive
(over Vih and Vil); the test for the 3.3V environment is done with
0.1Vcc of overdrive. Timing parameters must be met with no more
overdrive than this. V max specifies the maximum peak-to-peak
waveform allowed for measuring input timing. Production testing may
use different voltage values, but must correlate results back to these
parameters.
4.2.4. Indeterminate Inputs and Metastability
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UHVLVWLYHFRQQHFWLRQWRDQADOLQHLVXVHGLWPD\WHQGWRIORDWDURXQGWKHVZLWFKLQJ
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130
Revision 2.2
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DIWHUWKH\KDYHEHHQGHDVVHUWHG
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4.2.5. Vendor Provided Specification
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FRPSRQHQWVWRJXDUDQWHHSURSHURSHUDWLRQ7RKHOSIDFLOLWDWHWKLVHIIRUWFRPSRQHQW
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EHVWW\SLFDOZRUVWFXUYHV$OVREH\RQGWKHUDLOUHVSRQVHLVFULWLFDOVRWKHYROWDJH
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4.2.6. Pinout Recommendation
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ZLWKPLQLPXPVWXEV)LJXUHVKRZVWKHUHFRPPHQGHGSLQRXWIRUDW\SLFDO34)33&,
FRPSRQHQW1RWHWKDWWKHSLQRXWLVH[DFWO\DOLJQHGZLWKWKHVLJQDORUGHURQWKHERDUG
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7KHDGGLWLRQDOVLJQDOVQHHGHGLQELWYHUVLRQVRIWKHEXVFRQWLQXHZUDSSLQJDURXQGWKH
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131
Revision 2.2
JTAG
{
PCI Component
RST#
CLK
GNT
REQ
All PCI Shared Signals
Below this Line
REQ64#
ACK64#
AD[0]
.
AD[7]
C/BE0#
AD[23]
.
AD[16]
C/BE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
LOCK#
PERR#
SERR#
PAR
C/BE1#
AD[15]
.
.
AD[8]
AD[31]
.
.
AD[24]
C/BE3#
IDSEL
PAR64
AD[32]
.
.
AD[63]
C/BE4#
C/BE5#
C/BE6#
C/BE7#
PCI Card Edge
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4.3. System (Motherboard) Specification
4.3.1. Clock Skew
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VLQJOHWKUHVKROGSRLQWEXWDWDOOSRLQWVRQWKHFORFNHGJHWKDWIDOOLQWKHVZLWFKLQJUDQJH
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FRPSRQHQWVUDWKHUWKDQEHWZHHQFRQQHFWRUV7RFRUUHFWO\HYDOXDWHFORFNVNHZWKH
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31 Non-resistive connections of IDSEL to one of the AD[xx] lines create a technical violation of the single
load per expansion board rule. PCI protocol provides for pre-driving of address lines in configuration
cycles, and it is recommended that this be done in order to allow a resistive coupling of IDSEL. In absence
of this, signal performance must be derated for the extra IDSEL load.
32
The system designer must address an additional source of skew. This clock skew occurs between two
components that have clock input trip points at opposite ends of the Vil - Vih range. In certain
circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew
must be limited to the specified number.
132
Revision 2.2
7DEOH&ORFN6NHZ3DUDPHWHUV
Symbol
5V Signaling
3.3V Signaling
Units
Vtest
1.5
0.4 Vcc
V
Tskew
2 (max)
2 (max)
ns
V_ih
CLK
(@Device #1)
V_test
V_il
T_skew
T_skew
T_skew
V_ih
CLK
(@Device #2)
V_test
V_il
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4.3.2. Reset
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UHVSHFWWRCLK7KHULVLQJGHDVVHUWLRQHGJHRIWKHRST#VLJQDOPXVWEHPRQRWRQLF
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VSHFLILHGLQ7DEOH7KH3&,VSHFLILFDWLRQGRHVQRWSUHFOXGHWKHLPSOHPHQWDWLRQRID
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SDWKVFRXOGVKRUWFLUFXLWDFWLYHRXWSXWEXIIHUV7KHUHIRUHRST#LVDVVHUWHGXSRQSRZHU
IDLOXUHLQRUGHUWRIORDWWKHRXWSXWEXIIHUV
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•
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P9
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RUGHUWRPLQLPL]HSRVVLEOHYROWDJHFRQWHQWLRQEHWZHHQ9DQG9SDUWVRST#PXVW
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$IWHURST#LV DVVHUWHG3&,FRPSRQHQWVPXVWDV\QFKURQRXVO\GLVDEOHIORDWWKHLU
RXWSXWVEXWDUHQRWFRQVLGHUHGUHVHWXQWLOERWK7UVWDQG7UVWFONSDUDPHWHUVKDYHEHHQ
PHW)LJXUHVKRZVRST#VLJQDOWLPLQJ
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GHOD\IROORZLQJWKHGHDVVHUWLRQRIRST#WRDGHYLFHEHIRUHWKHV\VWHPZLOOSHUPLWWKH
33
Component vendors should note that a fixed timing relationship between RST# and power sequencing
cannot be guaranteed in all cases.
133
Revision 2.2
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•
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Implementation Note: Reset
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134
Revision 2.2
Implementation Note: Trhfa
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V\VWHPZLWKQR3&,VORWVZRXOGRQO\QHHGWRZDLWIRUWKHLQLWLDOL]DWLRQUHTXLUHPHQWVRI
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34
This reset timing figure optionally shows the "PWR_GOOD" signal as a pulse which is used to time the
RST# pulse. In many systems, "PWR_GOOD" may be a level, in which case the RST# pulse must be
timed in another way.
135
Revision 2.2
4.3.3. Pull-ups
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SERR#PERR#LOCK#, INTA#, INTB#, INTC#, INTD#,REQ64#DQG ACK64#
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7KHIRUPXODVIRUPLQLPXPDQGPD[LPXPSXOOXSUHVLVWRUVDUHSURYLGHGEHORZ5PLQLV
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DVHFRQGDU\HIIHFW2QWKHRWKHUKDQG5PD[LVSULPDULO\GULYHQE\WKHQXPEHURIORDGV
SUHVHQW7KHVSHFLILFDWLRQSURYLGHVIRUDPLQLPXP5YDOXHWKDWLVFDOFXODWHGEDVHGRQ
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PD[LPXP5YDOXHZLWKORDGV7KHPD[LPXP5YDOXHLVSURYLGHGE\IRUPXODRQO\
DQGZLOOEHWKHKLJKHVWLQDV\VWHPZLWKWKHVPDOOHVWQXPEHURIORDGV
5
PLQ
5
PD[
= >9FF
PD[ = >9FF
PLQ − 9 @ > , + ⋅ , @ , where 16 = max number of loads
RO
RO
LO
− 9[ @ > QXP B ORDGV × ,LK @,
where: 9[ = Y for 5V signaling, and 9[ = 9FF for 3.3V signaling.
7DEOHSURYLGHVPLQLPXPDQGW\SLFDOYDOXHVIRUERWK9DQG9VLJQDOLQJ
HQYLURQPHQWV7KHW\SLFDOYDOXHVKDYHEHHQGHUDWHGIRUUHVLVWRUVDWQRPLQDOYDOXHV
7DEOH0LQLPXPDQG7\SLFDO3XOOXS5HVLVWRU9DOXHV
Signaling Rail
Rmin
Rtypical
Rmax
5V
963 Ω
2.7 KΩ @ 10%
see formula
3.3V
2.42 KΩ
8.2 KΩ @ 10%
see formula
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ZHDNSXOOXSRQHDFKXQFRQQHFWHGREQ#SLQDQGHDFKREQ#SLQFRQQHFWHGWRD3&,
H[SDQVLRQVORWLQRUGHUWRLQVXUHWKDWWKHVHVLJQDOVGRQRWIORDW9DOXHVIRUWKLVSXOOXS
VKDOOEHVSHFLILHGE\WKHFHQWUDOUHVRXUFHYHQGRU
6\VWHPVXWLOL]LQJPME#PXVWSURYLGHDSXOOXSRQWKDWVLJQDO7KHUHVLVWRUYDOXHXVHGLV
FDOFXODWHGXVLQJWKHIRUPXODVDERYHEXWVXEVWLWXWLQJ, IRU, 2II
136
LK
Revision 2.2
4.3.4. Power
4.3.4.1. Power Requirements
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7DEOH3RZHU6XSSO\5DLO7ROHUDQFHV
Power Rail
5 V ±5%
3.3 V ±0.3 V
Expansion Boards (Short and Long)
5 A max. (system dependent)
7.6 A max. (system dependent)
12 V ±5%
500 mA
-12 V ±10%
100 mA
4.3.4.2. Sequencing
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137
Revision 2.2
4.3.4.3. Decoupling
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4.3.5. System Timing Budget
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EXLOGODUJHU3&,WRSRORJLHVKDYLQJ7SURSYDOXHVODUJHUWKDQWKRVHVSHFLILHGKHUH6LQFH
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138
Revision 2.2
Implementation Note: Determining the End of Tprop
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139
Revision 2.2
Vth
Driving
Test Load
Vth
Input Signal
Edge Rate
Driving
2.0V
Vih
Driving
Bus
2.0V
Vtest
Vih Test Load
Driving
Bus
Vtest
1.0V
1.0V
Tprop
Tprop
(a)
Vth
(b)
Driving
Test Load
Tprop
2.0V
Driving
Bus
Vih
2.0V
Input
Signal
Edge
Rate
Vtest
Vtest
Driving Bus
1.0V
1.0V
Tprop
Vil
Vtl
Driving Test Load
(c)
(d)
Tprop
Tprop
2.0V
2.0V
Vtest
Vtest
Input Signal
Edge Rate
1.0V
1.0V
Vil
Driving
Bus
Vtl
Driving Test Load
(e)
Input Signal
Edge Rate
Driving
Test Load
Vil
Vtl
Driving Bus
(f)
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140
Revision 2.2
4.3.6. Physical Requirements
4.3.6.1. Routing and Layout Recommendations for Four-Layer
Motherboards
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VLJQDOHJ0+]LVUHIHUHQFHGWRERWKSODQHV6LJQDOWUDFHVVKRXOGHLWKHUUHPDLQ
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VLJQDOVPXVWEHURXWHGRYHUWKHSODQHVSOLWWKHWZRSODQHVVKRXOGEHFDSDFLWLYHO\WLHG
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IRUHDFKIRXUVLJQDOVFURVVLQJWKHVSOLWDQGWKHFDSDFLWRUVKRXOGEHSODFHGQRWPRUHWKDQ
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4.3.6.2. Motherboard Impedance
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141
Revision 2.2
4.3.7. Connector Pin Assignments
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WRJURXQGZLWKµ)KLJKVSHHGFDSDFLWRUVEHFDXVHRQHRUERWKRIWKHSLQVDOVR
SURYLGHDQ$&UHWXUQSDWK7KHVHSLQVPD\QRWEHEXVHGRURWKHUZLVHFRQQHFWHGWRHDFK
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GHVFULEHGLQ6HFWLRQ)RUDOORWKHU3&,FRQQHFWRUVWKLVSLQPXVWEHWUHDWHGLQDOO
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SODQH
142
Revision 2.2
7DEOH3&,&RQQHFWRU3LQRXW
5V System Environment
3.3V System Environment
Pin
Side B
Side A
Side B
Side A
Comments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
Ground
Ground
Reserved
Ground
CLK
Ground
REQ#
+5V (I/O)
AD[31]
AD[29]
Ground
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
Ground
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
Ground
IRDY#
+3.3V
DEVSEL#
Ground
LOCK#
PERR#
+3.3V
SERR#
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+5V (I/O)
Reserved
Ground
Ground
3.3Vaux
RST#
+5V (I/O)
GNT#
Ground
PME#
AD[30]
+3.3V
AD[28]
AD[26]
Ground
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
Ground
AD[18]
AD[16]
+3.3V
FRAME#
Ground
TRDY#
Ground
STOP#
+3.3V
Reserved*
Reserved*
Ground
-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+3.3V (I/O)
Reserved
32-bit connector start
CONNECTOR KEY
CONNECTOR KEY
Reserved
Ground
CLK
Ground
REQ#
+3.3V (I/O)
AD[31]
AD[29]
Ground
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
Ground
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
Ground
IRDY#
+3.3V
DEVSEL#
Ground
LOCK#
PERR#
+3.3V
SERR#
3.3 volt key
3.3 volt key
3.3Vaux
RST#
+3.3V (I/O)
GNT#
Ground
PME#
AD[30]
+3.3V
AD[28]
AD[26]
Ground
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
Ground
AD[18]
AD[16]
+3.3V
FRAME#
Ground
TRDY#
Ground
STOP#
+3.3V
Reserved*
Reserved*
Ground
7KLVSLQZDVXVHGLQSUHYLRXVYHUVLRQVRIWKLVVSHFLILFDWLRQDQGPD\KDYHEHHQEXVHGWRRWKHU
FRQQHFWRUVDQGSXOOHGXS7REHFRPSODLQWZLWKWKLVYHUVLRQRIWKHVSHFLILFDWLRQWKLVSLQPXVWEH
OHIWXQFRQQHFWHGHJQRWEXVHGRUSXOOHGXS
143
Revision 2.2
7DEOH3&,&RQQHFWRU3LQRXWFRQWLQXHG
5V System Environment
Pin
Side B
Side A
Side B
Side A
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
+3.3V
C/BE[1]#
AD[14]
Ground
AD[12]
AD[10]
Ground
PAR
AD[15]
+3.3V
AD[13]
AD[11]
Ground
AD[09]
+3.3V
C/BE[1]#
AD[14]
Ground
AD[12]
AD[10]
M66EN
Ground
Ground
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
Ground
AD[01]
+3.3V (I/O)
ACK64#
+5V
+5V
PAR
AD[15]
+3.3V
AD[13]
AD[11]
Ground
AD[09]
Ground
Ground
C/BE[0]#
+3.3V
AD[06]
AD[04]
Ground
AD[02]
AD[00]
+3.3V (I/O)
REQ64#
+5V
+5V
CONNECTOR KEY
CONNECTOR KEY
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
Ground
AD[01]
+5V (I/O)
ACK64#
+5V
+5V
C/BE[0]#
+3.3V
AD[06]
AD[04]
Ground
AD[02]
AD[00]
+5V (I/O)
REQ64#
+5V
+5V
CONNECTOR KEY
CONNECTOR KEY
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
144
3.3V System Environment
Reserved
Ground
C/BE[6]#
C/BE[4]#
Ground
AD[63]
AD[61]
+5V (I/O)
AD[59]
AD[57]
Ground
AD[55]
AD[53]
Ground
AD[51]
AD[49]
+5V (I/O)
AD[47]
AD[45]
Ground
Ground
C/BE[7]#
C/BE[5]#
+5V (I/O)
PAR64
AD[62]
Ground
AD[60]
AD[58]
Ground
AD[56]
AD[54]
+5V (I/O)
AD[52]
AD[50]
Ground
AD[48]
AD[46]
Ground
AD[44]
CONNECTOR KEY
CONNECTOR KEY
Reserved
Ground
C/BE[6]#
C/BE[4]#
Ground
AD[63]
AD[61]
+3.3V (I/O)
AD[59]
AD[57]
Ground
AD[55]
AD[53]
Ground
AD[51]
AD[49]
+3.3V (I/O)
AD[47]
AD[45]
Ground
Ground
C/BE[7]#
C/BE[5]#
+3.3V (I/O)
PAR64
AD[62]
Ground
AD[60]
AD[58]
Ground
AD[56]
AD[54]
+3.3V (I/O)
AD[52]
AD[50]
Ground
AD[48]
AD[46]
Ground
AD[44]
Comments
66 MHz / gnd
5 volt key
5 volt key
32-bit connector end
64-bit spacer
64-bit spacer
64-bit connector start
Revision 2.2
7DEOH3&,&RQQHFWRU3LQRXWFRQWLQXHG
5V System Environment
3.3V System Environment
Pin
Side B
Side A
Side B
Side A
83
84
85
86
87
88
89
90
91
92
93
94
AD[43]
AD[41]
Ground
AD[39]
AD[37]
+5V (I/O)
AD[35]
AD[33]
Ground
Reserved
Reserved
Ground
AD[42]
+5V (I/O)
AD[40]
AD[38]
Ground
AD[36]
AD[34]
Ground
AD[32]
Reserved
Ground
Reserved
AD[43]
AD[41]
Ground
AD[39]
AD[37]
+3.3V (I/O)
AD[35]
AD[33]
Ground
Reserved
Reserved
Ground
AD[42]
+3.3V (I/O)
AD[40]
AD[38]
Ground
AD[36]
AD[34]
Ground
AD[32]
Reserved
Ground
Reserved
Comments
64-bit connector end
3LQVODEHOHG9,2DQG9,2DUHVSHFLDOSRZHUSLQVIRUGHILQLQJDQGGULYLQJ
WKH3&,VLJQDOLQJUDLORQWKH8QLYHUVDO%RDUG2QWKHPRWKHUERDUGWKHVHSLQVDUH
FRQQHFWHGWRWKHPDLQ9RU9SODQHUHVSHFWLYHO\
5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUWKHFRQQHFWLRQRIREQ64#RQ
ELWRQO\H[SDQVLRQVORWFRQQHFWRUV
145
Revision 2.2
4.4. Expansion Board Specification
4.4.1. Board Pin Assignment
7KH3&,FRQQHFWRUFRQWDLQVDOOWKHVLJQDOVGHILQHGIRU3&,FRPSRQHQWVSOXVWZRSLQV
WKDWDUHUHODWHGWRWKHFRQQHFWRURQO\7KHVHDUHPRSNT1#DQGPRSNT2#7KH\DUH
XVHGIRUWZRSXUSRVHVLQGLFDWLQJWKDWDQH[SDQVLRQERDUGLVSK\VLFDOO\SUHVHQWLQWKH
VORWDQGSURYLGLQJLQIRUPDWLRQDERXWWKHWRWDOSRZHUUHTXLUHPHQWVRIWKHERDUG
7DEOHGHILQHVWKHUHTXLUHGVHWWLQJRIWKHPRSNT#SLQVIRUH[SDQVLRQERDUGV
7DEOH3UHVHQW6LJQDO'HILQLWLRQV
PRSNT1#
PRSNT2#
Expansion Configuration
Open
Open
No expansion board present
Ground
Open
Expansion board present, 25 W maximum
Open
Ground
Expansion board present, 15 W maximum
Ground
Ground
Expansion board present, 7.5 W maximum
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146
Revision 2.2
7DEOH3&,([SDQVLRQ%RDUG3LQRXW
5V Board
Universal Board
3.3V Board
Pin
Side B
Side A
Side B
Side A
Side B
Side A
Comments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
Ground
Ground
Reserved
Ground
CLK
Ground
REQ#
+5V
AD[31]
AD[29]
Ground
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
Ground
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
Ground
IRDY#
+3.3V
DEVSEL#
Ground
LOCK#
PERR#
+3.3V
SERR#
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+5V
Reserved
Ground
Ground
3.3Vaux
RST#
+5V
GNT#
Ground
PME#
AD[30]
+3.3V
AD[28]
AD[26]
Ground
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
Ground
AD[18]
AD[16]
+3.3V
FRAME#
Ground
TRDY#
Ground
STOP#
+3.3V
Reserved
Reserved
Ground
-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+VI/O
Reserved
-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+3.3V
Reserved
32-bit start
KEYWAY
KEYWAY
Reserved
Ground
CLK
Ground
REQ#
+VI/O
AD[31]
AD[29]
Ground
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
Ground
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
Ground
IRDY#
+3.3V
DEVSEL#
Ground
LOCK#
PERR#
+3.3V
SERR#
3.3Vaux
RST#
+VI/O
GNT#
Ground
PME#
AD[30]
+3.3V
AD[28]
AD[26]
Ground
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
Ground
AD[18]
AD[16]
+3.3V
FRAME#
Ground
TRDY#
Ground
STOP#
+3.3V
Reserved
Reserved
Ground
KEYWAY
KEYWAY
Reserved
Ground
CLK
Ground
REQ#
+3.3V
AD[31]
AD[29]
Ground
AD[27]
AD[25]
+3.3V
C/BE[3]#
AD[23]
Ground
AD[21]
AD[19]
+3.3V
AD[17]
C/BE[2]#
Ground
IRDY#
+3.3V
DEVSEL#
Ground
LOCK#
PERR#
+3.3V
SERR#
3.3V key
3.3V key
3.3Vaux
RST#
+3.3V
GNT#
Ground
PME#
AD[30]
+3.3V
AD[28]
AD[26]
Ground
AD[24]
IDSEL
+3.3V
AD[22]
AD[20]
Ground
AD[18]
AD[16]
+3.3V
FRAME#
Ground
TRDY#
Ground
STOP#
+3.3V
Reserved
Reserved
Ground
147
Revision 2.2
7DEOH3&,([SDQVLRQ%RDUG3LQRXWFRQWLQXHG
5V Board
Universal Board
3.3V Board
Pin
Side B
Side A
Side B
Side A
Side B
Side A
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
+3.3V
C/BE[1]#
AD[14]
Ground
AD[12]
AD[10]
Ground
PAR
AD[15]
+3.3V
AD[13]
AD[11]
Ground
AD[09]
+3.3V
C/BE[1]#
AD[14]
Ground
AD[12]
AD[10]
M66EN
PAR
AD[15]
+3.3V
AD[13]
AD[11]
Ground
AD[09]
+3.3V
C/BE[1]#
AD[14]
Ground
AD[12]
AD[10]
M66EN
Ground
Ground
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
Ground
AD[01]
+3.3V
ACK64#
+5V
+5V
PAR
AD[15]
+3.3V
AD[13]
AD[11]
Ground
AD[09]
Ground
Ground
C/BE[0]#
+3.3V
AD[06]
AD[04]
Ground
AD[02]
AD[00]
+3.3V
REQ64#
+5V
+5V
KEYWAY
KEYWAY
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
Ground
AD[01]
+5V
ACK64#
+5V
+5V
C/BE[0]#
+3.3V
AD[06]
AD[04]
Ground
AD[02]
AD[00]
+5V
REQ64#
+5V
+5V
KEYWAY
KEYWAY
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
148
Reserved
Ground
C/BE[6]#
C/BE[4]#
Ground
AD[63]
AD[61]
+5V
AD[59]
AD[57]
Ground
AD[55]
AD[53]
Ground
AD[51]
AD[49]
+5V
AD[47]
AD[45]
Ground
Ground
C/BE[7]#
C/BE[5]#
+5V
PAR64
AD[62]
Ground
AD[60]
AD[58]
Ground
AD[56]
AD[54]
+5V
AD[52]
AD[50]
Ground
AD[48]
AD[46]
Ground
AD[44]
KEYWAY
KEYWAY
AD[08]
AD[07]
+3.3V
AD[05]
AD[03]
Ground
AD[01]
+VI/O
ACK64#
+5V
+5V
C/BE[0]#
+3.3V
AD[06]
AD[04]
Ground
AD[02]
AD[00]
+VI/O
REQ64#
+5V
+5V
KEYWAY
KEYWAY
Reserved
Ground
C/BE[6]#
C/BE[4]#
Ground
AD[63]
AD[61]
+VI/O
AD[59]
AD[57]
Ground
AD[55]
AD[53]
Ground
AD[51]
AD[49]
+VI/O
AD[47]
AD[45]
Ground
Ground
C/BE[7]#
C/BE[5]#
+VI/O
PAR64
AD[62]
Ground
AD[60]
AD[58]
Ground
AD[56]
AD[54]
+VI/O
AD[52]
AD[50]
Ground
AD[48]
AD[46]
Ground
AD[44]
KEYWAY
KEYWAY
Reserved
Ground
C/BE[6]#
C/BE[4]#
Ground
AD[63]
AD[61]
+3.3V
AD[59]
AD[57]
Ground
AD[55]
AD[53]
Ground
AD[51]
AD[49]
+3.3V
AD[47]
AD[45]
Ground
Ground
C/BE[7]#
C/BE[5]#
+3.3V
PAR64
AD[62]
Ground
AD[60]
AD[58]
Ground
AD[56]
AD[54]
+3.3V
AD[52]
AD[50]
Ground
AD[48]
AD[46]
Ground
AD[44]
Comments
66 MHz /gnd
5V key
5V key
32-bit end
64-bit spacer
64-bit spacer
64-bit start
Revision 2.2
7DEOH3&,([SDQVLRQ%RDUG3LQRXWFRQWLQXHG
5V Board
Universal Board
3.3V Board
Pin
Side B
Side A
Side B
Side A
Side B
Side A
Comments
83
84
85
86
87
88
89
90
91
92
93
94
AD[43]
AD[41]
Ground
AD[39]
AD[37]
+5V
AD[35]
AD[33]
Ground
Reserved
Reserved
Ground
AD[42]
+5V
AD[40]
AD[38]
Ground
AD[36]
AD[34]
Ground
AD[32]
Reserved
Ground
Reserved
AD[43]
AD[41]
Ground
AD[39]
AD[37]
+VI/O
AD[35]
AD[33]
Ground
Reserved
Reserved
Ground
AD[42]
+VI/O
AD[40]
AD[38]
Ground
AD[36]
AD[34]
Ground
AD[32]
Reserved
Ground
Reserved
AD[43]
AD[41]
Ground
AD[39]
AD[37]
+3.3V
AD[35]
AD[33]
Ground
Reserved
Reserved
Ground
AD[42]
+3.3V
AD[40]
AD[38]
Ground
AD[36]
AD[34]
Ground
AD[32]
Reserved
Ground
Reserved
64-bit end
7DEOH3LQ6XPPDU\ELW([SDQVLRQ%RDUG
Pin Type
5V Board
Universal Board
3.3V Board
Ground
+5 V
+3.3 V
I/O pwr
Reserv’d
22
13
12
0
4
18 (Note)
8
12
5
4
22 (Note)
8
17
0
4
NOTE:
If the M66EN pin is implemented, the number of ground pins for a Universal
board is 17 and the number of ground pins for a 3.3V board is 21.
7DEOH3LQ6XPPDU\ELW%RDUGLQFUHPHQWDOSLQV
Pin Type
5V Board
Universal Board
3.3V Board
Ground
+5 V
+3.3 V
I/O pwr
Reserv’d
16
6
0
0
5
16
0
0
6
5
16
0
6
0
5
149
Revision 2.2
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UDLORQWKH8QLYHUVDO%RDUG2QWKLVERDUGWKH3&,FRPSRQHQW
V,2EXIIHUVPXVWEH
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SLQV
4.4.2. Power Requirements
4.4.2.1. Decoupling
8QGHUW\SLFDOFRQGLWLRQVWKH9FFSODQHWRJURXQGSODQHFDSDFLWDQFHZLOOSURYLGH
DGHTXDWHGHFRXSOLQJIRUWKH9FFFRQQHFWRUSLQV7KHPD[LPXPWUDFHOHQJWKIURPD
FRQQHFWRUSDGWRWKH9FF*1'SODQHYLDVKDOOEHLQFKHVDVVXPHVDPLOWUDFH
ZLGWK
+RZHYHURQWKH8QLYHUVDOERDUGLWLVOLNHO\WKDWWKH,2EXIIHUSRZHUUDLOZLOOQRWKDYH
DGHTXDWHFDSDFLWDQFHWRWKHJURXQGSODQHWRSURYLGHWKHQHFHVVDU\GHFRXSOLQJ3LQV
ODEHOHG9,2VKRXOGEHGHFRXSOHGWRJURXQGZLWKDQDYHUDJHRIµ)SHUSLQ
$GGLWLRQDOO\DOO9SLQVHYHQLIWKH\DUHQRWDFWXDOO\GHOLYHULQJSRZHUDQGDQ\
XQXVHG9DQG9,2SLQVRQWKH3&,HGJHFRQQHFWRUSURYLGHDQ$&UHWXUQSDWKDQG
PXVWKDYHSODWHGHGJHILQJHUVDQGEHFRXSOHGWRWKHJURXQGSODQHRQWKHH[SDQVLRQERDUG
DVGHVFULEHGEHORZWRHQVXUHWKH\FRQWLQXHWRIXQFWLRQDVHIILFLHQW$&UHIHUHQFHSRLQWV
7KHGHFRXSOLQJPXVWDYHUDJHDWOHDVWµ)KLJKVSHHGSHU9FFSLQ
7KHWUDFHOHQJWKIURPSLQSDGWRFDSDFLWRUSDGVKDOOEHQRJUHDWHUWKDQLQFKHV
XVLQJDWUDFHZLGWKRIDWOHDVWLQFKHV
7KHUHLVQROLPLWWRWKHQXPEHURISLQVWKDWFDQVKDUHWKHVDPHFDSDFLWRUSURYLGHG
WKDWUHTXLUHPHQWVDQGDUHPHW
4.4.2.2. Power Consumption
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SRZHUGUDZQIURPDOOSRZHUUDLOVSURYLGHGDWWKHFRQQHFWRU999,2 9
99DX[7KHH[SDQVLRQERDUGPD\RSWLRQDOO\GUDZDOOWKLVSRZHUIURPHLWKHU
WKH9RU9UDLO
,WLVDQWLFLSDWHGWKDWPDQ\V\VWHPVZLOOQRWSURYLGHDIXOOZDWWVSHUFRQQHFWRUIRUHDFK
SRZHUUDLOEHFDXVHPRVWERDUGVZLOOW\SLFDOO\GUDZPXFKOHVVWKDQWKLVDPRXQW)RUWKLV
UHDVRQLWLVUHFRPPHQGHGWKDW3&,ERDUGVWKDWFRQVXPHPRUHWKDQZDWWVSRZHUXSLQ
35
While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and
expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI component
of this type is used on the Universal Board, its I/O buffers may optionally be connected to the 3.3V rail
rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O"
designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V rail
with a simple diode must never be used in the 5V signaling environment.") Since the effective operation of
these high clamp diodes may be critical to both signal quality and device reliability, the designer must
provide enough extra "I/O" designated power pins on a component to handle the current spikes associated
with the 5V maximum AC waveforms (Section 4.2.1.3.).
150
Revision 2.2
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FDQEHVXVSHQGHGLIQHFHVVDU\7KLVSRZHUVDYLQJVWDWHFDQEHDFKLHYHGLQDYDULHW\RI
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SUREDEO\UHJLVWHUEDVHG,QDGYDQFHGSRZHUPDQDJHGV\VWHPVWKHGHYLFHGULYHUPD\
EHUHTXLUHGWRUHSRUWWKHWDUJHWSRZHUFRQVXPSWLRQEHIRUHIXOO\HQDEOLQJWKHERDUGLQ
RUGHUWRDOORZWKHV\VWHPWRGHWHUPLQHLILWKDVDVXIILFLHQWSRZHUEXGJHWIRUDOOERDUGVLQ
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V\VWHP¶VSRZHU,QVRPHFDVHVERDUGVFDSDEOHRI93&,VLJQDOLQJKDYHPXOWLSOH
PHFKDQLVPVWKDWLQGLUHFWO\VRXUFHSRZHUEDFNWRWKHV\VWHPDQGZLOOYLRODWHWKLV
UHTXLUHPHQWLIQRWSURSHUO\FRQWUROOHG)RUH[DPSOHERDUGVFRQWDLQLQJFRPSRQHQWVZLWK
EXVFODPSVWRWKH9UDLOPD\FUHDWHD³FKDUJHSXPS´ZKLFKGLUHFWVH[FHVVEXV
VZLWFKLQJHQHUJ\EDFNLQWRWKHV\VWHPERDUG$OWHUQDWHO\,2RXWSXWEXIIHUVRSHUDWLQJ
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4.4.3. Physical Requirements
4.4.3.1. Trace Length Limits
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151
Revision 2.2
4.4.3.2. Routing Recommendations for Four-Layer Expansion
Boards
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4.4.3.3. Impedance
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4.4.3.4. Signal Loading
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Chapter 5
Mechanical Specification
5.1. Overview
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36 It
is highly recommended that adapter card designers implement I/O brackets which mount on the
backside of PCI cards as soon as possible to reduce their exposure to causing EMC leakage in systems.
37 It
is highly recommended that system designers initiate requirements which include the use of this new
design by their adapter card suppliers.
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5.2.1. Connector Physical Description
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5.2.1.1. Connector Physical Requirements
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Part
176
Materials
Connector Housing
High-temperature thermoplastic, UL flammability rating
94V-0, color: white.
Contacts
Phosphor bronze.
Contact Finish
0.000030 inch minimum gold over 0.000050 inch
minimum nickel in the contact area. Alternate finish:
gold flash over 0.000040 inch (1 micron) minimum
palladium or palladium-nickel over nickel in the contact
area.
Revision 2.2
5.2.1.2. Connector Performance Specification
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Parameter
Specification
Durability
100 mating cycles without physical damage or
exceeding low level contact resistance requirement
when mated with the recommended card edge.
Mating Force
6 oz. (1.7N) max. avg. per opposing contact pair using
MIL-STD-1344, Method 2013.1 and gauge per
MIL-C-21097 with profile as shown in add-in board
specification.
Contact Normal Force
75 grams minimum.
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Parameter
Specification
Contact Resistance
(low signal level) 30 mΩ max. initial, 10 mΩ max.
increase through testing. Contact resistance, test per
MIL-STD-1344, Method 3002.1.
Insulation Resistance
1000 MΩ min. per MIL STD 202, Method 302,
Condition B.
Dielectric Withstand
Voltage
500 VAC RMS. per MIL-STD-1344, Method D3001.1
Condition 1.
Capacitance
2 pF max. @ 1 MHz.
Current Rating
1A, 30 °C rise above ambient.
Voltage Rating
125V.
Certification
UL Recognition and CSA Certification required.
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Parameter
Specification
Operating Temperature
-40 °C to 105 °C
Thermal Shock
-55 °C to 85 °C, 5 cycles per MIL-STD-1344, Method
1003.1.
Flowing Mixed Gas Test
Battelle, Class II. Connector mated with board and
tested per Battelle method.
177
Revision 2.2
5.2.2. Planar Implementation
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38
It is highly recommended that LPX system chassis designers utilize the PCI riser connector when
implementing riser cards on LPX systems and using adapter cards slots on 0.800” spacing.
39
It is highly recommended that LPX system chassis designers utilize the taller riser style of ISA and EISA
connectors when combining PCI and ISA/EISA.
181
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Revision 2.2
Chapter 6
Configuration Space
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40
The device dependent region contains device specific information and is not described in this document.
41
The PC Card Standard is available from PCMCIA and contact information can be found at
http://www.pc-card.com
190
Revision 2.2
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191
Revision 2.2
6.2. Configuration Space Functions
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6.2.1. Device Identification
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192
Vendor ID
This field identifies the manufacturer of the device. Valid
vendor identifiers are allocated by the PCI SIG to ensure
uniqueness. 0FFFFh is an invalid value for Vendor ID.
Device ID
This field identifies the particular device. This identifier is
allocated by the vendor.
Revision ID
This register specifies a device specific revision identifier.
The value is chosen by the vendor. Zero is an acceptable
value. This field should be viewed as a vendor defined
extension to the Device ID.
Header Type
This byte identifies the layout of the second part of the
predefined header (beginning at byte 10h in Configuration
Space) and also whether or not the device contains multiple
functions. Bit 7 in this register is used to identify a multifunction device. If the bit is 0, then the device is single
function. If the bit is 1, then the device has multiple
functions. Bits 6 through 0 identify the layout of the second
part of the predefined header. The encoding 00h specifies the
layout shown in Figure 6-1. The encoding 01h is defined for
PCI-to-PCI bridges and is defined in the document PCI to
PCI Bridge Architecture Specification. The encoding 02h is
defined for a CardBus bridge and is documented in the PC
Card Standard. All other encodings are reserved.
Revision 2.2
Class Code
The Class Code register is read-only and is used to identify
the generic function of the device and, in some cases, a
specific register-level programming interface. The register is
broken into three byte-size fields. The upper byte (at offset
0Bh) is a base class code which broadly classifies the type of
function the device performs. The middle byte (at offset 0Ah)
is a sub-class code which identifies more specifically the
function of the device. The lower byte (at offset 09h)
identifies a specific register-level programming interface (if
any) so that device independent software can interact with the
device. Encodings for base class, sub-class, and programming
interface are provided in Appendix D. All unspecified
encodings are reserved.
6.2.2. Device Control
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15
10 9
8
7
6
5
4
3
2
1
0
Reserved
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193
Revision 2.2
7DEOH&RPPDQG5HJLVWHU%LWV
Bit Location
194
Description
0
Controls a device’s response to I/O Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
respond to I/O Space accesses. State after RST# is 0.
1
Controls a device’s response to Memory Space accesses. A value of
0 disables the device response. A value of 1 allows the device to
respond to Memory Space accesses. State after RST# is 0.
2
Controls a device’s ability to act as a master on the PCI bus. A value
of 0 disables the device from generating PCI accesses. A value of 1
allows the device to behave as a bus master. State after RST# is 0.
3
Controls a device’s action on Special Cycle operations. A value of 0
causes the device to ignore all Special Cycle operations. A value of 1
allows the device to monitor Special Cycle operations. State after
RST# is 0.
4
This is an enable bit for using the Memory Write and Invalidate
command. When this bit is 1, masters may generate the command.
When it is 0, Memory Write must be used instead. State after RST# is
0. This bit must be implemented by master devices that can generate
the Memory Write and Invalidate command.
5
This bit controls how VGA compatible and graphics devices handle
accesses to VGA palette registers. When this bit is 1, palette
snooping is enabled (i.e., the device does not respond to palette
register writes and snoops the data). When the bit is 0, the device
should treat palette write accesses like all other accesses. VGA
compatible devices should implement this bit. Refer to Section 3.10.
for more details on VGA palette snooping.
Revision 2.2
7DEOH&RPPDQG5HJLVWHU%LWVFRQWLQXHG
Bit Location
Description
6
This bit controls the device’s response to parity errors. When the bit is
set, the device must take its normal action when a parity error is
detected. When the bit is 0, the device sets its Detected Parity Error
status bit (bit 15 in the Status register) when an error is detected, but
does not assert PERR# and continues normal operation. This bit’s
state after RST# is 0. Devices that check parity must implement this
bit. Devices are still required to generate parity even if parity checking
is disabled.
7
This bit is used to control whether or not a device does address/data
stepping. Devices that never do stepping must hardwire this bit to 0.
Devices that always do stepping must hardwire this bit to 1. Devices
that can do either, must make this bit read/write and have it initialize to
1 after RST#.
8
This bit is an enable bit for the SERR# driver. A value of 0 disables
the SERR# driver. A value of 1 enables the SERR# driver. This bit’s
state after RST# is 0. All devices that have an SERR# pin must
implement this bit. Address parity errors are reported only if this bit
and bit 6 are 1.
9
This optional read/write bit controls whether or not a master can do
fast back-to-back transactions to different devices. Initialization
software will set the bit if all targets are fast back-to-back capable. A
value of 1 means the master is allowed to generate fast back-to-back
transactions to different agents as described in Section 3.4.2. A value
of 0 means fast back-to-back transactions are only allowed to the
same agent. This bit’s state after RST# is 0.
10-15
Reserved.
195
Revision 2.2
6.2.3. Device Status
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15 14 13 12 11 10 9 8
7
6
5
4
0
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Capabilities List
66 MHz Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
DEVSEL timing
00 - fast
01 - medium
10 - slow
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
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196
Revision 2.2
7DEOH6WDWXV5HJLVWHU%LWV
Bit Location
0-3
Description
Reserved.
4
This optional read-only bit indicates whether or not this device
implements the pointer for a New Capabilities linked list at offset 34h.
A value of zero indicates that no New Capabilities linked list is
available. A value of one indicates that the value read at offset 34h is a
pointer in Configuration Space to a linked list of new capabilities. Refer
to Section 6.7. for details on New Capabilities.
5
This optional read-only bit indicates whether or not this device is
capable of running at 66 MHz as defined in Chapter 7. A value of zero
indicates 33 MHz. A value of 1 indicates that the device is 66 MHz
capable.
6
This bit is reserved42.
7
This optional read-only bit indicates whether or not the target is
capable of accepting fast back-to-back transactions when the
transactions are not to the same agent. This bit can be set to 1 if the
device can accept these transactions and must be set to 0 otherwise.
Refer to Section 3.4.2. for a complete description of requirements for
setting this bit.
8
This bit is only implemented by bus masters. It is set when three
conditions are met: 1) the bus agent asserted PERR# itself (on a read)
or observed PERR# asserted (on a write); 2) the agent setting the bit
acted as the bus master for the operation in which the error occurred;
and 3) the Parity Error Response bit (Command register) is set.
9-10
These bits encode the timing of DEVSEL#. Section 3.6.1. specifies
three allowable timings for assertion of DEVSEL#. These are
encoded as 00b for fast, 01b for medium, and 10b for slow (11b is
reserved). These bits are read-only and must indicate the slowest time
that a device asserts DEVSEL# for any bus command except
Configuration Read and Configuration Write.
42
In Revision 2.1 of this specification, this bit was used to indicate whether or not a device supported User
Definable Features.
197
Revision 2.2
7DEOH6WDWXV5HJLVWHU%LWVFRQWLQXHG
Bit Location
Description
11
This bit must be set by a target device whenever it terminates a
transaction with Target-Abort. Devices that will never signal TargetAbort do not need to implement this bit.
12
This bit must be set by a master device whenever its transaction is
terminated with Target-Abort. All master devices must implement this
bit.
13
This bit must be set by a master device whenever its transaction
(except for Special Cycle) is terminated with Master-Abort. All master
devices must implement this bit.
14
This bit must be set whenever the device asserts SERR#. Devices
who will never assert SERR# do not need to implement this bit.
15
This bit must be set by the device whenever it detects a parity error,
even if parity error handling is disabled (as controlled by bit 6 in the
Command register).
6.2.4. Miscellaneous Registers
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198
Revision 2.2
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0
Rsvd
Start BIST
BIST capable
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Bit Location
Description
7
Return 1 if device supports BIST. Return 0 if the device is not BIST
capable.
6
Write a 1 to invoke BIST. Device resets the bit when BIST is complete.
Software should fail the device if BIST is not complete after 2 seconds.
5-4
Reserved. Device returns 0.
3-0
A value of 0 means the device has passed its test. Non-zero values
mean the device failed. Device-specific failure codes can be encoded
in the non-zero value.
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199
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43
For x86 based PCs, the values in this register correspond to IRQ numbers (0-15) of the standard dual
8259 configuration. The value 255 is defined as meaning "unknown" or "no connection" to the interrupt
controller. Values between 15 and 254 are reserved.
200
Revision 2.2
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9DOXHVLQWKHVHUHJLVWHUVPXVWEHORDGHGDQGYDOLGSULRUWRWKHV\VWHP%,26RUDQ\
V\VWHPVRIWZDUHDFFHVVLQJWKH3&,&RQILJXUDWLRQ6SDFH+RZWKHVHYDOXHVDUHORDGHGLV
QRWVSHFLILHGEXWFRXOGEHGRQHGXULQJWKHPDQXIDFWXULQJSURFHVVRUORDGHGIURP
H[WHUQDOORJLFHJVWUDSSLQJRSWLRQVVHULDO520VHWF7KHVHYDOXHVPXVWQRWEH
ORDGHGXVLQJH[SDQVLRQ520VRIWZDUHEHFDXVHH[SDQVLRQ520VRIWZDUHLVQRW
JXDUDQWHHGWREHUXQGXULQJ3267LQDOOV\VWHPV'HYLFHVDUHUHVSRQVLEOHIRU
JXDUDQWHHLQJWKHGDWDLVYDOLGEHIRUHDOORZLQJUHDGVWRWKHVHUHJLVWHUVWRFRPSOHWH7KLV
FDQEHGRQHE\UHVSRQGLQJWRDQ\DFFHVVHVZLWK5HWU\XQWLOWKHGDWDLVYDOLG
,IDGHYLFHLVGHVLJQHGWREHXVHGH[FOXVLYHO\RQWKHPRWKHUERDUGWKHV\VWHPYHQGRUPD\
XVHV\VWHPVSHFLILFVRIWZDUHWRLQLWLDOL]HWKHVHUHJLVWHUVDIWHUHDFKSRZHURQ
&DSDELOLWLHV3RLQWHU
7KLVRSWLRQDOUHJLVWHULVXVHGWRSRLQWWRDOLQNHGOLVWRIQHZFDSDELOLWLHVLPSOHPHQWHGE\
WKLVGHYLFH7KLVUHJLVWHULVRQO\YDOLGLIWKH³&DSDELOLWLHV/LVW´ELWLQWKH6WDWXV5HJLVWHU
LVVHW,ILPSOHPHQWHGWKHERWWRPWZRELWVDUHUHVHUYHGDQGVKRXOGEHVHWWRE
6RIWZDUHVKRXOGPDVNWKHVHELWVRIIEHIRUHXVLQJWKLVUHJLVWHUDVDSRLQWHULQ
&RQILJXUDWLRQ6SDFHWRWKHILUVWHQWU\RIDOLQNHGOLVWRIQHZFDSDELOLWLHV5HIHUWR
6HFWLRQIRUDGHVFULSWLRQRIWKLVGDWDVWUXFWXUH
6.2.5. Base Addresses
2QHRIWKHPRVWLPSRUWDQWIXQFWLRQVIRUHQDEOLQJVXSHULRUFRQILJXUDELOLW\DQGHDVHRIXVH
LVWKHDELOLW\WRUHORFDWH3&,GHYLFHVLQWKHDGGUHVVVSDFHV$WV\VWHPSRZHUXSGHYLFH
LQGHSHQGHQWVRIWZDUHPXVWEHDEOHWRGHWHUPLQHZKDWGHYLFHVDUHSUHVHQWEXLOGD
FRQVLVWHQWDGGUHVVPDSDQGGHWHUPLQHLIDGHYLFHKDVDQH[SDQVLRQ520(DFKRIWKHVH
DUHDVLVFRYHUHGLQWKHIROORZLQJVHFWLRQV
6.2.5.1. Address Maps
3RZHUXSVRIWZDUHQHHGVWREXLOGDFRQVLVWHQWDGGUHVVPDSEHIRUHERRWLQJWKHPDFKLQH
WRDQRSHUDWLQJV\VWHP7KLVPHDQVLWKDVWRGHWHUPLQHKRZPXFKPHPRU\LVLQWKH
V\VWHPDQGKRZPXFKDGGUHVVVSDFHWKH,2FRQWUROOHUVLQWKHV\VWHPUHTXLUH$IWHU
GHWHUPLQLQJWKLVLQIRUPDWLRQSRZHUXSVRIWZDUHFDQPDSWKH,2FRQWUROOHUVLQWR
UHDVRQDEOHORFDWLRQVDQGSURFHHGZLWKV\VWHPERRW,QRUGHUWRGRWKLVPDSSLQJLQD
GHYLFHLQGHSHQGHQWPDQQHUWKHEDVHUHJLVWHUVIRUWKLVPDSSLQJDUHSODFHGLQWKH
SUHGHILQHGKHDGHUSRUWLRQRI&RQILJXUDWLRQ6SDFH
%LWLQDOO%DVH$GGUHVVUHJLVWHUVLVUHDGRQO\DQGXVHGWRGHWHUPLQHZKHWKHUWKH
UHJLVWHUPDSVLQWR0HPRU\RU,26SDFH%DVH$GGUHVVUHJLVWHUVWKDWPDSWR0HPRU\
44
A company has only one Vendor ID. That value can be used in either the Vendor ID field of
configuration space (offset 00h) or the Subsystem Vendor ID field of configuration space (offset 2Ch). It is
used in the Vendor ID field (offset 00h) if the company built the silicon. It is used in the Subsystem Vendor
ID field (offset 2Ch) if the company built the add-in card. If a company builds both the silicon and the addin card, then the same value would be used in both fields.
201
Revision 2.2
6SDFHPXVWUHWXUQDLQELWVHH)LJXUH%DVH$GGUHVVUHJLVWHUVWKDWPDSWR,2
6SDFHPXVWUHWXUQDLQELWVHH)LJXUH
)LJXUH%DVH$GGUHVV5HJLVWHUIRU0HPRU\
31
2 1 0
Base Address
0 1
Reserved
IO space indicator
)LJXUH%DVH$GGUHVV5HJLVWHUIRU,2
%DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR,26SDFHDUHDOZD\VELWVZLGHZLWKELW
KDUGZLUHGWRD%LWLVUHVHUYHGDQGPXVWUHWXUQRQUHDGVDQGWKHRWKHUELWVDUHXVHG
WRPDSWKHGHYLFHLQWR,26SDFH
%DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR0HPRU\6SDFHFDQEHELWVRUELWVZLGHWR
VXSSRUWPDSSLQJLQWRDELWDGGUHVVVSDFHZLWKELWKDUGZLUHGWRD)RU0HPRU\
%DVH$GGUHVVUHJLVWHUVELWVDQGKDYHDQHQFRGHGPHDQLQJDVVKRZQLQ7DEOH
%LWVKRXOGEHVHWWRLIWKHGDWDLVSUHIHWFKDEOHDQGUHVHWWRRWKHUZLVH$GHYLFHFDQ
PDUNDUDQJHDVSUHIHWFKDEOHLIWKHUHDUHQRVLGHHIIHFWVRQUHDGVWKHGHYLFHUHWXUQVDOO
E\WHVRQUHDGVUHJDUGOHVVRIWKHE\WHHQDEOHVDQGKRVWEULGJHVFDQPHUJHSURFHVVRU
ZULWHVUHIHUWR6HFWLRQLQWRWKLVUDQJHZLWKRXWFDXVLQJHUURUV%LWVDUHUHDG
RQO\
45
Any device that has a range that behaves like normal memory should mark the range as prefetchable. A
linear frame buffer in a graphics device is an example of a range that should be marked prefetchable.
202
Revision 2.2
7DEOH0HPRU\%DVH$GGUHVV5HJLVWHU%LWV(QFRGLQJ
Bits 2/1
Meaning
00
Base register is 32 bits wide and mapping can be
done anywhere in the 32-bit Memory Space.
01
Reserved46
10
Base register is 64 bits wide and can be mapped
anywhere in the 64-bit address space.
11
Reserved
7KHQXPEHURIXSSHUELWVWKDWDGHYLFHDFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKRIWKH
DGGUHVVVSDFHWKHGHYLFHZLOOUHVSRQGWR$ELWUHJLVWHUFDQEHLPSOHPHQWHGWR
VXSSRUWDVLQJOHPHPRU\VL]HWKDWLVDSRZHURIIURPE\WHVWR*%$GHYLFHWKDW
ZDQWVD0%PHPRU\DGGUHVVVSDFHXVLQJDELWEDVHDGGUHVVUHJLVWHUZRXOGEXLOG
WKHWRSELWVRIWKHDGGUHVVUHJLVWHUKDUGZLULQJWKHRWKHUELWVWR
3RZHUXSVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHVE\ZULWLQJ
DYDOXHRIDOO
VWRWKHUHJLVWHUDQGWKHQUHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQ
VLQDOOGRQ
WFDUHDGGUHVVELWVHIIHFWLYHO\VSHFLI\LQJWKHDGGUHVVVSDFHUHTXLUHG
8QLPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVDUHKDUGZLUHGWR]HUR
7KLVGHVLJQLPSOLHVWKDWDOODGGUHVVVSDFHVXVHGDUHDSRZHURIWZRLQVL]HDQGDUH
QDWXUDOO\DOLJQHG'HYLFHVDUHIUHHWRFRQVXPHPRUHDGGUHVVVSDFHWKDQUHTXLUHGEXW
GHFRGLQJGRZQWRD.%VSDFHIRUPHPRU\LVVXJJHVWHGIRUGHYLFHVWKDWQHHGOHVVWKDQ
WKDWDPRXQW)RULQVWDQFHDGHYLFHWKDWKDVE\WHVRIUHJLVWHUVWREHPDSSHGLQWR
0HPRU\6SDFHPD\FRQVXPHXSWR.%RIDGGUHVVVSDFHLQRUGHUWRPLQLPL]HWKH
QXPEHURIELWVLQWKHDGGUHVVGHFRGHU'HYLFHVWKDWGRFRQVXPHPRUHDGGUHVVVSDFHWKDQ
WKH\XVHDUHQRWUHTXLUHGWRUHVSRQGWRWKHXQXVHGSRUWLRQRIWKDWDGGUHVVVSDFH'HYLFHV
WKDWPDSFRQWUROIXQFWLRQVLQWR,26SDFHPXVWQRWFRQVXPHPRUHWKDQE\WHVSHU,2
%DVH$GGUHVVUHJLVWHU7KHXSSHUELWVRIWKH,2%DVH$GGUHVVUHJLVWHUPD\EH
KDUGZLUHGWR]HURIRUGHYLFHVLQWHQGHGIRUELW,2V\VWHPVVXFKDV3&FRPSDWLEOHV
+RZHYHUDIXOOELWGHFRGHRI,2DGGUHVVHVPXVWVWLOOEHGRQH
46
The encoding to support memory space below 1M was supported in previous versions of the
specification. System software should recognize this encoding and handle appropriately.
203
Revision 2.2
Implementation Note: Sizing a 32 bit Base Address Register
Example
'HFRGH,2RUPHPRU\RIDUHJLVWHULVGLVDEOHGYLDWKHFRPPDQGUHJLVWHUEHIRUHVL]LQJ
D%DVH$GGUHVVUHJLVWHU6RIWZDUHVDYHVWKHRULJLQDOYDOXHRIWKH%DVH$GGUHVVUHJLVWHU
ZULWHV))))))))KWRWKHUHJLVWHUWKHQUHDGVLWEDFN6L]HFDOFXODWLRQFDQEHGRQHIURP
WKHELWYDOXHUHDGE\ILUVWFOHDULQJHQFRGLQJLQIRUPDWLRQELWVELWIRU,2ELWVIRU
PHPRU\LQYHUWLQJDOOELWVORJLFDO127WKHQLQFUHPHQWLQJE\7KHUHVXOWDQW
ELWYDOXHLVWKHPHPRU\,2UDQJHVL]HGHFRGHGE\WKHUHJLVWHU1RWHWKDWWKHXSSHU
ELWVRIWKHUHVXOWLVLJQRUHGLIWKH%DVH$GGUHVVUHJLVWHULVIRU,2DQGELWVUHWXUQHG
]HURXSRQUHDG7KHRULJLQDOYDOXHLQWKH%DVH$GGUHVVUHJLVWHULVUHVWRUHGEHIRUHUH
HQDEOLQJGHFRGHLQWKHFRPPDQGUHJLVWHURIWKHGHYLFH
ELWPHPRU\%DVH$GGUHVVUHJLVWHUVFDQEHKDQGOHGWKHVDPHH[FHSWWKDWWKHVHFRQG
ELWUHJLVWHULVFRQVLGHUHGDQH[WHQVLRQRIWKHILUVWLHELWV6RIWZDUHZULWHV
))))))))KWRERWKUHJLVWHUVUHDGVWKHPEDFNDQGFRPELQHVWKHUHVXOWLQWRDELW
YDOXH6L]HFDOFXODWLRQLVGRQHRQWKHELWYDOXH
$W\SHKSUHGHILQHGKHDGHUKDVVL[':25'ORFDWLRQVDOORFDWHGIRU%DVH$GGUHVV
UHJLVWHUVVWDUWLQJDWRIIVHWKLQ&RQILJXUDWLRQ6SDFH$GHYLFHPD\XVHDQ\RIWKH
ORFDWLRQVWRLPSOHPHQW%DVH$GGUHVVUHJLVWHUV$QLPSOHPHQWHGELW%DVH$GGUHVV
UHJLVWHUFRQVXPHVWZRFRQVHFXWLYH':25'ORFDWLRQV6RIWZDUHORRNLQJIRU
LPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVPXVWVWDUWDWRIIVHWKDQGFRQWLQXHXSZDUGV
WKURXJKRIIVHWK$W\SLFDOGHYLFHZLOOUHTXLUHRQHPHPRU\UDQJHIRULWVFRQWURO
IXQFWLRQV6RPHJUDSKLFVGHYLFHVPD\XVHWZRUDQJHVRQHIRUFRQWUROIXQFWLRQVDQG
DQRWKHUIRUDIUDPHEXIIHU$GHYLFHWKDWZDQWVWRPDSFRQWUROIXQFWLRQVLQWRERWK
PHPRU\DQG,26SDFHVDWWKHVDPHWLPHPXVWLPSOHPHQWWZR%DVH$GGUHVVUHJLVWHUV
RQHPHPRU\DQGRQH,27KHGULYHUIRUWKDWGHYLFHPLJKWRQO\XVHRQHVSDFHLQZKLFK
FDVHWKHRWKHUVSDFHZLOOEHXQXVHG'HYLFHVDUHUHFRPPHQGHGDOZD\VWRPDSFRQWURO
IXQFWLRQVLQWR0HPRU\6SDFH
6.2.5.2. Expansion ROM Base Address Register
6RPH3&,GHYLFHVHVSHFLDOO\WKRVHWKDWDUHLQWHQGHGIRUXVHRQH[SDQVLRQERDUGVLQ3&
DUFKLWHFWXUHVUHTXLUHORFDO(3520VIRUH[SDQVLRQ520UHIHUWR6HFWLRQIRUD
GHILQLWLRQRI520FRQWHQWV7KHIRXUE\WHUHJLVWHUDWRIIVHWKLQDW\SHK
SUHGHILQHGKHDGHULVGHILQHGWRKDQGOHWKHEDVHDGGUHVVDQGVL]HLQIRUPDWLRQIRUWKLV
H[SDQVLRQ520)LJXUHVKRZVKRZWKLVZRUGLVRUJDQL]HG7KHUHJLVWHUIXQFWLRQV
H[DFWO\OLNHDELW%DVH$GGUHVVUHJLVWHUH[FHSWWKDWWKHHQFRGLQJDQGXVDJHRIWKH
ERWWRPELWVLVGLIIHUHQW7KHXSSHUELWVFRUUHVSRQGWRWKHXSSHUELWVRIWKH
([SDQVLRQ520EDVHDGGUHVV7KHQXPEHURIELWVRXWRIWKHVHWKDWDGHYLFH
DFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHV)RU
LQVWDQFHDGHYLFHWKDWUHTXLUHVD.%DUHDWRPDSLWVH[SDQVLRQ520ZRXOG
LPSOHPHQWWKHWRSELWVLQWKHUHJLVWHUOHDYLQJWKHERWWRPRXWRIWKHVH
KDUGZLUHGWR'HYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWLPSOHPHQWWKLVUHJLVWHU
'HYLFHLQGHSHQGHQWFRQILJXUDWLRQVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKH
GHYLFHUHTXLUHVE\ZULWLQJDYDOXHRIDOO
VWRWKHDGGUHVVSRUWLRQRIWKHUHJLVWHUDQGWKHQ
UHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQ
VLQDOOGRQ
WFDUHELWVHIIHFWLYHO\
VSHFLI\LQJWKHVL]HDQGDOLJQPHQWUHTXLUHPHQWV7KHDPRXQWRIDGGUHVVVSDFHDGHYLFH
UHTXHVWVPXVWQRWEHJUHDWHUWKDQ0%
204
Revision 2.2
31
1 0
11 10
Expansion ROM Base Address
(Upper 21 bits)
Reserved
Expansion ROM Enable
)LJXUH([SDQVLRQ520%DVH$GGUHVV5HJLVWHU/D\RXW
%LWLQWKHUHJLVWHULVXVHGWRFRQWUROZKHWKHURUQRWWKHGHYLFHDFFHSWVDFFHVVHVWRLWV
H[SDQVLRQ520:KHQWKLVELWLVWKHGHYLFH¶VH[SDQVLRQ520DGGUHVVVSDFHLV
GLVDEOHG:KHQWKHELWLVDGGUHVVGHFRGLQJLVHQDEOHGXVLQJWKHSDUDPHWHUVLQWKH
RWKHUSDUWRIWKHEDVHUHJLVWHU7KLVDOORZVDGHYLFHWREHXVHGZLWKRUZLWKRXWDQ
H[SDQVLRQ520GHSHQGLQJRQV\VWHPFRQILJXUDWLRQ7KH0HPRU\6SDFHELWLQWKH
&RPPDQGUHJLVWHUKDVSUHFHGHQFHRYHUWKH([SDQVLRQ520HQDEOHELW$GHYLFHPXVW
UHVSRQGWRDFFHVVHVWRLWVH[SDQVLRQ520RQO\LIERWKWKH0HPRU\6SDFHELWDQGWKH
([SDQVLRQ520%DVH$GGUHVV(QDEOHELWDUHVHWWR7KLVELW
VVWDWHDIWHURST#LV
,QRUGHUWRPLQLPL]HWKHQXPEHURIDGGUHVVGHFRGHUVQHHGHGDGHYLFHPD\VKDUHD
GHFRGHUEHWZHHQWKH([SDQVLRQ520%DVH$GGUHVVUHJLVWHUDQGRWKHU%DVH$GGUHVV
UHJLVWHUV:KHQH[SDQVLRQ520GHFRGHLVHQDEOHGWKHGHFRGHULVXVHGIRUDFFHVVHVWR
WKHH[SDQVLRQ520DQGGHYLFHLQGHSHQGHQWVRIWZDUHPXVWQRWDFFHVVWKHGHYLFHWKURXJK
DQ\RWKHU%DVH$GGUHVVUHJLVWHUV
6.3. PCI Expansion ROMs
7KH3&,VSHFLILFDWLRQSURYLGHVDPHFKDQLVPZKHUHGHYLFHVFDQSURYLGHH[SDQVLRQ520
FRGHWKDWFDQEHH[HFXWHGIRUGHYLFHVSHFLILFLQLWLDOL]DWLRQDQGSRVVLEO\DV\VWHPERRW
IXQFWLRQUHIHUWR6HFWLRQ7KHPHFKDQLVPDOORZVWKH520WRFRQWDLQVHYHUDO
GLIIHUHQWLPDJHVWRDFFRPPRGDWHGLIIHUHQWPDFKLQHDQGSURFHVVRUDUFKLWHFWXUHV7KLV
VHFWLRQVSHFLILHVWKHUHTXLUHGLQIRUPDWLRQDQGOD\RXWRIFRGHLPDJHVLQWKHH[SDQVLRQ
5201RWHWKDW3&,GHYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWDOORZWKDW520WR
EHDFFHVVHGZLWKDQ\FRPELQDWLRQRIE\WHHQDEOHV7KLVVSHFLILFDOO\PHDQVWKDW
':25'DFFHVVHVWRWKHH[SDQVLRQ520PXVWEHVXSSRUWHG
7KHLQIRUPDWLRQLQWKH520VLVODLGRXWWREHFRPSDWLEOHZLWKH[LVWLQJ,QWHO[
([SDQVLRQ520KHDGHUVIRU,6$(,6$DQG0&DGDSWHUVEXWLWZLOODOVRVXSSRUWRWKHU
PDFKLQHDUFKLWHFWXUHV7KHLQIRUPDWLRQDYDLODEOHLQWKHKHDGHUKDVEHHQH[WHQGHGVRWKDW
PRUHRSWLPXPXVHFDQEHPDGHRIWKHIXQFWLRQSURYLGHGE\WKHDGDSWHUDQGVRWKDWWKH
PLQLPXPDPRXQWRI0HPRU\6SDFHLVXVHGE\WKHUXQWLPHSRUWLRQRIWKHH[SDQVLRQ
520FRGH
7KH3&,([SDQVLRQ520KHDGHULQIRUPDWLRQVXSSRUWVWKHIROORZLQJIXQFWLRQV
•
$OHQJWKFRGHLVSURYLGHGWRLGHQWLI\WKHWRWDOFRQWLJXRXVDGGUHVVVSDFHQHHGHGE\
WKH3&,GHYLFH520LPDJHDWLQLWLDOL]DWLRQ
•
$QLQGLFDWRULGHQWLILHVWKHW\SHRIH[HFXWDEOHRULQWHUSUHWLYHFRGHWKDWH[LVWVLQWKH
520DGGUHVVVSDFHLQHDFK520LPDJH
•
$UHYLVLRQOHYHOIRUWKHFRGHDQGGDWDRQWKH520LVSURYLGHG
•
7KH9HQGRU,'DQG'HYLFH,'RIWKHVXSSRUWHG3&,GHYLFHDUHLQFOXGHGLQWKH520
47Note
that it is the address decoder that is shared, not the registers themselves. The Expansion ROM Base
Address register and other Base Address registers must be able to hold unique values at the same time.
205
Revision 2.2
2QHPDMRUGLIIHUHQFHLQWKHXVDJHPRGHOEHWZHHQ3&,H[SDQVLRQ520VDQGVWDQGDUG
,6$(,6$DQG0&520VLVWKDWWKH520FRGHLVQHYHUH[HFXWHGLQSODFH,WLVDOZD\V
FRSLHGIURPWKH520GHYLFHWR5$0DQGH[HFXWHGIURP5$07KLVHQDEOHVG\QDPLF
VL]LQJRIWKHFRGHIRULQLWLDOL]DWLRQDQGUXQWLPHDQGSURYLGHVVSHHGLPSURYHPHQWVZKHQ
H[HFXWLQJUXQWLPHFRGH
6.3.1. PCI Expansion ROM Contents
3&,GHYLFHH[SDQVLRQ520VPD\FRQWDLQFRGHH[HFXWDEOHRULQWHUSUHWLYHIRUPXOWLSOH
SURFHVVRUDUFKLWHFWXUHV7KLVPD\EHLPSOHPHQWHGLQDVLQJOHSK\VLFDO520ZKLFKFDQ
FRQWDLQDVPDQ\FRGHLPDJHVDVGHVLUHGIRUGLIIHUHQWV\VWHPDQGSURFHVVRUDUFKLWHFWXUHV
VHH)LJXUH(DFKLPDJHPXVWVWDUWRQDE\WHERXQGDU\DQGPXVWFRQWDLQWKH
3&,H[SDQVLRQ520KHDGHU7KHVWDUWLQJSRLQWRIHDFKLPDJHGHSHQGVRQWKHVL]HRI
SUHYLRXVLPDJHV7KHODVWLPDJHLQD520KDVDVSHFLDOHQFRGLQJLQWKHKHDGHUWR
LGHQWLI\LWDVWKHODVWLPDJH
Image 0
Image 1
Image N
)LJXUH3&,([SDQVLRQ5206WUXFWXUH
6.3.1.1. PCI Expansion ROM Header Format
7KHLQIRUPDWLRQUHTXLUHGLQHDFK520LPDJHLVVSOLWLQWRWZRGLIIHUHQWDUHDV2QHDUHD
WKH520KHDGHULVUHTXLUHGWREHORFDWHGDWWKHEHJLQQLQJRIWKH520LPDJH7KH
VHFRQGDUHDWKH3&,'DWD6WUXFWXUHPXVWEHORFDWHGLQWKHILUVW.%RIWKHLPDJH
7KHIRUPDWIRUWKH3&,([SDQVLRQ520+HDGHULVJLYHQEHORZ7KHRIIVHWLVD
KH[DGHFLPDOQXPEHUIURPWKHEHJLQQLQJRIWKHLPDJHDQGWKHOHQJWKRIHDFKILHOGLV
JLYHQLQE\WHV
([WHQVLRQVWRWKH3&,([SDQVLRQ520+HDGHUDQGRUWKH3&,'DWD6WUXFWXUHPD\EH
GHILQHGE\VSHFLILFV\VWHPDUFKLWHFWXUHV([WHQVLRQVIRU3&$7FRPSDWLEOHV\VWHPVDUH
GHVFULEHGLQ6HFWLRQ
206
Revision 2.2
Offset
0h
1h
2h-17h
18h-19h
Length
1
1
16h
2
Value
55h
AAh
xx
xx
Description
ROM Signature, byte 1
ROM Signature, byte 2
Reserved (processor architecture unique data)
Pointer to PCI Data Structure
ROM Signature
The ROM Signature is a two-byte field containing a 55h in
the first byte and AAh in the second byte. This signature
must be the first two bytes of the ROM address space for
each image of the ROM.
Pointer to PCI Data
Structure
The Pointer to the PCI Data Structure is a two-byte pointer in
little endian format that points to the PCI Data Structure. The
reference point for this pointer is the beginning of the ROM
image.
6.3.1.2. PCI Data Structure Format
7KH3&,'DWD6WUXFWXUHPXVWEHORFDWHGZLWKLQWKHILUVW.%RIWKH520LPDJHDQG
PXVWEH':25'DOLJQHG7KH3&,'DWD6WUXFWXUHFRQWDLQVWKHIROORZLQJLQIRUPDWLRQ
Offset
0
4
6
8
A
C
D
10
12
14
15
16
Length
4
2
2
2
2
1
3
2
2
1
1
2
Description
Signature, the string "PCIR"
Vendor Identification
Device Identification
Reserved
PCI Data Structure Length
PCI Data Structure Revision
Class Code
Image Length
Revision Level of Code/Data
Code Type
Indicator
Reserved
Signature
These four bytes provide a unique signature for the PCI Data
Structure. The string "PCIR" is the signature with "P" being
at offset 0, "C" at offset 1, etc.
Vendor Identification
The Vendor Identification field is a 16-bit field with the same
definition as the Vendor Identification field in the
Configuration Space for this device.
Device Identification
The Device Identification field is a 16-bit field with the same
definition as the Device Identification field in the
Configuration Space for this device.
207
Revision 2.2
Resvd
Reserved 16-bit field.
Note that in earlier versions of the PCI Local Bus
Specification this field pointed to ROM located Vital Product
Data. This has been superseded by Vital Product Data as
described in Section 6.4.
PCI Data Structure
Length
The PCI Data Structure Length is a 16-bit field that defines
the length of the data structure from the start of the data
structure (the first byte of the Signature field). This field is in
little-endian format and is in units of bytes.
PCI Data Structure
Revision
The PCI Data Structure Revision field is an eight-bit field that
identifies the data structure revision level. This revision level
is 0.
Class Code
The Class Code field is a 24-bit field with the same fields and
definition as the class code field in the Configuration Space
for this device.
Image Length
The Image Length field is a two-byte field that represents the
length of the image. This field is in little-endian format, and
the value is in units of 512 bytes.
Revision Level
The Revision Level field is a two-byte field that contains the
revision level of the code in the ROM image.
Code Type
The Code Type field is a one-byte field that identifies the
type of code contained in this section of the ROM. The code
may be executable binary for a specific processor and system
architecture or interpretive code. The following code types
are assigned:
Indicator
48
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Bit 7 in this field tells whether or not this is the last image in
the ROM. A value of 1 indicates "last image;" a value of 0
indicates that another image follows. Bits 0-6 are reserved.
Open Firmware is a processor architecture and system architecture independent standard for dealing with
device specific option ROM code. Documentation for Open Firmware is available in the IEEE 1275-1994
Standard for Boot (Initialization, Configuration) Firmware Core Requirements and Practices. A related
document, PCI Bus Binding to IEEE 1275-1994, specifies the application of Open Firmware to the PCI
local bus, including PCI-specific requirements and practices. This document may be obtained using
anonymous FTP to the machine playground.sun.com with the filename
/pub/p1275/bindings/postscript/PCI.ps.
208
Revision 2.2
6.3.2. Power-on Self Test (POST) Code
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6.3.3. PC-compatible Expansion ROMs
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6.3.3.1. ROM Header Extensions
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FRPSDWLELOLW\7ZRILHOGVDUHDGGHGRQHDWRIIVHWKSURYLGHVWKHLQLWLDOL]DWLRQVL]HIRU
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Offset
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1h
2h
Length
1
1
1
Value
55h
AAh
xx
3h
3
xx
6h-17h
18h-19h
12h
2
xx
xx
Description
ROM Signature byte 1
ROM Signature byte 2
Initialization Size - size of the code in units of
512 bytes
Entry point for INIT function. POST does a
FAR CALL to this location.
Reserved (application unique data)
Pointer to PCI Data Structure
6.3.3.1.1. POST Code Extensions
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209
Revision 2.2
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6.3.3.1.2. INIT Function Extensions
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210
Revision 2.2
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6.3.3.1.3. Image Structure
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7KHUXQWLPHOHQJWKVSHFLILHVWKHDPRXQWRIWKHLPDJHWKDWFRQWDLQVWKHUXQWLPHFRGH
7KLVLVWKHDPRXQWRIGDWDWKH3267FRGHZLOOOHDYHLQ5$0ZKLOHWKHV\VWHPLV
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Header
Runtime size
Initialization size
PCI Data structure
Checksum byte
Image size
Checksum byte
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211
Revision 2.2
6.4. Vital Product Data
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6.5. Device Drivers
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IURPVWDQGDUGRUH[LVWLQJGHYLFHGULYHUV7KHILUVWFKDUDFWHULVWLFLVWKDW3&,GHYLFHVDUH
UHORFDWDEOHLHQRWKDUGZLUHGLQWKHDGGUHVVVSDFHV3&,GHYLFHGULYHUVDQGRWKHU
FRQILJXUDWLRQVRIWZDUHVKRXOGXVHWKHPDSSLQJLQIRUPDWLRQVWRUHGLQWKHGHYLFH
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7KHVHFRQGFKDUDFWHULVWLFLVWKDW3&,LQWHUUXSWVDUHVKDUHDEOH3&,GHYLFHGULYHUVDUH
UHTXLUHGWRVXSSRUWVKDUHGLQWHUUXSWVVLQFHLWLVYHU\OLNHO\WKDWV\VWHPLPSOHPHQWDWLRQV
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6RPHV\VWHPVPD\QRWJXDUDQWHHWKDWGDWDLVGHOLYHUHGWRPDLQPHPRU\EHIRUHLQWHUUXSWV
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7KHV\VWHPKDUGZDUHFDQJXDUDQWHHWKDWSRVWLQJEXIIHUVDUHIOXVKHGEHIRUHLQWHUUXSWV
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7KHGHYLFHVLJQDOLQJWKHLQWHUUXSWFDQSHUIRUPDUHDGRIWKHMXVWZULWWHQGDWDEHIRUH
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212
Revision 2.2
6.6. System Reset
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6.7. Capabilities List
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DGGLQJDVHWRIUHJLVWHUVWRDOLQNHGOLVWFDOOHGWKH&DSDELOLWLHV/LVW7KLVRSWLRQDOGDWD
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213
Revision 2.2
6.8. Message Signaled Interrupts
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6.8.1. Message Capability Structure
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06,FDSDEOHGHYLFH7KHPHVVDJHFDSDELOLW\VWUXFWXUHLVLOOXVWUDWHGLQ)LJXUH(DFK
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214
Revision 2.2
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6.8.1.1. Capability ID
7::0
CAP_ID
The value of 05h in this field identifies the function as
message signaled interrupt capable. This field is
read only.
6.8.1.2. Next Pointer
7::0
NXT_PTR
Pointer to the next item in the capabilities list. Must
be NULL for the final item in the list. This field is read
only.
6.8.1.3. Message Control
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ILHOGV
Bits
Field
15::08
Reserved
7
64 bit address
capable
Description
Always returns 0 on a read and a write operation has
no effect.
If 1, the function is capable of generating a 64-bit
message address.
If 0, the function is not capable of generating a 64-bit
message address.
This bit is read only.
215
Revision 2.2
Bits
6::4
Field
Multiple Message
Enable
Description
System software writes to this field to indicate the
number of allocated messages (equal to or less than
the number of requested messages). The number of
allocated messages is aligned to a power of two. If a
function requests four messages (indicated by a
Multiple Message Capable encoding of “010”), system
software can allocate either four, two, or one
message by writing a “010”, “001, or “000” to this
field, respectively. When MSI is enabled, a device will
be allocated at least 1 message. The encoding is
defined as:
Encoding
# of messages allocated
000
1
001
2
010
4
011
8
100
16
101
32
110
Reserved
111
Reserved
This field’s state after reset is “000”.
This field is read/write.
3::1
Multiple Message
Capable
System software reads this field to determine the
number of requested messages. The number of
requested messages must be aligned to a power of
two (if a function requires three messages, it requests
four by initializing this field to “010”). The encoding is
defined as:
Encoding
000
1
001
2
010
4
011
8
100
16
101
32
110
Reserved
111
Reserved
This field is read/only.
216
# of messages requested
Revision 2.2
Bits
0
Field
MSI Enable
Description
If 1, the function is permitted to use MSI to request
service and is prohibited from using its INTx# pin (if
implemented). System configuration software sets
this bit to enable MSI. A device driver is prohibited
from writing this bit to mask a function’s service
request.
If 0, the function is prohibited from using MSI to
request service.
This bit’s state after reset is 0 (MSI is disabled).
This bit is read/write.
6.8.1.4. Message Address
Bits
31::02
Field
Message
Address
Description
System-specified message address.
If the Message Enable bit (bit 0 of the Message
Control register) is set, the contents of this register
specify the DWORD aligned address (AD[31::02]) for
the MSI memory write transaction. AD[1::0] are
driven to zero during the address phase.
This field is read/write.
01::00
Reserved
Always returns 0 on read. Write operations have no
effect.
6.8.1.5. Message Upper Address (Optional)
Bits
31::00
Field
Message Upper
Address
Description
System-specified message upper address.
This register is optional and is implemented only if the
device supports a 64-bit message address (bit 7 in
Message Control register set)49. If the Message
Enable bit (bit 0 of the Message Control register) is
set, the contents of this register (if non-zero) specify
the upper 32-bits of a 64-bit message address
(AD[63::32]). If the contents of this register are zero,
the device uses the 32 bit address specified by the
message address register.
This field is read/write.
49
This register is required when the device supports 64-bit addressing (DAC) when acting as a master.
217
Revision 2.2
6.8.1.6. Message Data
Bits
Field
Description
15::00
Message Data
System-specified message.
Each MSI function is allocated up to 32 unique
messages.
System architecture specifies the number of unique
messages supported by the system.
If the Message Enable bit (bit 0 of the Message
Control register) is set, the message data is driven
onto the lower word (AD[15::00]) of the memory write
transaction’s data phase. AD[31::16] are driven to
zero during the memory write transaction’s data
phase. C/BE[3::0]# are asserted during the data
phase of the memory write transaction.
The Multiple Message Enable field (bits 6-4 of the
Message Control register) defines the number of low
order message data bits the function is permitted to
modify to generate its system software allocated
messages. For example, a Multiple Message Enable
encoding of “010” indicates the function has been
allocated four messages and is permitted to modify
message data bits 1 and 0 (a function modifies the
lower message data bits to generate the allocated
number of messages). If the Multiple Message
Enable field is “000”, the function is not permitted to
modify the message data.
This field is read/write.
6.8.2. MSI Operation
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218
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219
Revision 2.2
6.8.2.1. MSI Transaction Termination
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PHPRU\ZULWHWUDQVDFWLRQ7KHWHUPLQDWLRQUHTXLUHPHQWVIRUDQ06,DUHWKHVDPHDVIRU
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PDVWHUWKDWRULJLQDWHGWKH06,ZULWHWUDQVDFWLRQLVUHTXLUHGWRUHSRUWWKHHUURUE\
DVVHUWLQJSERR#LIELWLQWKH&RPPDQGUHJLVWHULVVHWDQGWRVHWWKHDSSURSULDWHELWV
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WKHWDUJHWLILWLVWHUPLQDWHGZLWKD0DVWHU$ERUWRU7DUJHW$ERUW
If the MSI write transaction results in a data parity error, the master that originated the
MSI write transaction is required to assert SERR# (if bit 8 in the Command register is
set) and to set the appropriated bits in the Status register (refer to Section 3.7.4.).
6.8.2.2. MSI Transaction Reception and Ordering Requirements
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220
Revision 2.2
Chapter 7
66 MHz PCI Specification
7.1. Introduction
7KH0+]3&,EXVLVDFRPSDWLEOHVXSHUVHWRI3&,GHILQHGWRRSHUDWHXSWRD
PD[LPXPFORFNVSHHGRI0+]7KH0+]3&,EXVLVLQWHQGHGWREHXVHGE\ORZ
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VWDWLFVLJQDOLVDGGHGE\UHGHILQLQJDQH[LVWLQJJURXQGSLQDQGRQHELWLVDGGHGWRWKH
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0+]3&,EXV6LPLODUO\LIDQ\0+]3&,GHYLFHVDUHFRQQHFWHGWRD0+]3&,
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7.2. 6FRSH
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WKLVGRFXPHQWLQFOXGLQJLQIRUPDWLRQRQGHYLFHDQGEULGJHVXSSRUW7KLVFKDSWHUZLOOQRW
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221
Revision 2.2
7.3. Device Implementation Considerations
7.3.1. Configuration Space
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7.4. Agent Architecture
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7.5. Protocol
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition
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NQRZOHGJHRIWKHVSHHGLWLVSHUPLWWHGWROHDYHM66ENGLVFRQQHFWHG
50
Configuration software identifies agent capabilities by checking the 66MHZ_CAPABLE bit in the Status
register. This includes both the primary and secondary Status registers in a PCI-to-PCI bridge. This allows
configuration software to detect a 33 MHz PCI agent on a 66 MHz PCI bus or a 66 MHz PCI agent on a
33 MHz PCI bus and issue a warning to the user describing the situation.
222
Revision 2.2
7DEOH%XVDQG$JHQW&RPELQDWLRQV
Bus
66MHZ_CAPABLE51
Agent
66MHZ_CAPABLE
0
0
33 MHz PCI agent located on a
33 MHz PCI bus
0
1
66 MHz PCI agent located on a
33 MHz PCI bus52
1
0
33 MHz PCI agent located on a
66 MHz PCI bus52
1
1
66 MHz PCI agent located on a
66 MHz PCI bus
Description
7.5.2. Latency
7KH0+]3&,EXVLVLQWHQGHGIRUORZODWHQF\GHYLFHV,WLVUHTXLUHGWKDWWKHWDUJHW
LQLWLDOODWHQF\QRWH[FHHGFORFNV
7.6. Electrical Specification
7.6.1. Overview
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FRPSRQHQWVV\VWHPVDQGH[SDQVLRQERDUGVLQFOXGLQJFRQQHFWRUSLQDVVLJQPHQWV
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51
•
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The bus 66MHZ_CAPABLE status bit is located in a bridge’s Status registers.
52
This condition may cause the configuration software to generate a warning to the user stating that the
card is installed in an inappropriate socket and should be relocated.
223
Revision 2.2
7.6.2. Transition Roadmap to 66 MHz PCI
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Tcyc ≥ Tval + Tprop + Tskew + Tsu
Tcyc = 30 ns
33 MHZ
Tval =11 ns
Tprop = 10 ns
Tskew = 2ns
Tsu=7ns
Tcyc = 15 ns
66 MHZ
Tval
6 ns
Tprop
5 ns
Tskew
1 ns
Tsu
3 ns
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7.6.3. Signaling Environment
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224
Revision 2.2
7.6.3.1. DC Specifications
5HIHUWR6HFWLRQ
7.6.3.2. AC Specifications
7DEOH$&6SHFLILFDWLRQV
Symbol
Parameter
Condition
Min
Max
Units Notes
AC Drive Points
Ioh(AC,min)
Switching Current
High, minimum
Vout = 0.3Vcc
-12Vcc
-
mA
Ioh(AC,max)
Switching Current
High, maximum
Vout = 0.7Vcc
-
-32Vcc
mA
Iol(AC,min)
Switching Current
Low, minimum
Vout = 0.6Vcc
16Vcc
-
mA
Iol(AC,max)
Switching
Current Low,
maximum
Vout = 0.18Vcc
-
38Vcc
mA
1
1
DC Drive Points
VOH
Output high
voltage
Iout = -0.5 mA
0.9Vcc
-
V
2
VOL
Output low
voltage
Iout = 1.5 mA
-
0.1Vcc
V
2
tr
Output rise slew
rate
0.3Vcc to 0.6Vcc
1
4
V/ns
3
tf
Output fall slew
rate
0.6Vcc to 0.3Vcc
1
4
V/ns
3
Ich
High clamp
current
Vcc + 4 > Vin ≥ Vcc + 1
25 + (Vin - Vcc - 1) / 0.015
-
mA
Icl
Low clamp
current
-3 < Vin ≤ -1
-25 + (Vin + 1) / 0.015
-
mA
Slew Rate
Clamp Current
NOTES:
1. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half
size drivers may be used on these signals. This specification does not apply to CLK and RST# which are system
outputs. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and
INTD# which are open drain outputs.
2. These DC values are duplicated from Section 4.2.2.1. and are included here for completeness.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
instantaneous rate at any point within the transition range. The specified load (see Figure 7-7) is optional. The
designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus
Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not
simply a guideline). Rise slew rate does not apply to open drain outputs.
225
Revision 2.2
7.6.3.3. Maximum AC Ratings and Device Protection
5HIHUWR6HFWLRQ
7.6.4. Timing Specification
7.6.4.1. Clock Specification
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7DEOHVXPPDUL]HVWKHFORFNVSHFLILFDWLRQV T_cyc
T_high
3.3 volt Clock
0.6 Vcc
T_low
0.5 Vcc
0.4 Vcc, p-to-p
(minimum)
0.4 Vcc
0.3 Vcc
0.2 Vcc
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7DEOH
226
Revision 2.2
7DEOH&ORFN6SHFLILFDWLRQV
33 MHz4
66 MHz
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
Tcyc
CLK Cycle Time
15
30
30
∞
ns
1,3
Thigh
CLK High Time
6
11
ns
Tlow
CLK Low Time
6
11
ns
-
CLK Slew Rate
1.5
4
1
4
V/ns
-
-
kHz
2
Spread Spectrum Requirements
fmod
modulation
frequency
30
33
fspread
frequency
spread
-1
9
%
NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK
requirements vary depending upon whether the clock frequency is above 33 MHz.
a.
Device operational parameters at frequencies at or under 33 MHz will conform to the specifications in
Chapter 4. The clock frequency may be changed at any time during the operation of the system so
long as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low times
are not violated. The clock may only be stopped in a low state. A variance on this specification is
allowed for components designed for use on the system planar only. Refer to Section 4.2.3.1. for
more information.
b.
For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change except
while RST# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in Figure 7-2. Clock slew rate
is measured by the slew rate circuit shown in Figure 7-7.
3. The minimum clock period must not be violated for any single clock cycle; i.e., accounting for all system
jitter.
4. These values are duplicated from Section 4.2.3.1. and included here for comparison.
Implementation Note: Spread Spectrum Clocking (SSC)
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227
Revision 2.2
7.6.4.2. Timing Parameters
7DEOH0+]DQG0+]7LPLQJ3DUDPHWHUV
33 MHz7
66 MHz
Symbol
Min
Max
Min
Max
CLK to Signal Valid Delay bused signals
2
6
2
11
ns
1, 2,
3, 8
Tval(ptp) CLK to Signal Valid Delay point to point signals
2
6
2
12
ns
1, 2,
3, 8
ns
1, 8, 9
ns
1, 9
Tval
Parameter
2
2
Units
Notes
Ton
Float to Active Delay
Toff
Active to Float Delay
Tsu
Input Setup Time to CLK bused signals
3
7
ns
3, 4,
10
Tsu(ptp) Input Setup Time to CLK point to point signals
5
10,12
ns
3, 4
14
28
Th
Input Hold Time from CLK
0
0
ns
4
Trst
Reset Active Time after
power stable
1
1
ms
5
100
100
µs
5
ns
5, 6
Trst-clk
Reset Active Time after CLK
stable
Trst-off
Reset Active to output float
delay
40
trrsu
REQ64# to RST# setup time
10Tcyc
trrh
RST# to REQ64# hold time
0
Trhfa
RST# high to first
Configuration access
2
Trhff
RST# high to first FRAME#
assertion
5
25
40
10Tcyc
50
0
2
ns
50
25
5
ns
clocks
clocks
NOTES:
1.
See the timing measurement conditions in Figure 7-3. It is important that all driven signal transitions drive to their
Voh or Vol level within one Tcyc.
2.
Minimum times are measured at the package pin with the load circuit shown in Figure 7-7. Maximum times are
measured with the load circuit shown in Figures 7-5 and 7-6.
3.
REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#
and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.
4.
See the timing measurement conditions in Figure 7-4.
5.
If M66EN is asserted, CLK is stable when it meets the requirements in Section 7.6.4.1. RST# is asserted and
deasserted asynchronously with respect to CLK. Refer to Section 4.3.2. for more information.
6.
All output drivers must be floated when RST# is active. Refer to Section 4.3.2. for more information.
7.
These values are duplicated from Section 4.2.3.2. and are included here for comparison.
8.
When M66EN is asserted, the minimum specification for T val(min), Tval(ptp)(min), and Ton may be reduced to
1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is deasserted.
228
Revision 2.2
9.
For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
10. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the
same time. Refer to Section 3.10., item 9 for additional details.
7.6.4.3. Measurement and Test Conditions
V_th
CLK
V_test
V_tl
T_val
OUTPUT
DELAY
V_tfall
T_val
OUTPUT
DELAY
V_trise
Tri-State
OUTPUT
T_on
T_off
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V_th
CLK
V_test
V_tl
T_su
T_h
V_th
INPUT
V_test
inputs
valid
V_test
V_max
V_tl
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229
Revision 2.2
7DEOH0HDVXUHPHQW&RQGLWLRQ3DUDPHWHUV
Symbol
Vth
3.3V Signaling
0.6Vcc
V
Units
1
Notes
Vtl
0.2Vcc
V
1
Vtest
0.4Vcc
V
Vtrise
0.285Vcc
V
2
Vtfall
0.615Vcc
V
2
Vmax
0.4Vcc
V
1
Input Signal
Slew Rate
1.5
V/ns
3
NOTES:
1.
The test for the 3.3V environment is done with 0.1*V cc of overdrive.
Vmax specifies the maximum peak-to-peak waveform allowed for
measuring input timing. Production testing may use different voltage
values but must correlate results back to these parameters.
2.
Vtrise and Vtfall are reference voltages for timing measurements only.
Developers of 66 MHz PCI systems need to design buffers that launch
enough energy into a 25 Ω transmission line so that correct input
levels are guaranteed after the first reflection.
3.
Outputs will be characterized and measured at the package pin with
the load shown in Figure 7-7. Input signal slew rate will be measured
between 0.3Vcc and 0.6Vcc.
pin
1/2 in. max.
output
buffer
10 pF
25 Ω
)LJXUH7YDOPD[5LVLQJ(GJH
1/2 in. max.
Vcc
25 Ω
10 pF
)LJXUH7YDOPD[)DOOLQJ(GJH
230
Revision 2.2
pin
1/2 in. max.
output
buffer
Vcc
1K Ω
10 pF
1K Ω
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7.6.5. Vendor Provided Specification
5HIHUWR6HFWLRQ
7.6.6. Recommendations
7.6.6.1. Pinout Recommendations
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7.6.6.2. Clocking Recommendations
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231
Revision 2.2
Clock Source
Add-in Board
66 MHz
Device A
PCI Add-in
Connector
66 MHz
Device B
66 MHz
Device C
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7.7. System (Planar) Specification
7.7.1. Clock Uncertainty
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53
Symbol
66 MHz 3.3V Signaling
33 MHz 3.3V Signaling
Units
Vtest
0.4Vcc
0.4Vcc
V
Tskew
1 (max)
2 (max)
ns
The system designer must address an additional source of clock skew. This clock skew occurs between
two components that have clock input trip points at opposite ends of the Vil - Vih range. In certain
circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew
must be limited to the specified number.
232
Revision 2.2
V_ih
CLK
(@Device #1)
V_test
V_il
T_skew
T_skew
T_skew
V_ih
CLK
(@Device #2)
V_test
V_il
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7.7.2. Reset
5HIHUWR6HFWLRQ
7.7.3. Pullups
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7.7.4. Power
7.7.4.1. Power Requirements
5HIHUWR6HFWLRQ
7.7.4.2. Sequencing
5HIHUWR6HFWLRQ
7.7.4.3. Decoupling
5HIHUWR6HFWLRQ
7.7.5. System Timing Budget
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233
Revision 2.2
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Implementation Note: Determining the End of Tprop
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234
Revision 2.2
0.7Vcc
0.7Vcc
0.6Vcc
0.5Vcc
0.4Vcc
Vth
Driving Bus
0.6Vcc
Vih
0.5Vcc
Vtest
0.4Vcc
Input Signal
Slew Rate
Vth
Vih
Driving
Bus
Vtest
0.3Vcc Vtrise
0.3Vcc Vtrise
0.2Vcc
Driving
Test Load
Tprop
0.2Vcc
Tprop
0.1Vcc
0.1Vcc
0
0
(a)
(b)
0.9Vcc
0.9V cc
0.8V cc
Input Signal
Slew Rate
0.7V cc
0.6V cc
0.5V cc
0.4V cc
0.3V cc
Driving
Test Load
Vth
Driving
Bus
0.8Vcc
Tprop
0.7Vcc
0.6Vcc
Vih
Vtfall
Driving
Test Load
0.5Vcc
Vtest
0.4Vcc
Vtest
0.3Vcc Vil
Vtrise
Driving
Test Load
0.2V cc
0.2Vcc
Driving Bus
Vtl
Tprop
0.1Vcc
0.1V cc
0
0
(d)
(c)
0.9Vcc
0.9Vcc
0.8Vcc
0.8Vcc
Tprop
Tprop
0.7Vcc
0.7Vcc
Vtfall
Driving
Test Load
0.5Vcc
0.4Vcc
0.3Vcc
0.2Vcc
Vtfall
0.6Vcc
0.6Vcc
Vtest
0.5Vcc
0.4Vcc
Input Signal
Slew Rate
Vil
Driving Bus
Vtl
Driving
Test Load
0.3Vcc
0.2Vcc
Vtest
Vtl
0.1Vcc
0.1Vcc
Input Signal
Slew Rate
Vil
Driving Bus
0
0
(e)
(f)
)LJXUH0HDVXUHPHQWRI7SURS
UHIHUWR7DEOHIRUSDUDPHWHUYDOXHV
235
Revision 2.2
7KHUHOHYDQWWLPLQJEXGJHWFDQEHH[SUHVVHGE\WKHHTXDWLRQ
7F\F≥7YDO7SURS7VX7VNHZ
7KHIROORZLQJWDEOHFRPSDUHV3&,WLPLQJEXGJHWVDWYDULRXVVSHHGV
7DEOH7LPLQJ%XGJHWV
Timing Element
33 MHz
66 MHz
50 MHz1
Units
Tcyc
30
15
20
ns
Tval
11
6
6
ns
Tprop
10
5
10
ns
Tsu
7
3
3
ns
Tskew
2
1
1
ns
Notes
2
3
NOTES:
1.
The 50 MHz example is shown for example purposes only.
2.
These times are computed. The other times are fixed. Thus, slowing down the bus clock enables the
system manufacturer to gain additional distance or add additional loads. The component specifications
are required to guarantee operation at 66 MHz.
3
Clock skew specified here includes all sources of skew. If spread spectrum clocking (SSC) is used on the
system board, the maximum clock skew at the input of the device on an expansion board includes SSC
tracking skew.
7.7.6. Physical Requirements
7.7.6.1. Routing and Layout Recommendations for Four-Layer
Boards
5HIHUWR6HFWLRQ
7.7.6.2. Planar Impedance
5HIHUWR6HFWLRQ7LPLQJQXPEHUVDUHFKDQJHGDFFRUGLQJWRWKHWDEOHVLQWKLV
FKDSWHU
7.7.7. Connector Pin Assignments
7KHM66ENSLQSLQ%LVWKHRQO\FRQQHFWRUGLIIHUHQFHEHWZHHQEXVVHJPHQWV
FDSDEOHRI0+]RSHUDWLRQDQGWKRVHOLPLWHGWR0+]5HIHUWR6HFWLRQIRU
SODQDUFRQQHFWRUV7KLVSLQLVDQRUPDOJURXQGSLQLQLPSOHPHQWDWLRQVWKDWDUHQRW
FDSDEOHRI0+]RSHUDWLRQ
236
Revision 2.2
,QLPSOHPHQWDWLRQVWKDWDUH0+]FDSDEOHWKHM66ENSLQLVEXVHGEHWZHHQDOO
FRQQHFWRUVZLWKLQWKHVLQJOHORJLFDOEXVVHJPHQWWKDWLV0+]FDSDEOHDQGWKLVQHW
LVSXOOHGXSZLWKD.ΩUHVLVWRUWR9FF$OVRWKLVQHWLVFRQQHFWHGWRWKHM66ENLQSXW
SLQRIFRPSRQHQWVORFDWHGRQWKHVDPHORJLFDOEXVVHJPHQWRIWKHV\VWHPSODQDU7KLV
VLJQDOLVVWDWLFWKHUHLVQRVWXEOHQJWKUHVWULFWLRQ
7RFRPSOHWHDQ$&UHWXUQSDWKDµ)FDSDFLWRUPXVWEHORFDWHGZLWKLQLQFKHV
RIWKHM66ENSLQRIHDFKVXFKH[SDQVLRQERDUGFRQQHFWRUDQGPXVWGHFRXSOHWKH
M66ENVLJQDOWRJURXQG$Q\DWWDFKHGFRPSRQHQWRULQVWDOOHGH[SDQVLRQERDUGWKDWLV
QRW0+]FDSDEOHPXVWSXOOWKHM66ENQHWWRWKH9LOLQSXWOHYHO7KHUHPDLQLQJ
FRPSRQHQWVH[SDQVLRQERDUGVDQGWKHORJLFDOEXVVHJPHQWFORFNUHVRXUFHDUHWKHUHE\
VLJQDOHGWRRSHUDWHLQ0+]PRGH
7.8. Expansion Board Specifications
7KHM66ENSLQSLQ%LVWKHRQO\FRQQHFWRUGLIIHUHQFHEHWZHHQH[SDQVLRQFDUGV
FDSDEOHRI0+]RSHUDWLRQDQGWKRVHOLPLWHGWR0+]5HIHUWR6HFWLRQIRU
WKHH[SDQVLRQERDUGHGJHFRQQHFWRU7KHM66ENSLQLVDQRUPDOJURXQGSLQLQ
LPSOHPHQWDWLRQVWKDWDUHQRWFDSDEOHRI0+]RSHUDWLRQ
,QLPSOHPHQWDWLRQVWKDWDUH0+]FDSDEOHWKHM66ENSLQPXVWEHGHFRXSOHGWR
JURXQGZLWKDµ)FDSDFLWRUZKLFKPXVWEHORFDWHGZLWKLQLQFKHVRIWKHHGJH
FRQWDFWWRFRPSOHWHDQ$&UHWXUQSDWK,IWKHM66ENSLQLVSXOOHGWRWKH9LOLQSXWOHYHO
LWLQGLFDWHVWKDWWKHH[SDQVLRQERDUGPXVWRSHUDWHLQWKH0+]PRGH
54
As a general rule, there will be only one such connector, but more than one are possible in certain cases.
237
Revision 2.2
238
Revision 2.2
Appendix A
Special Cycle Messages
6SHFLDO&\FOHPHVVDJHHQFRGLQJVDUHGHILQHGLQWKLVDSSHQGL[5HVHUYHGHQFRGLQJVVKRXOGQRW
EHXVHG3&,6,*PHPEHUFRPSDQLHVWKDWUHTXLUHVSHFLDOHQFRGLQJVRXWVLGHWKHUDQJHRI
FXUUHQWO\GHILQHGHQFRGLQJVVKRXOGVHQGDZULWWHQUHTXHVWWRWKH3&,6,*6WHHULQJ&RPPLWWHH
7KH6WHHULQJ&RPPLWWHHZLOODOORFDWHDQGGHILQHVSHFLDOF\FOHHQFRGLQJVEDVHGXSRQ
LQIRUPDWLRQSURYLGHGE\WKHUHTXHVWHUVSHFLI\LQJXVDJHQHHGVDQGIXWXUHSURGXFWRUDSSOLFDWLRQ
GLUHFWLRQ
Message Encodings
AD[15::0]
K
K
K
K
WKURXJK
))))K
0HVVDJH7\SH
6+87'2:1
+$/7
[DUFKLWHFWXUHVSHFLILF
5HVHUYHG
5HVHUYHG
6+87'2:1LVDEURDGFDVWPHVVDJHLQGLFDWLQJWKHSURFHVVRULVHQWHULQJLQWRD
VKXWGRZQPRGH
+$/7LVDEURDGFDVWPHVVDJHIURPWKHSURFHVVRULQGLFDWLQJLWKDVH[HFXWHGDKDOW
LQVWUXFWLRQ
7KH[DUFKLWHFWXUHVSHFLILFHQFRGLQJLVDJHQHULFHQFRGLQJIRUXVHE\[SURFHVVRUV
DQGFKLSVHWVAD[31::16]GHWHUPLQHWKHVSHFLILFPHDQLQJRIWKH6SHFLDO&\FOHPHVVDJH
6SHFLILFPHDQLQJVDUHGHILQHGE\,QWHO&RUSRUDWLRQDQGDUHIRXQGLQSURGXFWVSHFLILF
GRFXPHQWDWLRQ
Use of Specific Encodings
8VHRUJHQHUDWLRQRIDUFKLWHFWXUHVSHFLILFHQFRGLQJVLVQRWOLPLWHGWRWKHUHTXHVWHURIWKH
HQFRGLQJ6SHFLILFHQFRGLQJVPD\EHXVHGE\DQ\YHQGRULQDQ\V\VWHP7KHVH
HQFRGLQJVDOORZV\VWHPVSHFLILFFRPPXQLFDWLRQOLQNVEHWZHHQFRRSHUDWLQJ3&,GHYLFHV
IRUSXUSRVHVZKLFKFDQQRWEHKDQGOHGZLWKWKHVWDQGDUGGDWDWUDQVIHUF\FOHW\SHV
239
Revision 2.2
240
Revision 2.2
Appendix B
State Machines
This appendix describes master and target state machines. These state machines are for
illustrative purposes only and are included to help illustrate PCI protocol. Actual
implementations should not directly use these state machines. The machines are
believed to be correct; however, if a conflict exists between the specification and the
state machines, the specification has precedence.
The state machines use three types of variables: states, PCI signals, and internal signals.
They can be distinguished from each other by:
State in a state machine = STATE
PCI signal = SIGNAL
Internal signal = Signal
The state machines assume no delays from entering a state until signals are generated
and available for use in the machine. All PCI signals are latched on the rising edge of
CLK.
The state machines support some options (but not all) discussed in the PCI specification.
A discussion about each state and the options illustrated follows the definition of each
state machine. The target state machine assumes medium decode and, therefore, does
not describe fast decode. If fast decode is implemented, the state diagrams (and their
associated equations) will need to be changed to support fast decode. Caution needs to
be taken when supporting fast decode (Refer to Section 3.4.2.).
The bus interface consists of two parts. The first is the bus sequencer that performs the
actual bus operation. The second part is the backend or hardware application. In a
master, the backend generates the transaction and provides the address, data, command,
Byte Enables, and the length of the transfer. It is also responsible for the address when a
transaction is retried. In a target, the backend determines when a transaction is
terminated. The sequencer performs the bus operation as requested and guarantees the
PCI protocol is not violated. Note that the target implements a resource lock.
The state machine equations assume a logical operation where "*" is an AND function
and has precedence over "+" which is an OR function. Parentheses have precedence
over both. The "!" character is used to indicate the NOT of the variable. In the state
machine equations, the PCI SIGNALs represent the actual state of the signal on the PCI
bus. Low true signals will be true or asserted when they appear as !SIGNAL# and will
be false or deasserted when they appear as SIGNAL#. High true signals will be true or
241
Revision 2.2
asserted when they appear as SIGNAL and will be false or deasserted when they appear
as !SIGNAL. Internal signals will be true when they appear as Signal and false when
they appear as !Signal. A few of the output enable equations use the "==" symbol to
refer to the previous state. For example:
OE[PAR] == [S_DATA * !TRDY# * (cmd=read)]
This indicates the output buffer for PAR is enabled when the previous state is S_DATA,
TRDY# is asserted, the transaction is a read. The first state machine presented is for the
target, the second is the master. Caution needs to be taken when an agent is both a
master and a target. Each must have its own state machine that can operate
independently of the other to avoid deadlocks. This means that the target state machine
cannot be affected by the master state machine. Although they have similar states, they
cannot be built into a single machine.
Note: LOCK# can only be implemented by a bridge; refer to Appendix F for details
about the use of LOCK#. For a non-bridge device, the use of LOCK# is prohibited.
B _ BU S Y
ID LE
B A CK O F F
S _D AT A
Target
Sequencer
Machine
TURN_AR
FREE
LOCKED
Target LOCK Machine
IDLE or TURN_AR -- Idle condition or completed transaction on bus.
goto IDLE
goto B_BUSY
242
if FRAME#
if !FRAME# * !Hit
Revision 2.2
B_BUSY -- Not involved in current transaction.
goto B_BUSY
goto IDLE
goto S_DATA
goto BACKOFF
if (!FRAME# + !D_done) * !Hit
if FRAME# * D_done + FRAME# * !D_done * !DEVSEL#
if (!FRAME# + !IRDY#) * Hit * (!Term + Term * Ready)
* (FREE + LOCKED * L_lock#)
*if (!FRAME# + !IRDY#) * Hit
* (Term * !Ready + LOCKED * !L_lock#)
S_DATA -- Agent has accepted request and will respond.
goto S_DATA
goto BACKOFF
goto TURN_AR
if !FRAME# * !STOP# * !TRDY# * IRDY#
+ !FRAME# * STOP# + FRAME# * TRDY# * STOP#
if !FRAME# * !STOP# * (TRDY# + !IRDY#)
if FRAME# * (!TRDY# + !STOP#)
BACKOFF -- Agent busy unable to respond at this time.
goto BACKOFF
goto TURN_AR
if !FRAME#
if FRAME#
Target LOCK Machine
FREE -- Agent is free to respond to all transactions.
goto LOCKED
goto FREE
if !FRAME# * LOCK# * Hit * (IDLE + TURN_AR)
+ L_lock# * Hit * B_BUSY)
if ELSE
LOCKED -- Agent will not respond unless LOCK# is deasserted during the address
phase.
goto FREE
goto LOCKED
if FRAME# * LOCK#
if ELSE
Target of a transaction is responsible to drive the following signals: 55
OE[AD[31::00]]
OE[TRDY#]
OE[STOP#]
OE[DEVSEL#]
OE[PAR]
OE[PERR#]
=
=
=
=
=
=
(S_DATA + BACKOFF) * Tar_dly * (cmd = read)
BACKOFF + S_DATA + TURN_AR (See note.)
BACKOFF + S_DATA + TURN_AR (See note.)
BACKOFF + S_DATA + TURN_AR (See note.)
OE[AD[31::00]] delayed by one clock
R_perr + R_perr (delayed by one clock)
Note: If the device does fast decode, OE[PERR#] must be delayed one clock to
avoid contention.
When the target supports the Special Cycle command, an additional term must be included to ensure
these signals are not enabled during a Special Cycle transaction.
243
Revision 2.2
TRDY#
STOP#
DEVSEL#
PAR
PERR#
= !(Ready * !T_abort * S_DATA * (cmd=write + cmd=read * Tar_dly))
= ![BACKOFF + S_DATA * (T_abort + Term)
* (cmd=write + cmd=read * Tar_dly)]
= ![(BACKOFF + S_DATA) * !T_abort]
= even parity across AD[31::00] and C/BE#[3::0] lines.
= R_perr
Definitions
These signals are between the target bus sequencer and the backend. They indicate how
the bus sequencer should respond to the current bus operation.
Hit
D_done
T_abort
Term
Ready
L_lock#
Tar_dly
R_perr
Last_target
=
=
=
=
=
=
=
=
=
Hit on address decode.
Decode done. Device has completed the address decode.
Target is in an error condition and requires the current transaction to stop.
Terminate the transaction. (Internal conflict or > n wait states.)
Ready to transfer data.
Latched (during address phase) version of LOCK#.
Turn around delay only required for zero wait state decode.
Report parity error is a pulse of one PCI clock in duration.
Device was the target of the last (prior) PCI transaction.
The following paragraphs discuss each state and describe which equations can be
removed if some of the PCI options are not implemented.
The IDLE and TURN_AR are two separate states in the state machine, but are combined
here because the state transitions are the same from both states. They are implemented
as separate states because active signals need to be deasserted before the target tri-states
them.
If the target cannot do single cycle address decode, the path from IDLE to S_DATA can
be removed. The reason the target requires the path from the TURN_AR state to
S_DATA and B_BUSY is for back-to-back bus operations. The target must be able to
decode back-to-back transactions.
B_BUSY is a state where the agent waits for the current transaction to complete and the
bus to return to the Idle state. B_BUSY is useful for devices that do slow address
decode or perform subtractive decode. If the target does neither of these two options, the
path to S_DATA and BACKOFF may be removed. The term "!Hit" may be removed
from the B_BUSY equation also. This reduces the state to waiting for the current bus
transaction to complete.
S_DATA is a state where the target transfers data and there are no optional equations.
BACKOFF is where the target goes after it asserts STOP# and waits for the master to
deassert FRAME#.
FREE and LOCKED refer to the state of the target with respect to a lock operation. If
the target does not implement LOCK#, then these states are not required. FREE
indicates when the agent may accept any request when it is the target. If LOCKED, the
target will retry any request when it is the target unless LOCK# is deasserted during the
address phase. The agent marks itself locked whenever it is the target of a transaction
and LOCK# is deasserted during the address phase. It is a little confusing for the target
to lock itself on a transaction that is not locked. However, from an implementation point
of view, it is a simple mechanism that uses combinatorial logic and always works. The
device will unlock itself at the end of the transaction when it detects FRAME# and
LOCK# both deasserted.
244
Revision 2.2
The second equation in the goto LOCKED in the FREE state can be removed if fast
decode is done. The first equation can be removed if medium or slow decode is done.
L_lock# is LOCK# latched during the address phase and is used when the agent’s decode
completes.
IDLE
ADDR
DR_BUS
S_TAR
M_DATA
Master
Sequencer
Machine
TURN_AR
FREE
BUSY
Master LOCK Machine
Master Sequencer Machine
IDLE -- Idle condition on bus.
goto ADDR
goto DR_BUS
if (Request * !Step) * !GNT# * FRAME# * IRDY#
if (Request * Step + !Request) * !GNT# * FRAME# * IRDY#
goto IDLE
if ELSE
ADDR -- Master starts a transaction.
JRWR0B'$7$
RQWKHQH[WULVLQJHGJHRICLK
245
Revision 2.2
M_DATA -- Master transfers data.
goto M_DATA
goto ADDR
goto S_TAR
goto TURN_AR
if !FRAME# + FRAME# * TRDY# * STOP#
* !Dev_to
if (Request *!Step) * !GNT# * FRAME# * !TRDY# *
STOP# * L-cycle * (Sa +FB2B_Ena)
if FRAME# * !STOP# + FRAME# * Dev_to
if ELSE
TURN_AR -- Transaction complete, do housekeeping.
goto ADDR
goto DR_BUS
goto IDLE
if (Request * !Step) * !GNT#
if (Request * Step + !Request) * !GNT#
if GNT#
S_TAR -- Stop was asserted, do turn around cycle.
goto DR_BUS
goto IDLE
if !GNT#
if GNT#
DR_BUS -- Bus parked at this agent or agent is using address stepping.
goto DR_BUS
goto ADDR
goto IDLE
if (Request * Step + !Request)* !GNT#
if (Request * !Step) * !GNT#
if GNT#
Master LOCK Machine
FREE -- LOCK# is not in use (not owned).
goto FREE
goto BUSY
if LOCK# + !LOCK# * Own_lock
if !LOCK# * !Own_lock
BUSY -- LOCK# is currently being used (owned).
goto FREE
goto BUSY
246
if LOCK# * FRAME#
if !LOCK# + !FRAME#
Revision 2.2
The master of the transaction is responsible to drive the following signals:
Enable the output buffers:
OE[FRAME#]
= ADDR + M_DATA
OE[C/BE#[3::0]] = ADDR + M_DATA + DR_BUS
if ADDR drive command
if M_DATA drive byte enables
if DR_BUS if (Step * Request) drive command else drive lines to a valid state
OE[AD[31::00] = ADDR + M_DATA * (cmd=write) + DR_BUS
if ADDR drive address
if M_DATA drive data
if DR_BUS if (Step * Request) drive address else drive lines to a valid state
OE [LOCK#]
OE[IRDY#]
OE[PAR]
OE[PERR#]
= Own_lock * M_DATA + OE [LOCK#] * (!FRAME# + !LOCK#)
== [M_DATA + ADDR]
= OE[AD[31::00]] delayed by one clock
= R_perr + R_perr (delayed by one clock)
The following signals are generated from state and sampled (not asynchronous) bus
signals.
FRAME# = !( ADDR + M_DATA * !Dev_to * {[!Comp
* (!To + !GNT#) * STOP#] + !Ready })
IRDY#
REQ#
= ![M_DATA * (Ready + Dev_to)]
= ![(Request * !Lock_a + Request * Lock_a * FREE)
*!(S_TAR * Last State was S_TAR)]
LOCK#
= Own_lock * ADDR + Target_abort
+ Master_abort + M_DATA * !STOP# * TRDY# * !Ldt
+ Own_lock * !Lock_a * Comp * M_DATA * FRAME# * !TRDY#
= even parity across AD[31::00] and C/BE#[3::0] lines.
= R_perr
PAR
PERR#
Master_abort
Target_abort
Own_lock
= (M_DATA * Dev_to)
= (!STOP# * DEVSEL# * M_DATA * FRAME# * !IRDY#)
= LOCK# * FRAME# * IRDY# * Request * !GNT# * Lock_a
+ Own_lock * (!FRAME# + !LOCK#)
247
Revision 2.2
Definitions
These signals go between the bus sequencer and the backend. They provide information
to the sequencer when to perform a transaction and provide information to the backend
on how the transaction is proceeding. If a cycle is retried, the backend will make the
correct modification to the affected registers and then indicate to the sequencer to
perform another transaction. The bus sequencer does not remember that a transaction
was retried or aborted but takes requests from the backend and performs the PCI
transaction.
Master_abort
Target_abort
Step
Request
Comp
L-cycle
To
Dev_to
Sa
Lock_a
Ready
Sp_cyc
Own_lock
Ldt
R_perr
FB2B_Ena
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
The transaction was aborted by the master. (No DEVSEL#.)
The transaction was aborted by the target.
Agent using address stepping (wait in the state until !Step).
Request pending.
Current transaction in last data phase.
Last cycle was a write.
Master timeout has expired.
Devsel timer has expired without DEVSEL# being asserted.
Next transaction to same agent as previous transaction.
Request is a locked operation.
Ready to transfer data.
Special Cycle command.
This agent currently owns LOCK#.
Data was transferred during a LOCK operation.
Report parity error is a pulse one PCI clock in duration.
Fast Back-to-Back Enable (Configuration register bit).
The master state machine has many options built in that may not be of interest to some
implementations. Each state will be discussed indicating what affect certain options
have on the equations.
IDLE is where the master waits for a request to do a bus operation. The only option in
this state is the term "Step". It may be removed from the equations if address stepping is
not supported. All paths must be implemented. The path to DR_BUS is required to
insure that the bus is not left floating for long periods. The master whose GNT# is
asserted must go to the drive bus if its Request is not asserted.
ADDR has no options and is used to drive the address and command on the bus.
M_DATA is where data is transferred. If the master does not support fast back-to-back
transactions, the path to the ADDR state is not required.
The equations are correct from the protocol point of view. However, compilers may
give errors when they check all possible combinations. For example, because of
protocol, Comp cannot be asserted when FRAME# is deasserted. Comp indicates the
master is in the last data phase, and FRAME# must be deasserted for this to be true.
TURN_AR is where the master deasserts signals in preparation for tri-stating them. The
path to ADDR may be removed if the master does not do back-to-back transactions.
S_TAR could be implemented a number of ways. The state was chosen to clarify that
"state" needs to be remembered when the target asserts STOP#.
248
Revision 2.2
DR_BUS is used when GNT# has been asserted, and the master either is not prepared to
start a transaction (for address stepping) or has none pending. If address stepping is not
implemented, then the equation in goto DR_BUS that has "Step" may be removed and
the goto ADDR equation may also remove "Step".
If LOCK# is not supported by the master, the FREE and BUSY states may be removed.
These states are for the master to know the state of LOCK# when it desires to do a
locked transaction. The state machine simply checks for LOCK# being asserted. Once
asserted, it stays BUSY until FRAME# and LOCK# are both deasserted signifying that
LOCK# is now free.
249
Revision 2.2
250
Revision 2.2
Appendix C
Operating Rules
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DVDUHSODFHPHQWIRUWKHVSHFLILFDWLRQ7KLVDSSHQGL[RQO\FRYHUVWKHEDVLFSURWRFRODQG
UHTXLUHPHQWVFRQWDLQHGLQ&KDSWHU,WLVPHDQWWREHXVHGDVDQDLGRUTXLFNUHIHUHQFH
WRWKHEDVLFUXOHVDQGUHODWLRQVKLSVRIWKHSURWRFRO
When Signals are Stable
7KHIROORZLQJVLJQDOVDUHJXDUDQWHHGWREHVWDEOHRQDOOULVLQJHGJHVRICLK RQFH
UHVHWKDVFRPSOHWHGLOCK# IRDY#TRDY#FRAME#DEVSEL#STOP#
REQ#GNT#REQ64#ACK64#SERR#RQIDOOLQJHGJHRQO\DQGPERR#
$GGUHVV'DWDOLQHVDUHJXDUDQWHHGWREHVWDEOHDWWKHVSHFLILHGFORFNHGJHDVIROORZV
D $GGUHVVAD[31::00]DUHVWDEOHUHJDUGOHVVRIZKHWKHUVRPHDUHORJLFDOGRQ
W
FDUHVRQWKHILUVWFORFNWKDWVDPSOHVFRAME#DVVHUWHG
E $GGUHVVAD[63::32]DUHVWDEOHDQGYDOLGGXULQJWKHILUVWFORFNDIWHU REQ64#
DVVHUWLRQZKHQELWDGGUHVVLQJLVEHLQJXVHG6$&RUWKHILUVWWZRFORFNV
DIWHUREQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLVXVHG'$&:KHQREQ64#
LVGHDVVHUWHGAD[63::32]DUHSXOOHGXSE\WKHFHQWUDOUHVRXUFH
F 'DWDAD[31::00]DUHVWDEOHDQGYDOLGUHJDUGOHVVZKLFKE\WHODQHVDUHLQYROYHG
LQWKHWUDQVDFWLRQRQUHDGVZKHQTRDY#LVDVVHUWHGDQGRQZULWHVZKHQIRDY#
LVDVVHUWHG$WDQ\RWKHUWLPHWKH\PD\EHLQGHWHUPLQDWH7KHADOLQHVFDQQRW
FKDQJHXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHVRQFHIRDY#LVDVVHUWHGRQDZULWH
WUDQVDFWLRQRUTRDY#LVDVVHUWHGRQDUHDGWUDQVDFWLRQ
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UHDGVRUIRDY#LVDVVHUWHGRQZULWHV$WDQ\RWKHUWLPHWKH\PD\EH
LQGHWHUPLQDWH
H 'DWD6SHFLDOF\FOHFRPPDQGAD[31::00]DUHVWDEOHDQGYDOLGUHJDUGOHVV
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251
Revision 2.2
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Master Signals
$WUDQVDFWLRQVWDUWVZKHQFRAME#LVDVVHUWHGIRUWKHILUVWWLPH
7KHIROORZLQJJRYHUQFRAME#DQGIRDY#LQDOO3&,WUDQVDFWLRQV
D FRAME#DQGLWVFRUUHVSRQGLQJIRDY#GHILQHWKH%XV\,GOHVWDWHRIWKHEXV
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WKH,GOHVWDWH
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WUDQVDFWLRQ
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EHDVVHUWHGRQWKHILUVWFORFNHGJHWKDWFRAME#LVGHDVVHUWHG
G 2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLO
WKHFXUUHQWGDWDSKDVHFRPSOHWHV
e. The master must deassert IRDY# the clock after the completion of the last data
phase.
:KHQFRAME#DQGIRDY# DUHGHDVVHUWHGWKHWUDQVDFWLRQKDVHQGHG
:KHQWKHFXUUHQWWUDQVDFWLRQLVWHUPLQDWHGE\WKHWDUJHWSTOP#DVVHUWHGWKH
PDVWHUPXVWGHDVVHUWLWVREQ#VLJQDOEHIRUHUHSHDWLQJWKHWUDQVDFWLRQ$GHYLFH
FRQWDLQLQJDVLQJOHVRXUFHRIPDVWHUDFWLYLW\PXVWGHDVVHUWREQ#IRUDPLQLPXPRI
WZRFORFNVRQHEHLQJZKHQWKHEXVJRHVWRWKH,GOHVWDWHDWWKHHQGRIWKH
WUDQVDFWLRQZKHUHSTOP#ZDVDVVHUWHGDQGHLWKHUWKHFORFNEHIRUHRUWKHFORFN
DIWHUWKH,GOHVWDWH$GHYLFHFRQWDLQLQJPXOWLSOHVRXUFHVRIPDVWHUDFWLYLW\LV
SHUPLWWHGWRDOORZHDFKVRXUFHWRXVHWKHEXVZLWKRXWGHDVVHUWLQJREQ#HYHQLIRQH
RUPRUHVRXUFHVDUHWDUJHWWHUPLQDWHG+RZHYHUWKHGHYLFHPXVWGHDVVHUWREQ#IRU
252
Revision 2.2
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WHUPLQDWHGFDQEHUHSHDWHG
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UHTXHVWXQWLOLWFRPSOHWHVKRZHYHULWLVQRWUHTXLUHGWRUHSHDWWKHWUDQVDFWLRQZKHQ
WHUPLQDWHGZLWK'LVFRQQHFW
Target Signals
7KHIROORZLQJJHQHUDOUXOHVJRYHUQFRAME#IRDY#TRDY#DQGSTOP#ZKLOH
WHUPLQDWLQJWUDQVDFWLRQV
D $GDWDSKDVHFRPSOHWHVRQDQ\ULVLQJFORFNHGJHRQZKLFKIRDY#LVDVVHUWHG
DQGHLWKHUSTOP#RUTRDY#LVDVVHUWHG
E ,QGHSHQGHQWRIWKHVWDWHRISTOP#DGDWDWUDQVIHUWDNHVSODFHRQHYHU\ULVLQJ
HGJHRIFORFNZKHUHERWKIRDY#DQGTRDY#DUHDVVHUWHG
F 2QFHWKHWDUJHWDVVHUWVSTOP#LWPXVWNHHSSTOP#DVVHUWHGXQWLOFRAME#LV
GHDVVHUWHGZKHUHXSRQLWPXVWGHDVVHUWSTOP#
G 2QFHDWDUJHWKDVDVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL#
TRDY#RUSTOP#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV
H :KHQHYHUSTOP#LVDVVHUWHGWKHPDVWHUPXVWGHDVVHUWFRAME#DVVRRQDV
IRDY#FDQEHDVVHUWHG
I
,IQRWDOUHDG\GHDVVHUWHGTRDY#STOP#DQGDEVSEL#PXVWEHGHDVVHUWHG
WKHFORFNIROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVHDQGPXVWEHWULVWDWHG
WKHQH[WFORFN
$QDJHQWFODLPVWREHWKHWDUJHWRIWKHDFFHVVE\DVVHUWLQJDEVSEL#
DEVSEL#PXVWEHDVVHUWHGZLWKRUSULRUWRWKHHGJHDWZKLFKWKHWDUJHWHQDEOHVLWV
RXWSXWVTRDY#STOP#RURQDUHDGADOLQHV
2QFHDEVSEL#KDVEHHQDVVHUWHGLWFDQQRWEHGHDVVHUWHGXQWLOWKHODVWGDWDSKDVH
KDVFRPSOHWHGH[FHSWWRVLJQDO7DUJHW$ERUW
Data Phases
7KHVRXUFHRIWKHGDWDLVUHTXLUHGWRDVVHUWLWV[RDY#VLJQDOXQFRQGLWLRQDOO\ZKHQ
GDWDLVYDOLGIRDY#RQDZULWHWUDQVDFWLRQTRDY#RQDUHDGWUDQVDFWLRQ
'DWDLVWUDQVIHUUHGEHWZHHQPDVWHUDQGWDUJHWRQHDFKFORFNHGJHIRUZKLFKERWK
IRDY#DQGTRDY#DUHDVVHUWHG
/DVWGDWDSKDVHFRPSOHWHVZKHQ
D FRAME#LVGHDVVHUWHGDQGTRDY#LVDVVHUWHGQRUPDOWHUPLQDWLRQRU
E FRAME#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHGWDUJHWWHUPLQDWLRQRU
F FRAME#LVGHDVVHUWHGDQGWKHGHYLFHVHOHFWWLPHUKDVH[SLUHG0DVWHU$ERUW
RU
G DEVSEL#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG7DUJHW$ERUW
253
Revision 2.2
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RUSTOP#7KHWDUJHWFRPPLWVWR
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E\DVVHUWLQJTRDY#DQGQRWDVVHUWLQJSTOP#
E 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\DVVHUWLQJ
ERWKTRDY#DQGSTOP#
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DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY#
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HUURUFRQGLWLRQ7DUJHW$ERUWE\DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY#DQG
DEVSEL#
7KHWDUJHWKDVQRWFRPPLWWHGWRFRPSOHWHWKHFXUUHQWGDWDSKDVHZKLOHTRDY#DQG
STOP#DUHERWKGHDVVHUWHG7KHWDUJHWLVVLPSO\LQVHUWLQJZDLWVWDWHV
Arbitration
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D GNT#LVDVVHUWHGDQGWKHEXVLVLGOHFRAME#DQGIRDY#DUHGHDVVHUWHG
E GNT#LVDVVHUWHGLQWKHODVWGDWDSKDVHRIDWUDQVDFWLRQDQGWKHDJHQWLVVWDUWLQJD
QHZWUDQVDFWLRQXVLQJIDVWEDFNWREDFNWLPLQJFRAME#LVGHDVVHUWHGDQG
TRDY#RUSTOP#LVDVVHUWHGRUWKHWUDQVDFWLRQWHUPLQDWHVZLWK0DVWHU$ERUW
7KHDUELWHUPD\GHDVVHUWDQDJHQW
VGNT#RQDQ\FORFN
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D ,IGNT#LVGHDVVHUWHGDQGFRAME#LVDVVHUWHGRQWKHVDPHFORFNWKHEXV
WUDQVDFWLRQLVYDOLGDQGZLOOFRQWLQXH
E 2QHGNT#FDQEHGHDVVHUWHGFRLQFLGHQWZLWKDQRWKHUGNT# EHLQJDVVHUWHGLI
WKHEXVLVQRWLQWKH,GOHVWDWH2WKHUZLVHDRQHFORFNGHOD\LVUHTXLUHGEHWZHHQ
WKHGHDVVHUWLRQRIDGNT#DQGWKHDVVHUWLRQRIWKHQH[WGNT#RUHOVHWKHUHPD\
EHFRQWHQWLRQRQWKHADOLQHVDQGPAR
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VHUYLFHDKLJKHUSULRULW\PDVWHURULQUHVSRQVHWRWKHDVVRFLDWHGREQ#EHLQJ
GHDVVHUWHG
:KHQWKHDUELWHUDVVHUWVDQDJHQW
VGNT#DQGWKHEXVLVLQWKH,GOHVWDWHWKDWDJHQW
PXVWHQDEOHLWVAD[31::00]C/BE[3::0]#DQGRQHFORFNODWHUPARRXWSXWEXIIHUV
ZLWKLQHLJKW3&,FORFNVUHTXLUHGZKLOHWZRWKUHHFORFNVLVUHFRPPHQGHG
Latency
25. All targets are required to complete the initial data phase of a transaction (read or
write) within 16 clocks from the assertion of FRAME#. Host bus bridges have an
exception (refer to Section 3.5.1.1.).
56
Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win
arbitration at a given instant in time.
254
Revision 2.2
26. The target is required to complete a subsequent data phase within eight clocks from
the completion of the previous data phase.
27. A master is required to assert its IRDY# within eight clocks for any given data phase
(initial and subsequent).
Device Selection
28. A target must do a full decode before driving/asserting DEVSEL# or any other
target response signal.
29. A target must assert DEVSEL# (claim the transaction) before it is allowed to issue
any other target response.
30. In all cases except Target-Abort, once a target asserts DEVSEL# it must not
deassert DEVSEL# until FRAME# is deasserted (IRDY# is asserted) and the last
data phase has completed.
31. A PCI device is a target of a Type 0 configuration transaction (read or write) only if
its IDSEL is asserted, and AD[1::0] are “00” during the address phase of the
command.
Parity
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D 3DULW\LVFDOFXODWHGWKHVDPHRQDOO3&,WUDQVDFWLRQVUHJDUGOHVVRIWKHW\SHRU
IRUP
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33. Only the master of a corrupted data transfer is allowed to report parity errors to
software using mechanisms other than PERR# (i.e., requesting an interrupt or
asserting SERR#). In some cases, the master delegates this responsibility to a PCIto-PCI bridge handling posted memory write data. See the PCI-to-PCI Bridge
Architecture Specification for details.
255
Revision 2.2
256
Revision 2.2
Appendix D
Class Codes
7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&ODVV&RGHHQFRGLQJV7KLVOLVWPD\EHHQKDQFHGDW
DQ\WLPH7KH3&,6,*ZHESDJHVFRQWDLQWKHODWHVWYHUVLRQ&RPSDQLHVZLVKLQJWR
GHILQHDQHZHQFRGLQJVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHG
IRU6,*DVVLJQPHQW
Base Class
Meaning
00h
Device was built before Class Code
definitions were finalized
01h
Mass storage controller
02h
Network controller
03h
Display controller
04h
Multimedia device
05h
Memory controller
06h
Bridge device
07h
Simple communication controllers
08h
Base system peripherals
09h
Input devices
0Ah
Docking stations
0Bh
Processors
0Ch
Serial bus controllers
0Dh
Wireless controller
0Eh
Intelligent I/O controllers
0Fh
Satellite communication controllers
10h
Encryption/Decryption controllers
11h
Data acquisition and signal processing
controllers
12h - FEh
Reserved
FFh
Device does not fit in any defined classes
257
Revision 2.2
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EHIRUHWKH&ODVV&RGHILHOGZDVGHILQHG1RQHZGHYLFHVVKRXOGXVHWKLVYDOXHDQG
H[LVWLQJGHYLFHVVKRXOGVZLWFKWRDPRUHDSSURSULDWHYDOXHLISRVVLEOH
)RUFODVVFRGHVZLWKWKLVEDVHFODVVYDOXHWKHUHDUHWZRGHILQHGYDOXHVIRUWKHUHPDLQLQJ
ILHOGVDVVKRZQLQWKHWDEOHEHORZ$OORWKHUYDOXHVDUHUHVHUYHG
Base Class
Sub-Class
00h
Interface
00h
01h
00h
00h
Meaning
All currently implemented devices
except VGA-compatible devices
VGA-compatible device
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YDOXHVDUHGHILQHG7KH,'(FRQWUROOHUFODVVLVWKHRQO\RQHWKDWKDVDVSHFLILFUHJLVWHU
OHYHOSURJUDPPLQJLQWHUIDFHGHILQHG
Base Class
01h
Sub-Class
00h
01h
02h
03h
04h
80h
Interface
00h
xxh
00h
00h
00h
00h
Meaning
SCSI bus controller
IDE controller (see below)
Floppy disk controller
IPI bus controller
RAID controller
Other mass storage controller
)LJXUH'3URJUDPPLQJ,QWHUIDFH%\WH/D\RXWIRU,'(&RQWUROOHU&ODVV&RGH
7KH3&,6,*GRFXPHQW3&,,'(&RQWUROOHU6SHFLILFDWLRQFRPSOHWHO\GHVFULEHVWKH
OD\RXWDQGPHDQLQJRIELWVWKURXJKLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KH
GRFXPHQW%XV0DVWHU3URJUDPPLQJ,QWHUIDFHIRU,'($7$&RQWUROOHUVGHVFULEHVWKH
PHDQLQJRIELWLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KLVGRFXPHQWFDQEHREWDLQHGYLD
)$;E\FDOOLQJDQGUHTXHVWLQJGRFXPHQW
258
Revision 2.2
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7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIQHWZRUNFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV
DUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG
Base Class
02h
Sub-Class
00h
01h
02h
03h
04h
80h
Interface
00h
00h
00h
00h
00h
00h
Meaning
Ethernet controller
Token Ring controller
FDDI controller
ATM controller
ISDN controller
Other network controller
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7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGLVSOD\FRQWUROOHUV)RU9*$GHYLFHV6XE
&ODVVKWKHSURJUDPPLQJLQWHUIDFHE\WHLVGLYLGHGLQWRDELWILHOGWKDWLGHQWLILHV
DGGLWLRQDOYLGHRFRQWUROOHUFRPSDWLELOLWLHV$GHYLFHFDQVXSSRUWPXOWLSOHLQWHUIDFHVE\
XVLQJWKHELWPDSWRLQGLFDWHZKLFKLQWHUIDFHVDUHVXSSRUWHG)RUWKH;*$GHYLFHV6XE
&ODVVKRQO\WKHVWDQGDUG;*$LQWHUIDFHLVGHILQHG6XE&ODVVKLVIRUFRQWUROOHUV
WKDWKDYHKDUGZDUHVXSSRUWIRU'RSHUDWLRQVDQGDUHQRW9*$FRPSDWLEOH
Base Class
Sub-Class
Interface
00000000b
03h
00h
00000001b
01h
02h
80h
00h
00h
00h
Meaning
VGA-compatible controller. Memory
addresses 0A0000h through
0BFFFFh. I/O addresses 3B0h to
3BBh and 3C0h to 3DFh and all
aliases of these addresses.
8514-compatible controller -- 2E8h
and its aliases, 2EAh-2EFh
XGA controller
3D controller
Other display controller
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7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPXOWLPHGLDGHYLFHV6HYHUDOVXEFODVVYDOXHV
DUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG
Base Class
04h
Sub-Class
00h
01h
02h
80h
Interface
00h
00h
00h
00h
Meaning
Video device
Audio device
Computer telephony device
Other multimedia device
259
Revision 2.2
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7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPHPRU\FRQWUROOHUVUHIHUWR6HFWLRQ
6HYHUDOVXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHV
GHILQHG
Base Class
05h
Sub-Class
00h
01h
80h
Interface
00h
00h
00h
Meaning
RAM
Flash
Other memory controller
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7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIEULGJHGHYLFHV$3&,EULGJHLVDQ\3&,GHYLFH
WKDWPDSV3&,UHVRXUFHVPHPRU\RU,2IURPRQHVLGHRIWKHGHYLFHWRWKHRWKHU
6HYHUDOVXEFODVVYDOXHVDUHGHILQHG
Base Class
06h
Sub-Class
00h
01h
02h
03h
04h
Interface
00h
00h
00h
00h
00h
01h
05h
06h
07h
08h
80h
00h
00h
00h
xxh
00h
Meaning
Host bridge
ISA bridge
EISA bridge
MCA bridge
PCI-to-PCI bridge
Subtractive Decode PCI-to-PCI
bridge. This interface code identifies
the PCI-to-PCI bridge as a device that
supports subtractive decoding in
addition to all the currently defined
functions of a PCI-to-PCI bridge.
PCMCIA bridge
NuBus bridge
CardBus bridge
RACEway bridge (see below)
Other bridge device
5$&(ZD\LVDQ$16,VWDQGDUG$16,9,7$VZLWFKLQJIDEULF)RUWKH
3URJUDPPLQJ,QWHUIDFHELWV>@DUHUHVHUYHGUHDGRQO\DQGUHWXUQ]HURV%LWGHILQHV
WKHRSHUDWLRQPRGHDQGLVUHDGRQO\
7UDQVSDUHQWPRGH
(QGSRLQWPRGH
260
Revision 2.2
Base Class 07h
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIVLPSOHFRPPXQLFDWLRQVFRQWUROOHUV6HYHUDO
VXEFODVVYDOXHVDUHGHILQHGVRPHRIWKHVHKDYLQJVSHFLILFZHOONQRZQUHJLVWHUOHYHO
SURJUDPPLQJLQWHUIDFHV
Base Class
Sub-Class
Interface
00h
00h
01h
02h
03h
04h
05h
06h
00h
01h
02h
03h
FEh
01h
07h
02h
00h
00h
01h
03h
02h
03h
04h
80h
00h
Meaning
Generic XT-compatible serial
controller
16450-compatible serial controller
16550-compatible serial controller
16650-compatible serial controller
16750-compatible serial controller
16850-compatible serial controller
16950-compatible serial controller
Parallel port
Bi-directional parallel port
ECP 1.X compliant parallel port
IEEE1284 controller
IEEE1284 target device (not a
controller)
Multiport serial controller
Generic modem
Hayes compatible modem, 16450compatible interface (see below)
Hayes compatible modem, 16550compatible interface (see below)
Hayes compatible modem, 16650compatible interface (see below)
Hayes compatible modem, 16750compatible interface (see below)
Other communications device
)RU+D\HVFRPSDWLEOHPRGHPVWKHILUVWEDVHDGGUHVVUHJLVWHUDWRIIVHWKPDSVWKH
DSSURSULDWHFRPSDWLEOHLHHWFUHJLVWHUVHWIRUWKHVHULDOFRQWUROOHUDW
WKHEHJLQQLQJRIWKHPDSSHGVSDFH1RWHWKDWWKHVHUHJLVWHUVFDQEHHLWKHUPHPRU\RU
,2PDSSHGGHSHQGLQJZKDWNLQGRI%$5LVXVHG
261
Revision 2.2
%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIJHQHULFV\VWHPSHULSKHUDOV6HYHUDOVXEFODVV
YDOXHVDUHGHILQHGPRVWRIWKHVHKDYLQJDVSHFLILFZHOONQRZQUHJLVWHUOHYHO
SURJUDPPLQJLQWHUIDFH
Base Class
Sub-Class
00h
01h
08h
02h
03h
04h
80h
Interface
00h
01h
02h
10h
20h
00h
01h
02h
00h
01h
02h
00h
01h
00h
00h
Meaning
Generic 8259 PIC
ISA PIC
EISA PIC
I/O APIC interrupt controller (see
below)
I/O(x) APIC interrupt controller
Generic 8237 DMA controller
ISA DMA controller
EISA DMA controller
Generic 8254 system timer
ISA system timer.
EISA system timers (two timers)
Generic RTC controller
ISA RTC controller
Generic PCI Hot-Plug controller
Other system peripheral
)RU,2$3,&,QWHUUXSW&RQWUROOHUWKH%DVH$GGUHVV5HJLVWHUDWRIIVHW[LVXVHGWR
UHTXHVWDPLQLPXPRIE\WHVRIQRQSUHIHWFKDEOHPHPRU\7ZRUHJLVWHUVZLWKLQWKDW
VSDFHDUHORFDWHGDW%DVH[,26HOHFW5HJLVWHUDQG%DVH[,2:LQGRZ
5HJLVWHU)RUDIXOOGHVFULSWLRQRIWKHXVHRIWKHVHUHJLVWHUVUHIHUWRWKHGDWDVKHHWIRU
WKH,QWHO(%LQWKH3&,VHW(,6$%ULGJH'DWDERRN
262
Revision 2.2
%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRILQSXWGHYLFHV6HYHUDOVXEFODVVYDOXHVDUH
GHILQHG$UHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHLVGHILQHGIRUJDPHSRUWFRQWUROOHUV
Base Class
09h
Sub-Class
00h
01h
02h
03h
04h
80h
Interface
00h
00h
00h
00h
00h
10h
00h
Meaning
Keyboard controller
Digitizer (pen)
Mouse controller
Scanner controller
Gameport controller (generic)
Gameport controller (see below)
Other input controller
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Appendix E
System Transaction Ordering
Many programming tasks, especially those controlling intelligent peripheral devices
common in PCI systems, require specific events to occur in a specific order. If the
events generated by the program do not occur in the hardware in the order intended by
the software, a peripheral device may behave in a totally unexpected way. PCI
transaction ordering rules are written to give hardware the flexibility to optimize
performance by rearranging certain events that do not affect device operation, yet strictly
enforce the order of events that do affect device operation.
One performance optimization that PCI systems are allowed to do is the posting of
memory write transactions. Posting means the transaction is captured by an intermediate
agent; e.g., a bridge from one bus to another, so that the transaction completes at the
source before it actually completes at the intended destination. This allows the source to
proceed with the next operation while the transaction is still making its way through the
system to its ultimate destination.
While posting improves system performance, it complicates event ordering. Since the
source of a write transaction proceeds before the write actually reaches its destination,
other events that the programmer intended to happen after the write may happen before
the write. Many of the PCI ordering rules focus on posting buffers requiring them to be
flushed to keep this situation from causing problems.
If the buffer flushing rules are not written carefully, however, deadlock can occur. The
rest of the PCI transaction ordering rules prevent the system buses from deadlocking
when posting buffers must be flushed.
Simple devices do not post outbound transactions. Therefore, their requirements are
much simpler than those presented here for bridges. Refer to Section 3.2.5.1. for the
requirements for simple devices.
The focus of the remainder of this appendix is on a PCI-to-PCI bridge. This allows the
same terminology to be used to describe a transaction initiated on either interface and is
easier to understand. To apply these rules to other bridges, replace a PCI transaction
type with its equivalent transaction type of the host bus (or other specific bus). While
the discussion focuses on a PCI-to-PCI bridge, the concepts can be applied to all bridges.
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The ordering rules for a specific implementation may vary. This appendix covers the
rules for all accesses traversing a bridge assuming that the bridge can handle multiple
transactions at the same time in each direction. Simpler implementations are possible
but are not discussed here.
E.1 Producer - Consumer Ordering Model
The Producer - Consumer model for data movement between two masters is an example
of a system that would require this kind of ordering. In this model, one agent, the
Producer, produces or creates the data and another agent, the Consumer, consumes or
uses the data. The Producer and Consumer communicate between each other via a flag
and a status element. The Producer sets the flag when all the data has been written and
then waits for a completion status code. The Consumer waits until it finds the flag set,
then it resets the flag, consumes the data, and writes the completion status code. When
the Producer finds the completion status code, it clears it and the sequence repeats.
Obviously, the order in which the flag and data are written is important. If some of the
Producer’s data writes were posted, then without buffer-flushing rules it might be
possible for the Consumer to see the flag set before the data writes had completed. The
PCI ordering rules are written such that no matter which writes are posted, the Consumer
can never see the flag set and read the data until the data writes are finished. This
specification refers to this condition as “having a consistent view of data.” Notice that if
the Consumer were to pass information back to the Producer in addition to the status
code, the order of writing this additional information and the status code becomes
important, just as it was for the data and flag.
In practice, the flag might be a doorbell register in a device or it might be a mainmemory pointer to data located somewhere else in memory. And the Consumer might
signal the Producer using an interrupt or another doorbell register, rather than having the
Producer poll the status element. But in all cases, the basic need remains the same; the
Producer’s writes to the data area must complete before the Consumer observes that the
flag has been set and reads the data.
This model allows the data, the flag, the status element, the Producer, and the Consumer
to reside anywhere in the system. Each of these can reside on different buses and the
ordering rules maintain a consistent view of the data. For example, in Figure E-1, the
agent producing the data, the flag, and the status element reside on Bus 1, while the
actual data and the Consumer of the data both reside on Bus 0. The Producer writes the
last data and the PCI-to-PCI bridge between Bus 0 and 1 completes the access by posting
the data. The Producer of the data then writes the flag changing its status to indicate that
the data is now valid for the Consumer to use. In this case, the flag has been set before
the final datum has actually been written (to the final destination). PCI ordering rules
require that when the Consumer of the data reads the flag (to determine if the data is
valid), the read will cause the PCI-to-PCI bridge to flush the posted write data to the
final destination before completing the read. When the Consumer determines the data is
valid by checking the flag, the data is actually at the final destination.
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Consumer
Data
PCI Bus 0
PCI-PCI
Bridge
PCI Bus 1
Producer
Flag
Status
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The ordering rules lead to the same results regardless of where the Producer, the
Consumer, the data, the flag, and the status element actually reside. The data is always
at the final destination before the Consumer can read the flag. This is true even when all
five reside on different bus segments of the system. In one configuration, the data will
be forced to the final destination when the Consumer reads the flag. In another
configuration, the read of the flag occurs without forcing the data to its final destination;
however, the read request of the actual data pushes the final datum to the final
destination before completing the read.
A system may have multiple Producer-Consumer pairs operating simultaneously, with
different data - flag-status sets located all around the system. But since only one
Producer can write to a single data-flag set, there are no ordering requirements between
different masters. Writes from one master on one bus may occur in one order on one
bus, with respect to another master’s writes, and occur in another order on another bus.
In this case, the rules allow for some writes to be rearranged; for example, an agent on
Bus 1 may see Transaction A from a master on Bus 1 complete first, followed by
Transaction B from another master on Bus 0. An agent on Bus 0 may see Transaction B
complete first followed by Transaction A. Even though the actual transactions complete
in a different order, this causes no problem since the different masters must be
addressing different data-flag sets.
E.2. Summary of PCI Ordering Requirements
Following is a summary of the general PCI ordering requirements presented in
Section 3.2.5. These requirements apply to all PCI transactions, whether they are using
Delayed Transactions or not.
General Requirements
1. The order of a transaction is determined when it completes. Transactions terminated
with Retry are only requests and can be handled by the system in any order.
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2. Memory writes can be posted in both directions in a bridge. I/O and Configuration
writes are not posted. (I/O writes can be posted in the Host Bridge, but some
restrictions apply.) Read transactions (Memory, I/O, or Configuration) are not
posted.
3. Posted memory writes moving in the same direction through a bridge will complete
on the destination bus in the same order they complete on the originating bus.
4. Write transactions crossing a bridge in opposite directions have no ordering
relationship.
5. A read transaction must push ahead of it through the bridge any posted writes
originating on the same side of the bridge and posted before the read. Before the
read transaction can complete on its originating bus, it must pull out of the bridge
any posted writes that originated on the opposite side and were posted before the
read command completes on the read-destination bus.
6. A bridge can never make the acceptance (posting) of a memory write transaction as a
target contingent on the prior completion of a non-locked transaction as a master on
the same bus. Otherwise, a deadlock may occur. Bridges are allowed to refuse to
accept a memory write for temporary conditions which are guaranteed to be resolved
with time. A bridge can make the acceptance of a memory write transaction as a
target contingent on the prior completion of locked transaction as a master only if
the bridge has already established a locked operation with its intended target.
The following is a summary of the PCI ordering requirements specific to Delayed
Transactions, presented in Section 3.3.3.3.
Delayed Transaction Requirements
1. A target that uses Delayed Transactions may be designed to have any number of
Delayed Transactions outstanding at one time.
2. Only non-posted transactions can be handled as Delayed Transactions.
3. A master must repeat any transaction terminated with Retry since the target may be
using a Delayed Transaction.
4. Once a Delayed Request has been attempted on the destination bus, it must continue
to be repeated until it completes on the destination bus. Before it is attempted on the
destination bus, it is only a request and may be discarded at any time.
5. A Delayed Completion can only be discarded when it is a read from a prefetchable
region, or if the master has not repeated the transaction in 2 15 clocks.
6. A target must accept all memory writes addressed to it, even while completing a
request using Delayed Transaction termination.
7. Delayed Requests and Delayed Completions are not required to be kept in their
original order with respect to themselves or each other.
8. Only a Delayed Write Completion can pass a Posted Memory Write. A Posted
Memory Write must be given an opportunity to pass everything except another
Posted Memory Write.
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9. A single master may have any number of outstanding requests terminated with
Retry. However, if a master requires one transaction to be completed before another,
it cannot attempt the second one on PCI until the first one has completed.
E.3. Ordering of Requests
A transaction is considered to be a request when it is presented on the bus. When the
transaction is terminated with Retry, it is still considered a request. A transaction
becomes complete or a completion when data actually transfers (or is terminated with
Master-Abort or Target-Abort). The following discussion will refer to transactions as
being a request or completion depending on the success of the transaction.
A transaction that is terminated with Retry has no ordering relationship with any other
access. Ordering of accesses is only determined when an access completes (transfers
data). For example, four masters A, B, C, and D reside on the same bus segment and all
desire to generate an access on the bus. For this example, each agent can only request a
single transaction at a time and will not request another until the current access
completes. The order in which transactions complete are based on the algorithm of the
arbiter and the response of the target, not the order in which each agent’s REQ# signal
was asserted. Assuming that some requests are terminated with Retry, the order in
which they complete is independent of the order they were first requested. By changing
the arbiter’s algorithm, the completion of the transactions can be any sequence (i.e., A,
B, C, and then D or B, D, C, and then A, and so on). Because the arbiter can change the
order in which transactions are requested on the bus, and, therefore, the completion of
such transactions, the system is allowed to complete them in any order it desires. This
means that a request from any agent has no relationship with a request from any other
agent. The only exception to this rule is when LOCK# is used, which is described later.
Take the same four masters (A, B, C, and D) used in the previous paragraph and
integrate them onto a single piece of silicon (a multi-function device). For a multifunction device, the four masters operate independent of each other, and each function
only presents a single request on the bus for this discussion. The order their requests
complete is the same as if they where separate agents and not a multi-function device,
which is based on the arbitration algorithm. Therefore, multiple requests from a single
agent may complete in any order, since they have no relationship to each other.
Another device, not a multi-function device, has multiple internal resources that can
generate transactions on the bus. If these different sources have some ordering
relationship, then the device must ensure that only a single request is presented on the
bus at any one time. The agent must not attempt a subsequent transaction until the
previous transaction completes. For example, a device has two transactions to complete
on the bus, Transaction A and Transaction B and A must complete before B to preserve
internal ordering requirements. In this case, the master cannot attempt B until A has
completed.
The following example would produce inconsistent results if it were allowed to occur.
Transaction A is to a flag that covers data, and Transaction B accesses the actual data
covered by the flag. Transaction A is terminated with Retry, because the addressed
target is currently busy or resides behind a bridge. Transaction B is to a target that is
ready and will complete the request immediately. Consider what happens when these
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two transactions are allowed to complete in the wrong order. If the master allows
Transaction B to be presented on the bus after Transaction A was terminated with Retry,
Transaction B can complete before Transaction A. In this case, the data may be accessed
before it is actually valid. The responsibility to prevent this from occurring rests with
the master, which must block Transaction B from being attempted on the bus until
Transaction A completes. A master presenting multiple transactions on the bus must
ensure that subsequent requests (that have some relationship to a previous request) are
not presented on the bus until the previous request has completed. The system is
allowed to complete multiple requests from the same agent in any order. When a master
allows multiple requests to be presented on the bus without completing, it must repeat
each request independent of how any of the other requests complete.
E.4. Ordering of Delayed Transactions
A Delayed Transaction progresses to completion in three phases:
1. Request by the master
2. Completion of the request by the target
3. Completion of the transaction by the master
During the first phase, the master generates a transaction on the bus, the target decodes
the access, latches the information required to complete the access, and terminates the
request with Retry. The latched request information is referred to as a Delayed Request.
During the second phase, the target independently completes the request on the
destination bus using the latched information from the Delayed Request. The result of
completing the Delayed Request on the destination bus produces a Delayed Completion,
which consists of the latched information of the Delayed Request and the completion
status (and data if a read request). During the third phase, the master successfully rearbitrates for the bus and reissues the original request. The target decodes the request
and gives the master the completion status (and data if a read request). At this point, the
Delayed Completion is retired and the transaction has completed.
The number of simultaneous Delayed Transactions a bridge is capable of handling is
limited by the implementation and not by the architecture. Table E-1 represents the
ordering rules when a bridge in the system is capable of allowing multiple transactions to
proceed in each direction at the same time. Each column of the table represents an
access that was accepted by the bridge earlier, while each row represents a transaction
just accepted. The contents of the box indicate what ordering relationship the second
transaction must have to the first.
PMW - Posted Memory Write is a transaction that has completed on the originating bus
before completing on the destination bus and can only occur for Memory Write and
Memory Write and Invalidate commands.
DRR - Delayed Read Request is a transaction that must complete on the destination bus
before completing on the originating bus and can be an I/O Read, Configuration Read,
Memory Read, Memory Read Line, or Memory Read Multiple commands. As
mentioned earlier, once a request has been attempted on the destination bus, it must
continue to be repeated until it completes on the destination bus. Before it is attempted
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on the destination bus the DRR is only a request and may be discarded at any time to
prevent deadlock or improve performance, since the master must repeat the request later.
DWR - Delayed Write Request is a transaction that must complete on the destination bus
before completing on the originating bus and can be an I/O Write or Configuration Write
command. Note: Memory Write and Memory Write and Invalidate commands must be
posted (PMW) and not be completed as DWR. As mentioned earlier, once a request has
been attempted on the destination bus, it must continue to be repeated until it completes.
Before it is attempted on the destination bus, the DWR is only a request and may be
discarded at any time to prevent deadlock or improve performance, since the master
must repeat the request later.
DRC - Delayed Read Completion is a transaction that has completed on the destination
bus and is now moving toward the originating bus to complete. The DRC contains the
data requested by the master and the status of the target (normal, Master-Abort, TargetAbort, parity error, etc.).
DWC - Delayed Write Completion is a transaction that has completed on the destination
bus and is now moving toward the originating bus. The DWC does not contain the data
of the access, but only status of how it completed (Normal, Master-Abort, Target-Abort,
parity error, etc.). The write data has been written to the specified target.
No - indicates that the subsequent transaction is not allowed to complete before the
previous transaction to preserve ordering in the system. The four No boxes found in
column 2 prevent PMW data from being passed by other accesses and thereby maintain a
consistent view of data in the system.
Yes - indicates that the subsequent transaction must be allowed to complete before the
previous one or a deadlock can occur.
When blocking occurs, the PMW is required to pass the Delayed Transaction. If the
master continues attempting to complete Delayed Requests, it must be fair in attempting
to complete the PMW. There is no ordering violation when these subsequent
transactions complete before a prior transaction.
Yes/No - indicates that the bridge designer may choose to allow the subsequent
transaction to complete before the previous transaction or not. This is allowed since there
are no ordering requirements to meet or deadlocks to avoid. How a bridge designer
chooses to implement these boxes may have a cost impact on the bridge implementation
or performance impact on the system.
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Table E-1: Ordering Rules for a Bridge
Row pass Col.?
PMW
(Col 2)
DRR
(Col 3)
DWR
(Col 4)
DRC
(Col 5)
DWC
(Col 6)
PMW (Row 1)
No1
Yes5
Yes5
Yes7
Yes7
DRR (Row 2)
No2
Yes/No
Yes/No
Yes/No
Yes/No
DWR (Row 3)
No3
Yes/No
Yes/No
Yes/No
Yes/No
DRC (Row 4)
No4
Yes6
Yes6
Yes/No
Yes/No
DWC (Row 5)
Yes/No
Yes6
Yes6
Yes/No
Yes/No
Rule 1 - A subsequent PMW cannot pass a previously accepted PMW.
(Col 2, Row 1)
Posted Memory write transactions must complete in the order they are
received. If the subsequent write is to the flag that covers the data, the
Consumer may use stale data if write transactions are allowed to pass each
other.
Rule 2 - A read transaction must push posted write data to maintain ordering.
(Col 2, Row 2)
For example, a memory write to a location followed by an immediate
memory read of the same location returns the new value (refer to
Section 3.10, item 6, for possible exceptions). Therefore, a memory read
cannot pass posted write data. An I/O read cannot pass a PMW, because the
read may be ensuring the write data arrives at the final destination.
Rule 3 - A non-postable write transaction must push posted write data to maintain
ordering. (Col 2, Row 3)
A Delayed Write Request may be the flag that covers the data previously
written (PMW), and, therefore, the write flag cannot pass the data that it
potentially covers.
Rule 4 - A read transaction must pull write data back to the originating bus of the
read transaction. (Col 2, Row 4)
For example, the read of a status register of the device writing data to
memory must not complete before the data is pulled back to the originating
bus; otherwise, stale data may be used.
Rule 5 - A Posted Memory Write must be allowed to pass a Delayed Request (read
or write) to avoid deadlocks. (Col 3 and Col 4, Row 1)
A deadlock can occur when bridges that support Delayed Transactions are
used with bridges that do not support Delayed Transactions. Referring to
Figure E-2, a deadlock can occur when Bridge Y (using Delayed
Transactions) is between Bridges X and Z (designed to a previous version of
this specification and not using Delayed Transactions). Master 1 initiates a
read to Target 1 that is forwarded through Bridge X and is queued as a
Delayed Request in Bridge Y. Master 3 initiates a read to Target 3 that is
forwarded through Bridge Z and is queued as a Delayed Request in Bridge
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Y. After Masters 1 and 3 are terminated with Retry, Masters 2 and 4 begin
memory write transactions of a long duration addressing Targets 2 and 4
respectively, which are posted in the write buffers of Bridges X and Z
respectively. When Bridge Y attempts to complete the read in either
direction, Bridges X and Z must flush their posted write buffers before
allowing the Read Request to pass through it.
If the posted write buffers of Bridges X and Z are larger than those of Bridge
Y, Bridge Y’s buffers will fill. If posted write data is not allowed to pass the
DRR, the system will deadlock. Bridge Y cannot discard the read request
since it has been attempted, and it cannot accept any more write data until
the read in the opposite direction is completed. Since this condition exists in
both directions, neither DRR can complete because the other is blocking the
path. Therefore, the PMW data is required to pass the DRR when the DRR
blocks forward progress of PMW data.
The same condition exists when a DWR sits at the head of both queues,
since some old bridges also require the posting buffers to be flushed on a
non-posted write cycle.
Rule 6 – A Delayed Completion (read or write) must be allowed to pass a Delayed
Request (read or write) to avoid deadlocks. (Cols 3 and 4, Rows 4 and 5)
A deadlock can occur when two bridges that support Delayed Transactions
are requesting accesses to each other. The common PCI bus segment is on
the secondary bus of Bridge A and the primary bus for Bridge B. If neither
bridge allows Delayed Completions to pass the Delayed Requests, neither
can make progress.
For example, suppose Bridge A’s request to Bridge B completes on Bridge
B’s secondary bus, and Bridge B’s request completes on Bridge A’s primary
bus. Bridge A’s completion is now behind Bridge B’s request and Bridge
B’s completion is behind Bridge A’s request. If neither bridge allows
completions to pass the requests, then a deadlock occurs because neither
master can make progress.
Rule 7 - A Posted Memory Write must be allowed to pass a Delayed Completion
(read or write) to avoid deadlocks. (Col 5 and Col 6, Row 1)
As in the example for Rule 5, another deadlock can occur in the system
configuration in Figure E-2. In this case, however, a DRC sits at the head of
the queues in both directions of Bridge Y at the same time. Again the old
bridges (X and Z) contain posted write data from another master. The
problem in this case, however, is that the read transaction cannot be repeated
until all the posted write data is flushed out of the old bridge and the master
is allowed to repeat its original request. Eventually, the new bridge cannot
accept any more posted data because its internal buffers are full and it
cannot drain them until the DRC at the other end completes. When this
condition exists in both directions, neither DRC can complete because the
other is blocking the path. Therefore, the PMW data is required to pass the
DRC when the DRC blocks forward progress of PMW data.
The same condition exists when a DWC sits at the head of both queues.
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Transactions that have no ordering constraints
Some transactions enqueued as Delayed Requests or Delayed Completions have no
ordering relationship with any other Delayed Requests or Delayed Completions. The
designer can (for performance or cost reasons) allow or disallow Delayed Requests to
pass other Delayed Requests and Delayed Completions that were previously enqueued.
Delayed Requests can pass other Delayed Requests (Cols 3 and 4, Rows 2 and 3).
Since Delayed Requests have no ordering relationship with other Delayed
Requests, these four boxes are don’t cares.
Delayed Requests can pass Delayed Completions (Col 5 and 6, Rows 2 and 3).
Since Delayed Requests have no ordering relationship with Delayed
Completions, these four boxes are don’t cares.
Delayed Completions can pass other Delayed Completions (Col 5 and 6, Rows 4 and
5).
Since Delayed Completions have no ordering relationship with other Delayed
Completions, these four boxes are don’t cares.
Delayed Write Completions can pass posted memory writes or be blocked by them
(Col 2, Row 5).
If the DWC is allowed to pass a PMW or if it remains in the same order,
there is no deadlock or data inconsistencies in either case. The DWC data
and the PMW data are moving in opposite directions, initiated by masters
residing on different buses accessing targets on different buses.
Target 1
Target 2
Master 3
Master 4
PCI Bus P
PCI-PCI
PCI-PCI
PCI-PCI
Bridge X
Bridge Y
Bridge Z
(pre 2.1)
(Rev. 2.1)
(pre 2.1)
PCI Bus N
Master 1
Master 2
Target 3
Target 4
Figure E-2: Example System with PCI-to-PCI Bridges
E.5. Delayed Transactions and LOCK#
The bridge is required to support LOCK# when a transaction is initiated on its primary
bus (and is using the lock protocol), but is not required to support LOCK# on
transactions that are initiated on its secondary bus. If a locked transaction is initiated on
the primary bus and the bridge is the target, the bridge must adhere to the lock semantics
276
Revision 2.2
defined by this specification. The bridge is required to complete (push) all PMWs
(accepted from the primary bus) onto the secondary bus before attempting the lock on
the secondary bus. The bridge may discard any requests enqueued, allow the locked
transaction to pass the enqueued requests, or simply complete all enqueued transactions
before attempting the locked transaction on the secondary interface. Once a locked
transaction has been enqueued by the bridge, the bridge cannot accept any other
transaction from the primary interface until the lock has completed except for a
continuation of the lock itself by the lock master. Until the lock is established on the
secondary interface, the bridge is allowed to continue enqueuing transactions from the
secondary interface, but not the primary interface. Once lock has been established on the
secondary interface, the bridge cannot accept any posted write data moving toward the
primary interface until LOCK# has been released (FRAME# and LOCK# deasserted on
the same rising clock edge). (In the simplest implementation, the bridge does not accept
any other transactions in either direction once lock is established on the secondary bus,
except for locked transactions from the lock master.) The bridge must complete PMW,
DRC, and DWC transactions moving toward the primary bus before allowing the locked
access to complete on the originating bus. The preceding rules are sufficient for
deadlock free operation. However, an implementation may be more or less restrictive,
but, in all cases must ensure deadlock-free operation.
E.6. Error Conditions
A bridge is free to discard data or status of a transaction that was completed using
Delayed Transaction termination when the master has not repeated the request within 2 10
PCI clocks (about 30 µs at 33 MHz). However, it is recommended that the bridge not
discard the transaction until 2 15 PCI clocks (about 983 µs at 33 MHz) after it acquired
the data or status. The shorter number is useful in a system where a master designed to a
previous version of this specification frequently fails to repeat a transaction exactly as
first requested. In this case, the bridge may be programmed to discard the abandoned
Delayed Completion early and allow other transactions to proceed. Normally, however,
the bridge would wait the longer time, in case the repeat of the transaction is being
delayed by another bridge or bridges designed to a previous version of this specification
that did not support Delayed Transactions.
When this timer (referred to as the Discard Timer) expires, the device is required to
discard the data; otherwise, a deadlock may occur.
Note: When the transaction is discarded, data may be destroyed. This
occurs when the discarded Delayed Completion is a read to a nonprefetchable region.
When the Discard Timer expires, the device may choose to report or ignore the error.
When the data is prefetchable, it is recommended that the device ignore the error since
system integrity is not affected. However, when the data is not prefetchable, it is
recommended that the device report the error to its device driver since system integrity is
affected. A bridge may assert SERR# since it typically does not have a device driver.
277
Revision 2.2
278
Revision 2.2
Appendix F
Exclusive Accesses
7KHXVHRILOCK#LVRQO\DOORZHGWREHVXSSRUWHGE\DKRVWEXVEULGJHD3&,WR3&,
EULGJHRUDQH[SDQVLRQEXVEULGJH,QHDUOLHUYHUVLRQVRIWKLVVSHFLILFDWLRQRWKHUGHYLFHV
ZHUHDOORZHGWRLQLWLDWHDQGUHVSRQGWRH[FOXVLYHDFFHVVHVXVLQJLOCK#+RZHYHUWKH
XVHIXOQHVVRIDKDUGZDUHEDVHGORFNPHFKDQLVPKDVGLPLQLVKHGDQGLVRQO\XVHIXOWR
SUHYHQWDGHDGORFNRUWRSURYLGHEDFNZDUGFRPSDWLELOLW\7KHUHIRUHDOORWKHUGHYLFHV
DUHUHTXLUHGWRLJQRUHLOCK#
$KRVWEXVEULGJHFDQRQO\LQLWLDWHDQH[FOXVLYHDFFHVVWRSUHYHQWDGHDGORFNDVGHVFULEHG
LQ6HFWLRQLWHPRUWRSURYLGHEDFNZDUGFRPSDWLELOLW\WRDQH[SDQVLRQEXVEULGJH
WKDWVXSSRUWVH[FOXVLYHDFFHVV$KRVWEXVEULGJHFDQRQO\KRQRUDQH[FOXVLYHDFFHVVDV
DWDUJHWZKHQSURYLGLQJFRPSDWLELOLW\WRDQDFFHVVLQLWLDWHGE\DQH[SDQVLRQEXVEULGJH
WKDWVXSSRUWVH[FOXVLYHDFFHVVHV1RRWKHUDJHQWFDQLQLWLDWHDORFNHGDFFHVVWRWKH+RVW
%XVEULGJH
$3&,WR3&,EULGJHLVRQO\DOORZHGWRSURSDJDWHDQH[FOXVLYHDFFHVVIURPLWVSULPDU\
EXVWRLWVVHFRQGDU\EXVDQGLVQHYHUDOORZHGWRLQLWLDWHDQH[FOXVLYHDFFHVVRILWVRZQ
LQLWLDWLYH$3&,WR3&,EULGJHLVUHTXLUHGWRLJQRUHLOCK#ZKHQDFWLQJDVDWDUJHWRQ
LWVVHFRQGDU\LQWHUIDFH
$QH[SDQVLRQEXVEULGJHLVRQO\DOORZHGWRLQLWLDWHDQH[FOXVLYHDFFHVVWRSURYLGH
EDFNZDUGFRPSDWLELOLW\7KLVPHDQVWKDWWKHH[SDQVLRQEXVVXSSRUWVDKDUGZDUHEDVHG
H[FOXVLYHDFFHVVPHFKDQLVPLH(,6$DQGQRW,6$7KHH[SDQVLRQEXVEULGJHFDQ
KRQRUDQH[FOXVLYHDFFHVVDVDWDUJHWZKHQVXSSRUWHGE\WKHH[SDQVLRQEXVRWKHUZLVH
LOCK#KDVQRPHDQLQJWRWKHEULGJH
7KHUHPDLQGHURIWKLVFKDSWHULVRQO\DSSOLFDEOHWRDGHYLFHWKDWLVDOORZHGWRVXSSRUW
LOCK#1RWHH[LVWLQJVRIWZDUHWKDWGRHVQRWVXSSRUWWKH3&,ORFNXVDJHUXOHVKDVWKH
SRWHQWLDORIQRWZRUNLQJFRUUHFWO\6RIWZDUHLVQRWDOORZHGWRXVHDQH[FOXVLYHDFFHVVWR
GHWHUPLQHLIDGHYLFHLVSUHVHQW
F.1. Exclusive Accesses on PCI
3&,SURYLGHVDQH[FOXVLYHDFFHVVPHFKDQLVPZKLFKDOORZVQRQH[FOXVLYHDFFHVVHVWR
SURFHHGLQWKHIDFHRIH[FOXVLYHDFFHVVHV7KLVDOORZVDPDVWHUWRKROGDKDUGZDUHORFN
DFURVVVHYHUDODFFHVVHVZLWKRXWLQWHUIHULQJZLWKQRQH[FOXVLYHGDWDWUDQVIHUVXFKDVUHDO
WLPHYLGHREHWZHHQWZRGHYLFHVRQWKHVDPHEXVVHJPHQW7KHPHFKDQLVPLVEDVHGRQ
279
Revision 2.2
ORFNLQJRQO\WKH3&,UHVRXUFHWRZKLFKWKHRULJLQDOORFNHGDFFHVVZDVWDUJHWHGDQGLV
FDOOHGDUHVRXUFHORFN
LOCK#LQGLFDWHVZKHWKHUWKHPDVWHUGHVLUHVWKHFXUUHQWWUDQVDFWLRQWRFRPSOHWHDVDQ
H[FOXVLYHDFFHVVRUQRW&RQWURORILOCK#LVREWDLQHGXQGHULWVRZQSURWRFROLQ
FRQMXQFWLRQZLWKGNT#5HIHUWR6HFWLRQ)IRUGHWDLOV0DVWHUVDQGWDUJHWVQRW
LQYROYHGLQWKHH[FOXVLYHDFFHVVDUHDOORZHGWRSURFHHGZLWKQRQH[FOXVLYHDFFHVVHV
ZKLOHDQRWKHUPDVWHUUHWDLQVRZQHUVKLSRILOCK#+RZHYHUZKHQFRPSDWLELOLW\
GLFWDWHVWKHDUELWHUFDQRSWLRQDOO\JUDQWWKHDJHQWWKDWRZQVLOCK#H[FOXVLYHDFFHVVWR
WKHEXVXQWLOLOCK#LVUHOHDVHG7KLVLVUHIHUUHGWRDVFRPSOHWHEXVORFNDQGLV
GHVFULEHGLQ6HFWLRQ))RUDUHVRXUFHORFNWKHWDUJHWRIWKHDFFHVVJXDUDQWHHV
H[FOXVLYLW\
7KHIROORZLQJSDUDJUDSKVGHVFULEHWKHEHKDYLRURIDPDVWHUDQGDWDUJHWIRUDORFNHG
RSHUDWLRQ7KHUXOHVRILOCK#ZLOOEHVWDWHGIRUERWKWKHPDVWHUDQGWDUJHW$GHWDLOHG
GLVFXVVLRQRIKRZWRVWDUWFRQWLQXHDQGFRPSOHWHDQH[FOXVLYHDFFHVVRSHUDWLRQIROORZV
WKHGLVFXVVLRQRIWKHUXOHV$GLVFXVVLRQRIKRZDWDUJHWEHKDYHVZKHQLWVXSSRUWVD
UHVRXUFHORFNZLOOIROORZWKHGHVFULSWLRQRIWKHEDVLFORFNPHFKDQLVP7KHFRQFOXGLQJ
VHFWLRQZLOOGLVFXVVKRZWRLPSOHPHQWDFRPSOHWHEXVORFN
0DVWHUUXOHVIRUVXSSRUWLQJLOCK#
$PDVWHUFDQDFFHVVRQO\DVLQJOHUHVRXUFHGXULQJDORFNRSHUDWLRQ
7KHILUVWWUDQVDFWLRQRIDORFNRSHUDWLRQPXVWEHDPHPRU\UHDGWUDQVDFWLRQ
LOCK#PXVWEHDVVHUWHGWKHFORFNIROORZLQJWKHDGGUHVVSKDVHDQGNHSWDVVHUWHG
WRPDLQWDLQFRQWURO
LOCK#PXVWEHUHOHDVHGLIWKHLQLWLDOWUDQVDFWLRQRIWKHORFNUHTXHVWLVWHUPLQDWHG
ZLWK5HWU\/RFNZDVQRWHVWDEOLVKHG
LOCK#PXVWEHUHOHDVHGZKHQHYHUDQDFFHVVLVWHUPLQDWHGE\7DUJHW$ERUWRU
0DVWHU$ERUW
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RQHFORFNZKLOHWKHEXVLVLQWKH,GOHVWDWH
57
In previous versions of this specification, a minimum of 16 bytes (naturally aligned) was considered the
lock resource. A device was permitted to lock its entire memory address space. This definition still applies
for an upstream locked access to main memory. For downstream locked access, a resource is the PCI-toPCI bridge or the Expansion Bus bridge that is addressed by the locked operation.
58
For a SAC, this is the clock after the address phase. For a DAC, this occurs the clock after the first
address phase.
59
Once lock has been established, the master retains ownership of LOCK# when terminated with Retry or
Disconnect.
60
Consecutive refers to back-to-back locked operations and not a continuation of the current locked
operation.
280
Revision 2.2
7DUJHW5XOHVIRUVXSSRUWLQJLOCK#
$EULGJHDFWLQJDVDWDUJHWRIDQDFFHVVORFNVLWVHOIZKHQLOCK#LVGHDVVHUWHG
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2QFHORFNLVHVWDEOLVKHGDEULGJHUHPDLQVORFNHGXQWLOERWKFRAME#DQG
LOCK#DUHVDPSOHGGHDVVHUWHGUHJDUGOHVVRIKRZWKHWUDQVDFWLRQLVWHUPLQDWHG
7KHEULGJHLVQRWDOORZHGWRDFFHSWDQ\QHZUHTXHVWVIURPHLWKHULQWHUIDFHZKLOHLW
LVLQDORFNHGFRQGLWLRQH[FHSWIURPWKHRZQHURILOCK#
F.2. Starting an Exclusive Access
:KHQDQDJHQWQHHGVWRGRDQH[FOXVLYHRSHUDWLRQLWFKHFNVWKHLQWHUQDOO\WUDFNHGVWDWH
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LOCK#KDVEHHQREWDLQHG7KHPDVWHULVIUHHWRSHUIRUPDQH[FOXVLYHRSHUDWLRQZKHQ
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61
A locked operation is established when LOCK# is deasserted during the address phase, asserted the
following clock, and data is transferred during the current transaction.
281
Revision 2.2
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282
Revision 2.2
$EULGJHDFWLQJDVDWDUJHWWKDWVXSSRUWVH[FOXVLYHDFFHVVHVPXVWVDPSOHLOCK#ZLWK
WKHDGGUHVVDQGRQDVXEVHTXHQWFORFN,IWKHEULGJHSHUIRUPVPHGLXPRUVORZGHFRGHLW
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FORFNIROORZLQJWKHILUVWDGGUHVVSKDVHDQGLVIUHHWRUHVSRQGWRRWKHUUHTXHVWV
F.3. Continuing an Exclusive Access
)LJXUH)VKRZVDPDVWHUFRQWLQXLQJDQH[FOXVLYHDFFHVV+RZHYHUWKLVDFFHVVPD\RU
PD\QRWFRPSOHWHWKHH[FOXVLYHRSHUDWLRQ:KHQWKHPDVWHULVJUDQWHGDFFHVVWRWKHEXV
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WUDQVDFWLRQ
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FRPSOHWLQJDQH[FOXVLYHDFFHVV
CLK
1
2
3
4
5
FRAME#
Release
LOCK#
AD
Continue
ADDRESS
DATA
IRDY#
TRDY#
DEVSEL#
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F.4. Accessing a Locked Agent
)LJXUH)VKRZVDPDVWHUWU\LQJDQRQH[FOXVLYHDFFHVVWRDORFNHGDJHQW:KHQ
LOCK#LVDVVHUWHGGXULQJWKHDGGUHVVSKDVHDQGLIWKHWDUJHWLVORFNHGIXOOORFNRU
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283
Revision 2.2
CLK
1
2
3
4
5
FRAME#
(driven low by master holding lock)
LOCK#
AD
ADDRESS
DATA
IRDY#
TRDY#
STOP#
DEVSEL#
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F.5. Completing an Exclusive Access
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ZLOODFFHSWWKHUHTXHVWDQGWKHQUHDVVHUWHGXQWLOWKHH[FOXVLYHDFFHVVWHUPLQDWHV
VXFFHVVIXOO\7KHPDVWHUPD\GHDVVHUWLOCK#DWDQ\WLPHZKHQWKHH[FOXVLYHRSHUDWLRQ
KDVFRPSOHWHG+RZHYHULWLVUHFRPPHQGHGEXWQRWUHTXLUHGWKDWLOCK#EH
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RIWKHORFNHGRSHUDWLRQ5HOHDVLQJLOCK# DWDQ\RWKHUWLPHPD\UHVXOWLQDVXEVHTXHQW
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FRAME#DQGLOCK#DUHERWKGHDVVHUWHGRQWKHVDPHFORFN
F.7. Complete Bus Lock
7KH3&,UHVRXUFHORFNFDQEHFRQYHUWHGLQWRDFRPSOHWHEXVORFNE\KDYLQJWKHDUELWHU
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ORFNHGVHTXHQFHLVWHUPLQDWHGZLWK5HWU\WKHPDVWHUPXVWGHDVVHUWERWKREQ#DQG
LOCK#,IWKHILUVWDFFHVVFRPSOHWHVQRUPDOO\WKHFRPSOHWHEXVORFNKDVEHHQ
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WKHEXVWRDQRWKHUDJHQWZKHQWKHFRPSOHWHEXVORFNZDVEHLQJHVWDEOLVKHGWKHDUELWHU
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FRPSOHWHEXVORFNPD\KDYHDVLJQLILFDQWLPSDFWRQWKHSHUIRUPDQFHRIWKHV\VWHP
SDUWLFXODUO\WKHYLGHRVXEV\VWHP$OOQRQH[FOXVLYHDFFHVVHVZLOOQRWSURFHHGZKLOHD
FRPSOHWHEXVORFNRSHUDWLRQLVLQSURJUHVV
284
Revision 2.2
Appendix G
I/O Space Address
Decoding for Legacy Devices
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,IWKHGHYLFHGRHVQRWRZQDOOE\WHVZLWKLQD':25'RIDOHJDF\,2UDQJHLWLV
UHTXLUHGWRXVHAD[1::0]WRFRPSOHWHWKHGHFRGHEHIRUHFODLPLQJWKHDFFHVVE\DVVHUWLQJ
DEVSEL#,IDOHJDF\IXQFWLRQLVDGGUHVVHGE\DQ,2WUDQVDFWLRQEXWGRHVQRWRZQDOO
E\WHVEHLQJDFFHVVHGLQWKH':25'LWLVUHTXLUHGWRWHUPLQDWHWKHWUDQVDFWLRQZLWK
7DUJHW$ERUW$QH[SDQVLRQEXVEULGJHLVJUDQWHGDQH[FHSWLRQWRWKLVUHTXLUHPHQWZKHQ
SHUIRUPLQJVXEWUDFWLYHGHFRGH7KHEULGJHLVSHUPLWWHGWRDVVXPHWKDWDOOE\WHVZLWKLQ
WKH':25'EHLQJDGGUHVVHGUHVLGHRQWKHH[SDQVLRQEXV7KLVPHDQVWKDWWKHEULGJHLV
QRWUHTXLUHGWRFKHFNWKHHQFRGLQJRIAD[1::0]DQGWKHE\WHHQDEOHVEHIRUHSDVVLQJWKH
UHTXHVWWRWKHH[SDQVLRQEXVWRFRPSOHWH
285
Revision 2.2
286
Revision 2.2
Appendix H
Capability IDs
7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&DSDELOLW\,'V(DFKGHILQHGFDSDELOLW\PXVWKDYHD
3&,6,*DVVLJQHG,'FRGH7KHVHFRGHVDUHDVVLJQHGDQGKDQGOHGPXFKOLNHWKH&ODVV
&RGHV
6HFWLRQRIWKLVVSHFLILFDWLRQSURYLGHVDIXOOGHVFULSWLRQRIWKH([WHQGHG&DSDELOLWLHV
/LVWIRU3&,GHYLFHV
7DEOH+&DSDELOLW\,'V
ID
Capability
0
Reserved
1
PCI Power Management Interface – This capability structure provides a
standard interface to control power management features in a PCI
device. It is fully documented in the PCI Power Management Interface
Specification. This document is available from the PCI SIG as
described in Chapter 1 of this specification.
2
AGP – This capability structure identifies a controller that is capable of
using Accelerated Graphics Port features. Full documentation can be
found in the Accelerated Graphics Port Interface Specification. This is
available at http://www.agpforum.org.
3
VPD – This capability structure identifies a device that supports Vital
Product Data. Full documentation of this feature can be found in
Section 6.4. and Appendix I of this specification.
287
Revision 2.2
7DEOH+&DSDELOLW\,'VFRQWLQXHG
ID
288
Capability
4
6ORW,GHQWLILFDWLRQ–7KLVFDSDELOLW\VWUXFWXUHLGHQWLILHVDEULGJHWKDW
SURYLGHVH[WHUQDOH[SDQVLRQFDSDELOLWLHV)XOOGRFXPHQWDWLRQRIWKLV
IHDWXUHFDQEHIRXQGLQWKH3&,WR3&,%ULGJH$UFKLWHFWXUH
6SHFLILFDWLRQ7KLVGRFXPHQWLVDYDLODEOHIURPWKH3&,6,*DV
GHVFULEHGLQ&KDSWHURIWKLVVSHFLILFDWLRQ
5
Message Signaled Interrupts – This capability VWUXFWXUHidentifies a PCI
function that can do message signaled interrupt delivery as defined in
Section 6.8. of this specification.
6
CompactPCI Hot Swap – This capability VWUXFWXUHprovides a standard
interface to control and sense status within a device that supports Hot
Swap insertion and extraction in a CompactPCI system. This capability
is documented in the CompactPCI Hot Swap Specification PICMG 2.1,
R1.0 available at http://www.picmg.org.
7-255
Reserved
Revision 2.2
Appendix I
Vital Product Data
9LWDO3URGXFW'DWD93'LVLQIRUPDWLRQWKDWXQLTXHO\LGHQWLILHVKDUGZDUHDQG
SRWHQWLDOO\VRIWZDUHHOHPHQWVRIDV\VWHP7KH93'FDQSURYLGHWKHV\VWHPZLWK
LQIRUPDWLRQRQYDULRXV)LHOG5HSODFHDEOH8QLWVVXFKDVSDUWQXPEHUVHULDOQXPEHUDQG
RWKHUGHWDLOHGLQIRUPDWLRQ7KHREMHFWLYHIURPDV\VWHPSRLQWRIYLHZLVWRPDNHWKLV
LQIRUPDWLRQDYDLODEOHWRWKHV\VWHPRZQHUDQGVHUYLFHSHUVRQQHO6XSSRUWRI93'LV
RSWLRQDO
93'UHVLGHVLQDVWRUDJHGHYLFHIRUH[DPSOHDVHULDO((3520LQD3&,GHYLFH
$FFHVVWRWKH93'LVSURYLGHGXVLQJWKH&DSDELOLWLHV/LVWLQ&RQILJXUDWLRQ6SDFH7KH
93'FDSDELOLW\VWUXFWXUHKDVWKHIROORZLQJIRUPDW
31 30
F
16
VPD Address
15
8
Pointer to Next ID
7
0
ID = 03h
VPD Data
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5HJLVWHU)LHOG'HVFULSWLRQV
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3RLQWHUWR1H[W,'²3RLQWHUWRWKHQH[WFDSDELOLW\VWUXFWXUHRUKLIWKLVLVWKHODVW
VWUXFWXUHLQWKH&DSDELOLW\/LVW7KLVLVDUHDGRQO\ILHOG
93'$GGUHVV²':25'DOLJQHGE\WHDGGUHVVRIWKH93'WREHDFFHVVHG7KHUHJLVWHU
LVUHDGZULWHDQGWKHLQLWLDOYDOXHDWSRZHUXSLVLQGHWHUPLQDWH
)²$IODJXVHGWRLQGLFDWHZKHQWKHWUDQVIHURIGDWDEHWZHHQWKH93''DWDUHJLVWHUDQG
WKHVWRUDJHFRPSRQHQWLVFRPSOHWHG7KHIODJUHJLVWHULVZULWWHQZKHQWKH93'$GGUHVV
UHJLVWHULVZULWWHQ7RUHDG93'LQIRUPDWLRQD]HURLVZULWWHQWRWKHIODJUHJLVWHUZKHQ
WKHDGGUHVVLVZULWWHQWRWKH93'$GGUHVVUHJLVWHU7KHKDUGZDUHGHYLFHZLOOVHWWKHIODJ
WRDRQHZKHQE\WHVRIGDWDIURPWKHVWRUDJHFRPSRQHQWKDYHEHHQWUDQVIHUUHGWRWKH
93''DWDUHJLVWHU6RIWZDUHFDQPRQLWRUWKHIODJDQGDIWHULWLVVHWWRDRQHUHDGWKH
93'LQIRUPDWLRQIURPWKH93''DWDUHJLVWHU,IHLWKHUWKH93'$GGUHVVRU93''DWD
UHJLVWHULVZULWWHQSULRUWRWKHIODJELWEHLQJVHWWRDRQHWKHUHVXOWVRIWKHRULJLQDOUHDG
RSHUDWLRQDUHXQSUHGLFWDEOH7RZULWH93'LQIRUPDWLRQWRWKHUHDGZULWHSRUWLRQRIWKH
93'VSDFHZULWHWKHGDWDWRWKH93''DWDUHJLVWHU7KHQZULWHWKHDGGUHVVRIZKHUHWKH
93'GDWDLVWREHVWRUHGLQWRWKH93'$GGUHVVUHJLVWHUDQGZULWHWKHIODJELWWRDRQHDW
289
Revision 2.2
WKHWLPHWKHDGGUHVVLVZULWWHQ7KHVRIWZDUHWKHQPRQLWRUVWKHIODJELWDQGZKHQLWLV
VHWWR]HURE\GHYLFHKDUGZDUHWKH93'GDWDDOOE\WHVKDVEHHQWUDQVIHUUHGIURPWKH
93''DWDUHJLVWHUWRWKHVWRUDJHFRPSRQHQW,IHLWKHUWKH93'$GGUHVVRU93''DWD
UHJLVWHULVZULWWHQSULRUWRWKHIODJELWEHLQJVHWWRD]HURWKHUHVXOWVRIWKHZULWH
RSHUDWLRQWRWKHVWRUDJHFRPSRQHQWDUHXQSUHGLFWDEOH
93''DWD²93'GDWDFDQEHUHDGWKURXJKWKLVUHJLVWHU7KHOHDVWVLJQLILFDQWE\WHRI
WKLVUHJLVWHUDWRIIVHWLQWKLVFDSDELOLW\VWUXFWXUHFRUUHVSRQGVWRWKHE\WHRI93'DWWKH
DGGUHVVVSHFLILHGE\WKH93'$GGUHVVUHJLVWHU7KHGDWDUHDGIURPRUZULWWHQWRWKLV
UHJLVWHUXVHVWKHQRUPDO3&,E\WHWUDQVIHUFDSDELOLWLHV)RXUE\WHVDUHDOZD\VWUDQVIHUUHG
EHWZHHQWKLVUHJLVWHUDQGWKH93'VWRUDJHFRPSRQHQW5HDGLQJRUZULWLQJGDWDRXWVLGH
RIWKH93'VSDFHLQWKHVWRUDJHFRPSRQHQWLVQRWDOORZHG7KH93'ERWKWKHUHDGRQO\
LWHPVDQGWKHUHDGZULWHILHOGVLVVWRUHGLQIRUPDWLRQDQGZLOOKDYHQRGLUHFWFRQWURORI
DQ\GHYLFHRSHUDWLRQV7KHLQLWLDOYDOXHRIWKLVUHJLVWHUDWSRZHUXSLVLQGHWHUPLQDWH
7KH93'$GGUHVVILHOGLVDE\WHDGGUHVVEXWPXVWVSHFLI\D':25'DOLJQHGORFDWLRQ
LHWKHERWWRPWZRELWVPXVWEH]HUR
(YHU\ERDUGPD\FRQWDLQ93':KHQD3&,H[SDQVLRQERDUGFRQWDLQVPXOWLSOHGHYLFHV
93'LISURYLGHGLVUHTXLUHGRQRQO\RQHRIWKHPEXWPD\EHLQFOXGHGLQHDFK3&,
GHYLFHVGHVLJQHGH[FOXVLYHO\IRUXVHRQWKHV\VWHPERDUGPD\DOVRVXSSRUWWKHRSWLRQDO
93'UHJLVWHUV
93'LQD3&,H[SDQVLRQERDUGXVHVWZRRIWKHSUHGHILQHGWDJLWHPQDPHVSUHYLRXVO\
GHILQHGLQWKH3OXJDQG3OD\,6$6SHFLILFDWLRQDQGWZRQHZRQHVGHILQHGVSHFLILFDOO\IRU
3&,93'7KH3Q3,6$WDJLWHPQDPHVWKDWDUHXVHGDUH,GHQWLILHU6WULQJ[IRUD
/DUJH5HVRXUFH'DWD7\SHDQG(QG7DJ[)IRUD6PDOO5HVRXUFH'DWD7\SH7KH
QHZODUJHUHVRXUFHLWHPQDPHVIRU93'DUH93'5ZLWKDYDOXHRI[IRUUHDGRQO\
GDWDDQG93':ZLWKDYDOXHRI[IRUUHDGZULWHGDWD
9LWDO3URGXFW'DWDLVPDGHXSRI6PDOODQG/DUJH5HVRXUFH'DWD7\SHVDVGHVFULEHGLQ
WKH3OXJDQG3OD\,6$6SHFLILFDWLRQ9HUVLRQD8VHRIWKHVHGDWDVWUXFWXUHVDOORZV
OHYHUDJLQJRIGDWDW\SHVDOUHDG\IDPLOLDUWRWKHLQGXVWU\DQGPLQLPL]HVWKHDPRXQWRI
DGGLWLRQDOUHVRXUFHVQHHGHGIRUVXSSRUW7KLVGDWDIRUPDWFRQVLVWVRIDVHULHVRI³WDJJHG´
GDWDVWUXFWXUHV7KHGDWDW\SHVIURPWKH3OXJDQG3OD\,6$6SHFLILFDWLRQ9HUVLRQD
DUHUHSURGXFHGLQWKHIROORZLQJILJXUHV
Offset
Field Name
Byte 0
Value = 0xxxxyyyb (Type = Small(0), Small Item Name = xxxx,
length = yy bytes
Bytes 1 to n
Actual information
)LJXUH,6PDOO5HVRXUFH'DWD7\SH7DJ%LW'HILQLWLRQV
290
Revision 2.2
Offset
Field Name
Byte 0
Value = 1xxxxxxxB (Type = Large(1), Large item name =
xxxxxxx)
Byte 1
Length of data items bits[7:0] (lsb)
Byte 2
Length of data items bits[15:8] (msb)
Byte 3 to n
Actual data items
)LJXUH,/DUJH5HVRXUFH'DWD7\SH7DJ%LW'HILQLWLRQV
7KH,GHQWLILHU6WULQJ[WDJLVWKHILUVW93'WDJDQGSURYLGHVWKHSURGXFWQDPHRIWKH
GHYLFH2QH93'5[WDJLVXVHGDVDKHDGHUIRUWKHUHDGRQO\NH\ZRUGVDQGRQH
93':[WDJLVXVHGDVDKHDGHUIRUWKHUHDGZULWHNH\ZRUGV7KH93'5OLVW
LQFOXGLQJWDJDQGOHQJWKPXVWFKHFNVXPWR]HUR7KHVWRUDJHFRPSRQHQWFRQWDLQLQJ
WKHUHDGZULWHGDWDLVDQRQYRODWLOHGHYLFHWKDWZLOOUHWDLQWKHGDWDZKHQSRZHUHGRII
$WWHPSWVWRZULWHWKHUHDGRQO\GDWDZLOOEHH[HFXWHGDVDQRRS7KHODVWWDJPXVWEH
WKH(QG7DJ[)$VPDOOH[DPSOHRIWKHUHVRXUFHGDWDW\SHWDJVXVHGLQDW\SLFDO
93'LVVKRZQLQ)LJXUH,
TAG
Identifier String
TAG
VPD-R list containing one or more VPD
keywords
TAG
VPD-W list containing one or more VPD
keywords
TAG
End Tag
)LJXUH,5HVRXUFH'DWD7\SH)ODJVIRUD7\SLFDO93'
291
Revision 2.2
I.1. VPD Format
,QIRUPDWLRQILHOGVZLWKLQD93'UHVRXUFHW\SHFRQVLVWRIDWKUHHE\WHKHDGHUIROORZHGE\
VRPHDPRXQWRIGDWDVHH)LJXUH,7KHWKUHHE\WHKHDGHUFRQWDLQVDWZRE\WH
NH\ZRUGDQGDRQHE\WHOHQJWK
$NH\ZRUGLVDWZRFKDUDFWHU$6&,,PQHPRQLFWKDWXQLTXHO\LGHQWLILHVWKHLQIRUPDWLRQ
LQWKHILHOG7KHODVWE\WHRIWKHKHDGHULVELQDU\DQGUHSUHVHQWVWKHOHQJWKYDOXHLQ
E\WHVRIWKHGDWDWKDWIROORZV
Keyword
Byte 0
Byte 1
Length
Data
Byte 2
Bytes 3 through n
)LJXUH,93')RUPDW
93'NH\ZRUGVDUHOLVWHGLQWZRFDWHJRULHVUHDGRQO\ILHOGVDQGUHDGZULWHILHOGV
8QOHVVRWKHUZLVHQRWHGNH\ZRUGGDWDILHOGVDUHSURYLGHGDV$6&,,FKDUDFWHUV8VHRI
$6&,,DOORZVNH\ZRUGGDWDWREHPRYHGDFURVVGLIIHUHQWHQWHUSULVHFRPSXWHUV\VWHPV
ZLWKRXWWUDQVODWLRQGLIILFXOW\$QH[DPSOHRIWKH³H[SDQVLRQERDUGVHULDOQXPEHU´93'
LWHPLVDVIROORZV
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61
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I.2. VPD Compatibility
2SWLRQDO93'ZDVVXSSRUWHGLQSULRUYHUVLRQVRIWKLVVSHFLILFDWLRQ)RULQIRUPDWLRQRQ
WKHSUHYLRXVGHILQLWLRQRI93'VHH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQ
I.3. VPD Definitions
7KLVVHFWLRQGHVFULEHVWKHFXUUHQW93'ODUJHDQGVPDOOUHVRXUFHGDWDWDJVSOXVWKH93'
NH\ZRUGV7KLVOLVWPD\EHHQKDQFHGDWDQ\WLPH&RPSDQLHVZLVKLQJWRGHILQHDQHZ
NH\ZRUGVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHGIRU6,*
DVVLJQPHQW
292
Revision 2.2
I.3.1. VPD Large and Small Resource Data Tags
93'LVFRQWDLQHGLQIRXUW\SHVRI/DUJHDQG6PDOO5HVRXUFH'DWD7DJV7KHIROORZLQJ
WDJVDQG93'NH\ZRUGILHOGVPD\EHSURYLGHGLQ3&,GHYLFHV
Large resource type Identifier
String Tag
(0x2)
This tag is the first item in the VPD storage
component. It contains the name of the board in
alphanumeric characters.
Large resource type VPD-R
Tag
(0x10)
This tag contains the read only VPD keywords for a
board.
Large resource type VPD-W
Tag
(0x11)
This tag contains the read/write VPD keywords for
the board.
Small resource type End Tag
(0xF)
This tag identifies the end of VPD in the storage
component.
I.3.1.1. Read-Only Fields
PN
Board Part Number
This keyword is provided as an extension to the
Device ID (or Subsystem ID) in the Configuration
Space header in Figure 6-1.
EC
EC Level of the Board
The characters are alphanumeric and represent the
engineering change level for this board.
MN
Manufacture ID
This keyword is provided as an extension to the
Vendor ID (or Subsystem Vendor ID) in the
Configuration Space header in Figure 6-1. This
allows vendors the flexibility to identify an
additional level of detail pertaining to the sourcing of
this device.
SN
Serial Number
The characters are alphanumeric and represent the
unique board Serial Number.
Vx
Vendor Specific
This is a vendor specific item and the characters are
alphanumeric. The second character (x) of the
keyword can be 0 through Z.
293
Revision 2.2
CP
Extended Capability
This field allows a new capability to be identified in
the VPD area. Since dynamic control/status cannot
be placed in VPD, the data for this field identifies
where, in the device’s memory or I/O address space,
the control/status registers for the capability can be
found. Location of the control/status registers is
identified by providing the index (a value between 0
and 5) of the Base Address register that defines the
address range that contains the registers, and the
offset within that Base Address register range where
the control/status registers reside. The data area for
this field is four bytes long. The first byte contains
the ID of the extended capability. The second byte
contains the index (zero based) of the Base Address
register used. The next two bytes contain the offset
(in little endian order) within that address range
where the control/status registers defined for that
capability reside.
RV
Checksum and
Reserved
The first byte of this item is a checksum byte. The
checksum is correct if the sum of all bytes in VPD
(from VPD address 0 up to and including this byte)
is zero. The remainder of this item is reserved space
(as needed) to identify the last byte of read-only
space. The read-write area does not have a
checksum. This field is required.
I.3.1.2 Read/Write Fields
294
Vx
Vendor Specific
This is a vendor specific item and the characters
are alphanumeric. The second character (x) of
the keyword can be 0 through Z.
Yx
System Specific
This is a system specific item and the characters
are alphanumeric. The second character (x) of
the keyword can be 0 through 9 and B through
Z.
YA
Asset Tag Identifier
This is a system specific item and the characters
are alphanumeric. This keyword contains the
system asset identifier provided by the system
owner.
RW
Remaining Read/Write
Area
This descriptor is used to identify the unused
portion of the read/write space. The product
vendor initializes this parameter based on the
size of the read/write space or the space
remaining following the Vx VPD items. One or
more of the Vx, Yx, and RW items are required.
Revision 2.2
I.3.2. VPD Example
The following is an example of a typical VPD.
Offset
Item
Value
0
Large Resource Type ID String Tag
(0x02)
0x82 “Product Name”
1
Length
0x0021
3
Data
“ABCD Super-Fast
Widget Controller”
36
Large Resource Type VPD-R Tag (0x10)
0x90
37
Length
0x0059
39
VPD Keyword
“PN”
41
Length
0x08
42
Data
“6181682A”
50
VPD Keyword
“EC”
52
Length
0x0A
53
Data
“4950262536”
63
VPD Keyword
“SN”
65
Length
0x08
66
Data
“00000194”
74
VPD Keyword
“MN”
76
Length
0x04
77
Data
“1037”
81
VPD Keyword
“RV”
83
Length
0x2C
84
Data
Checksum
85
Data
Reserved (0x00)
295
Revision 2.2
296
Offset
Item
Value
128
Large Resource Type VPD-W Tag (0x11)
0x91
129
Length
0x007E
131
VPD Keyword
“V1”
133
Length
0x05
134
Data
“65A01”
139
VPD Keyword
“Y1”
141
Length
0x0D
142
Data
“Error Code 26”
155
VPD Keyword
“RW”
157
Length
0x61
158
Data
Reserved (0x00)
255
Small Resource Type End Tag (0xF)
0x78
Revision 2.2
Glossary
64-bit extension
A group of PCI signals that support a 64-bit data path.
Address Spaces
A reference to the three separate physical address
regions of PCI: Memory, I/O, and Configuration.
agent
An entity that operates on a computer bus.
arbitration latency
The time that the master waits after having asserted
REQ# until it receives GNT#, and the bus returns to
the idle state after the previous master’s transaction.
backplate
The metal plate used to fasten an expansion board to
the system chassis.
BIST register
An optional register in the header region used for
control and status of built-in self tests.
bridge
The logic that connects one computer bus to another,
allowing an agent on one bus to access an agent on
the other.
burst transfer
The basic bus transfer mechanism of PCI. A burst is
comprised of an address phase and one or more data
phases.
bus commands
Signals used to indicate to a target the type of
transaction the master is requesting.
bus device
A bus device can be either a bus master or target:
catastrophic error
•
master -- drives the address phase and transaction
boundary (FRAME#). The master initiates a
transaction and drives data handshaking (IRDY#)
with the target.
•
target -- claims the transaction by asserting
DEVSEL# and handshakes the transaction
(TRDY#) with the initiator.
An error that affects the integrity of system operation
such as a detected address parity error or an invalid
PWR_GOOD signal.
297
Revision 2.2
298
central resources
Bus support functions supplied by the host system,
typically in a PCI compliant bridge or standard
chipset.
command
See bus command.
Configuration Address Space
A set of 64 registers (DWORDs) used for
configuration, initialization, and catastrophic error
handling. This address space consists of two regions:
a header region and a device-dependent region.
configuration transaction
Bus transaction used for system initialization and
configuration via the configuration address space.
DAC
Dual address cycle. A PCI transaction where a 64-bit
address is transferred across a 32-bit data path in two
clock cycles. See also SAC.
deadlock
When two devices (one a master, the other a target)
require the other device to respond first during a
single bus transaction. For example, a master
requires the addressed target to assert TRDY# on a
write transaction before the master will assert IRDY#.
(This behavior is a violation of this specification.)
Delayed Transaction
The process of a target latching a request and
completing it after the master was terminated with
Retry.
device
See PCI device.
device dependent region
The last 48 DWORDS of the PCI configuration space.
The contents of this region are not described in this
document.
Discard Timer
When this timer expires, a device is permitted to
discard unclaimed Delayed Completions (refer to
Section 3.3.3.3.3. and Appendix E).
DWORD
A 32-bit block of data.
EISA
Extended Industry Standard Architecture expansion
bus, based on the IBM PC AT bus, but extended to 32
bits of address and data.
expansion board
A circuit board that plugs into a motherboard and
provides added functionality.
expansion bus bridge
A bridge that has PCI as its primary interface and
ISA, EISA, or Micro Channel as its secondary
interface. This specification does not preclude the use
of bridges to other buses, although deadlock and other
system issues for those buses have not been
considered.
Function
A set of logic that is represented by a single
Configuration Space.
Revision 2.2
header region
The first 16 DWORDS of a device’s Configuration
Space. The header region consists of fields that
uniquely identify a PCI device and allow the device to
be generically controlled.
See also device dependent region.
hidden arbitration
Arbitration that occurs during a previous access so
that no PCI bus cycles are consumed by arbitration,
except when the bus is idle.
host bus bridge
A low latency path through which the processor may
directly access PCI devices mapped anywhere in the
memory, I/O, or configuration address spaces.
Idle state
Any clock period that the bus is idle (FRAME# and
IRDY# deasserted).
Initialization Time
The period of time that begins when RST# is
25
deasserted and completes 2 PCI clocks later.
ISA
Industry Standard Architecture expansion bus built
into the IBM PC AT computer.
keepers
Pullup resistors or active components that are only
used to sustain a signal state.
latency
See arbitration latency, master data latency, target
initial latency, and target subsequent latency.
Latency Timer
A mechanism for ensuring that a bus master does not
extend the access latency of other masters beyond a
specified value.
master
An agent that initiates a bus transaction.
Master-Abort
A termination mechanism that allows a master to
terminate a transaction when no target responds.
master data latency
The number of PCI clocks until IRDY# is asserted
from FRAME# being asserted for the first data phase
or from the end of the previous data phase.
MC
The Micro Channel architecture expansion bus as
defined by IBM for its PS/2 line of personal
computers.
motherboard
A circuit board containing the basic functions (e.g.,
CPU, memory, I/O, and expansion connectors) of a
computer.
multi-function device
A device that implements from two to eight functions.
Each function has its own Configuration Space that is
addressed by a different encoding of AD[10::08]
during the address phase of a configuration
transaction.
299
Revision 2.2
300
multi-master device
A single-function device that contains more than one
source of bus master activity. For example, a device
that has a receiver and transmitter that operate
independently.
NMI
Non-maskable interrupt.
operation
A logical sequence of transactions, e.g., Lock.
output driver
An electrical drive element (transistor) for a single
signal on a PCI device.
PCI connector
An expansion connector that conforms to the
electrical and mechanical requirements of the PCI
local bus standard.
PCI device
A device that (electrical component) conforms to the
PCI specification for operation in a PCI local bus
environment.
PGA
Pin grid array component package.
phase
One or more clocks in which a single unit of
information is transferred, consisting of:
•
an address phase (a single address transfer in one
clock for a single address cycle and two clocks
for a dual address cycle)
•
a data phase (one transfer state plus zero or more
wait states)
positive decoding
A method of address decoding in which a device
responds to accesses only within an assigned address
range. See also subtractive decoding.
POST
Power-on self test. A series of diagnostic routines
performed when a system is powered up.
pullups
Resistors used to insure that signals maintain stable
values when no agent is actively driving the bus.
run time
The time that follows Initialization Time.
SAC
Single address cycle. A PCI transaction where a
32-bit address is transferred across a 32-bit data path
in a single clock cycle. See also DAC.
shared slot
An arrangement on a PCI motherboard that allows a
PCI connector to share the system bus slot nearest the
PCI bus layout with an ISA, EISA, or MC bus
connector. In an MC system, for example, the shared
slot can accommodate either an MC expansion board
or a PCI expansion board.
single-function device
A device that contains only one function.
sideband signals
Any signal not part of the PCI specification that
connects two or more PCI-compliant agents and has
meaning only to those agents.
Revision 2.2
Special Cycle
A message broadcast mechanism used for
communicating processor status and/or (optionally)
logical sideband signaling between PCI agents.
stale data
Data in a cache-based system that is no longer valid
and, therefore, must be discarded.
stepping
The ability of an agent to spread assertion of qualified
signals over several clocks.
subtractive decoding
A method of address decoding in which a device
accepts all accesses not positively decoded by another
agent. See also positive decoding.
target
An agent that responds (with a positive
acknowledgment by asserting DEVSEL#) to a bus
transaction initiated by a master.
Target-Abort
A termination mechanism that allows a target to
terminate a transaction in which a fatal error has
occurred, or to which the target will never be able to
respond.
target initial latency
The number of PCI clocks that the target takes to
assert TRDY# for the first data transfer.
target subsequent latency
The number of PCI clocks that the target takes to
assert TRDY# from the end of the previous data
phase of a burst.
termination
A transaction termination brings bus transactions to
an orderly and systematic conclusion. All
transactions are concluded when FRAME# and
IRDY# are deasserted (an idle cycle). Termination
may be initiated by the master or the target.
transaction
An address phase plus one or more data phases.
turnaround cycle
A bus cycle used to prevent contention when one
agent stops driving a signal and another agent begins
driving it. A turnaround cycle must last one clock
and is required on all signals that may be driven by
more than one agent.
wait state
A bus clock in which no transfer occurs.
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Revision 2.2
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