NGC
Detector Array Controller Based on
High Speed Serial Link Technology
[ IRDT and ODT ]
First Light
PICNIC Array Mux
Image of ESO
Messenger Front Page
M.Meyer
June 05
Conventional Approach :
Acquisition System (IRACE)
PCI
Interface
Communication
and Data Transfer
Acquisition
Module(s)
Sequencer
Clock and Bias
NGC Prototype - Minimum System
Back-End and Front-End ( Four Channels

NGC is a modular system for IR detector
and CCD readout with a Back-end, a basic
Front-end unit containing a complete four
channel system on one card and additional
boards like multi channel ADC units and
more...

There is no processor, no parallel intermodule data bus on the front-end side.
Advanced FPGA link technology is used to
replace conventional logic

Connection between Back and Front-end
with high speed fiber links at 2.5GBit/s

Connection between Front-end modules
with high speed copper links at 2.5GBit/s.

Power Consumption on this Front-end is
less than 10 Watts
( Excluding power supply )

This Front-End system does not require
big cooling boxes
)
System Noise on Prototype
1
4
2
3
VirtexII Pro
Contains :
PCI 64 IF (IP)
Communication
DMA Data
Transfer
Fiber optics
Back-End
Back-End

Function is based on the XILINX Virtex
Pro FPGA XC2VP7 FF 672

Back-End PCI is a 64 Bit PCI board

FPGA contains PCI interface to
Communication functions
DMA data channel
Status and Command




Direct interface from FPGA to PCI
without glue logic
PCI master and PCI slave are independent
Scatter – Gather DMA implemented
Communication and data transfers all on
serial link with RocketIO transceivers

Handshake communication to Front-End

Data rate on one channel between front
and back-end ~ 200MByte/s
Back-End
VIDEO FIFO
Header #01
Rx
PCI BUS
Interface
RX COM
#10
Header #02
Tx
XILINX IP
PCI REGISTERS
SLAVE IF
MASTER IF
DOWNSTREAM
LINK
TX COM
#10
STATUS REG
# 14
COMMAND REG
#1C
VirtexII
Pro
Acquisition
CLOCK
and BIAS
Contains
:
Monitoring
4 Channels
Communication
16/18 Bit
Data transfer
Telemetry
Sequencer
16 Bit
Telemetry
Glue logic
Front-End
Front-End
Front-End


Function is based on the XILINX Virtex Pro
FPGA XC2VP7 FF 672
FPGA contains link interface for
communication and data transfer with
RocketIO transceivers, sequencer, system
administration, interface to acquisition,
clock and bias, telemetry and monitoring

Four ADC channels ( 16 or 18Bit)

16 clocks, 20 biases

Telemetry

Monitoring

Data rate on one channel between front-end
modules and front to back-end ~ 200MByte

Handshake for communication to back-end


Galvanic isolated trigger input and control
outputs
Connection to detector ASIC’s - all
communication and data transfer to the
back-end can be handled with the same
firmware already contained in the FPGA
On Board
ADCs
AQ FIFO
DOWNSTREAM
RX LINK
AQ FIFO 1
Rx
SEQUENCER
AQ MANAGER
STATUS REG
CLOCK and BIAS
UPSTREAM
TX LINK
Tx
MONITOR
TX COM
TELEMETRY
COM
IF
Rx
NEXT LINK
IF
UPSTREAM
RX LINK
Tx
SYSTEM RESET
CONFIG
REGISTER
LINK CONFIG
DOWNSTREAM
TX LINK
Virtex Pro Internals
Device utilization summary: Selected Device : 2vp7ff672-5
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of bonded IOBs:
Number of TBUFs:
Number of BRAMs:
Number of GCLKs:
Number of GTs:
Number of DCMs:
Signals to route :
Used language : VHDL
22530
2508 out of
3043 out of
4190 out of
124 out of
160 out of
25 out of
3 out of
4 out of
1 out of
4928
9856
9856
396
2720
44
16
8
4
50%
30%
42%
31%
5%
56%
18%
50%
25%
Communication and Data Transfer





Communication and data
transfer is handled with the
Virtex Pro FPGA’s Gigabit
transceivers
LINK COMMUNICATION
PRINCIPLE
The communication between
all system modules is based
on packet transmission over
serial links
A packet structure is
defined to address a
function ( e.g. a register or
memory in a front-end
module) for read or write
From the Back-End ( PCI
board ) the packets can be
routed to and through each
board in the Front-End
Data are routed with the
same structure from the
acquisition modules to the
Back-End
Board 1
Data
Packet
from
BackEnd
Rx
Board 2
FUNCTION
# ADDR
FUNCTION
# ADDR
RX COM
RX COM
HEADER #2
HEADER #2
NEXT LINK
Tx
Rx
HEADER #5
NEXT LINK
Tx
HEADER #5
PACKET STRUCTURE
WRITE
DATA
TO
ADDRESS
… | DATA | DATA | WRITE | ADDR | … | HEADER2 | HEADER1
OPTIONAL
READ n
WORDS
FROM
ADDRESS
READ n WORDS | ADDR | … | HEADER2 | HEADER1
OPTIONAL
Applications
and Architectures
Basic System
Basic System
Front-End
Front-End
Basic
Module
FPGA
Signal
Clock
Bias
Back-End
Fiber
Duplex
Connection
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
More Bandwidth
Front-End
Front-End
Basic
Module
FPGA
Signal
Clock
Bias
Back-End
Fiber
Duplex
Connection
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
More Clocks, Biases / Two Detectors synchronized …
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
FPGA
Signal
Clock
Bias
Serial
Links
On
Backplane
Front-End
Basic
Module
RxTx
RxTx
FPGA
Signal
Clock
Bias
Back-End PCI
PCI
FPGA
More AQ Channels
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
FPGA
Signal
Clock
Bias
Serial
Links
On
Backplane
Front-End
AQ 32 CH
3232Modul
e
RxTx
RxTx
FPGA
Signal
Back-End PCI
PCI
FPGA
More Bandwidth and Different Routing
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
FPGA
Signal
Clock
Bias
Serial
Links
On
Backplane
Back-End PCI
Front-End
AQ 32 CH
3232Modul
e
FPGA
Signal
RxTx
RxTx
RxTx
RxTx
FPGA
Even more channels
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
FPGA
Signal
Clock
Bias
Serial
Links
On
Backplane
Back-End PCI
Front-End
AQ 32 CH
3232Modul
e
RxTx
RxTx
RxTx
RxTx
FPGA
Signal
Front-End
AQ 32 CH
Module
RxTx
RxTx
FPGA
Signal
FPGA
Route to Dedicated Interfaces
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
FPGA
Signal
Clock
Bias
Dedicated IF
Serial
Links
On
Backplane
Front-End
AQ 32 CH
3232Modul
e
FPGA
Signal
RxTx
RxTx
RxTx
RxTx
Adaptive Optics
Interferometry
….
FPGA
Distribute/Copy Data
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
FPGA
Signal
Clock
Bias
Applications
Serial
Links
On
Backplane
Data
Distribution
Switch
RxTx
RxTx
RxTx
FPGA
RxTx
RxTx
RxTx
Front-End
AQ 32 CH
3232Modul
e
RxTx
RxTx
FPGA
Signal
Collecting /Routing /Preprocessing
Front-End
Back-End
Fiber
Duplex
Connection
Front-End
Basic
Module
RxTx
RxTx
RxTx
RxTx
Back-End PCI
PCI
FPGA
FPGA
Signal
Clock
Bias
Data Sources
Serial
Links
On
Backplane
Data
Distribution
Switch
RxTx
RxTx
RxTx
FPGA
RxTx
RxTx
RxTx
NGC
Detector Array Controller Based on
High Speed Serial Link Technology
Two Posters on the same Topic
NGC Front-end for CCDs and AO applications - Javier Reyes
Software for the New Generation Detector Controller - Claudio Cumani
M.Meyer
June 05
Engineers
Bad Days
or
The Real
World
How many Errors will be on ?
It’s a 10 Layer board with BGA’s !
Virtex BGA - One Connection too much
Virtex BGA - Missing Connection
Front-End Basic Board
Sequencer Module

Sequencer is completely
contained within the FPGA
 100MHz design = 10ns
resolution
SEQUENCER
STATUS REG
# 6000
COMMAND REG
# 6000
PATTERN RAM
 Firmware interpreter for
Sequencer Codes within
the FPGA
 Galvanic isolated high
speed trigger input and
control outputs
SEQ RAM
#4000
SEQ CODE
INTERPRETER
PATTERN
ADDR FIFO
REPETITION
COUNTER
Sequencer Codes
000 Stop Interpreter
 Stops Pattern Interpretation
001 EXEC Pattern < Number of Pattern, Number of Repetitions >
010 LOOP
< Number of Repetitions >
011 LOOP END
100 LOOP INFINITE
101 JUMP SUBROUTINE < Address >
110 RETURN SUBROUTINE
111 Reserved
LOW HIGH
#4800
#5000
TIME
COUNTER
ADDRESS
COUNTER