Timing issues
Why we should check timing ?
RTL Transfer
add <= a + b;
Logic level
Physical device
Should meet
the device
specifications
What is setup ? What is hold ?
Setup
Hold
Logic
clock
clock
clock
The “window” on which
the input data
should be stable !!!
Timing Conditions: Set-up
Give enough time to sample the data then close pass gate
weak inverter
D
q
CLK
Q#
Timing Conditions: Hold Time
Give enough time to close pass gate then change data
weak inverter
D
q
CLK
Q#
Timing conditions: Summary
SU
CLK
DATA
Hold
Setup checks
Setup: 1ns
1ns
4ns
1ns
2ns
3ns
clock
clock
1 2
clock
4
1
10ns
3
1
Setup checks (cont.)
T setup
Logic
Output delay
+ Propagation delay
+ Setup time
clock
< Cycle time
T cycle
clock
clock
Setup relationship is
from the 1st edge of the clock
in the “launch” flip-flop to the
subsequent capture edge of the clock
within the “receive” flip-flop
Setup checks : critical path
Setup: 1ns
4ns
8ns
1ns
12ns
clock
The critical path
for setup checks
is the longest path
10ns
clock 1
clock
4
8
12
1
Hold checks
Hold: 1ns
0.3ns
clock
clock
.3
clock
1
10ns
Hold checks (cont.)
T hold
Output delay
+ Propagation delay
- Hold time
clock
>0
Cycle time
clock
clock
Hold relationship is
between the release edge of
the “launch” clock
to the “receive” clock
preceding the setup check
Hold checks : Critical path
4ns
Hold: 1ns
0.7ns
0.3ns
clock
10ns
clock
.3
.7
clock
1
4
The critical path
for hold checks
is the shortest path
Setup -> Max delay
Hold -> Min delay
T setup
Logic
Max Output delay
Setup
+ Max Propagation delay Max
+ Setup time
< Cycle time
clock
T hold
Min Output delay
+ Min Propagation delay
- Hold time
clock
>0
Hold
Min
Timing exceptions
Control
Logic
Clk#1
Clk#1
Clk#1
Clk#1
Multi-cycle
path
Timing exceptions (cont.)
Control
Logic
Clk#2
Clk#1
Clk#1
Clk#2
False path
Modeling a non-ideal clock
clock
#2
Clk#1
#1
??
Clk#1
Clk#2
Clk#2
clock
Setup checks with a non-ideal clock
T setup
Output delay
+ Propagation delay
Logic
+ Setup time
clock
T cycle
clock
clock
< Cycle time
- Clock delay
Hold checks with a non-ideal
clock
T hold
Output delay
+ Propagation delay
- Hold time
clock
>0
+ Clock delay
Cycle time
clock
clock